228 results on '"Gabriel H. Loh"'
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2. AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization.
3. A Research Retrospective on AMD's Exascale Computing Journey.
4. The Next Era for Chiplet Innovation.
5. AMD InstinctTM MI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture.
6. Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources.
7. Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product.
8. Analyzing and Leveraging Decoupled L1 Caches in GPUs.
9. Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits.
10. Analyzing and Leveraging Shared L1 Caches in GPUs.
11. Experiences with ML-Driven Design: A NoC Case Study.
12. Modular Routing Design for Chiplet-Based Systems.
13. Scheduling Page Table Walks for Irregular GPU Applications.
14. Generic System Calls for GPUs.
15. Challenges of High-Capacity DRAM Stacks and Potential Directions.
16. A New Era of Tailored Computing.
17. Accelerating Variational Quantum Algorithms Using Circuit Concurrency.
18. Cost-effective design of scalable high-performance systems using active and passive interposers.
19. There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes.
20. Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries.
21. Design and Analysis of an APU for Exascale Computing.
22. MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories.
23. CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems.
24. OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures.
25. Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.
26. μC-States: Fine-grained GPU Datapath Power Management.
27. Efficient synthetic traffic models for large, complex SoCs.
28. Observations and opportunities in architecting shared virtual memory for heterogeneous systems.
29. HpMC: An Energy-aware Management System of Multi-level Memory Architectures.
30. Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems.
31. Large pages and lightweight memory management in virtualized environments: can you have it both ways?
32. Enabling interposer-based disintegration of multi-core processors.
33. A Software-Managed Approach to Die-Stacked DRAM.
34. Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance.
35. Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories.
36. Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors.
37. A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate.
38. Efficient RAS support for die-stacked DRAM.
39. Managing GPU Concurrency in Heterogeneous Architectures.
40. NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
41. Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache.
42. Design and Evaluation of Hierarchical Rings with Deflection Routing.
43. Toward efficient programmer-managed two-level memory hierarchies in exascale computers.
44. Managing DRAM Latency Divergence in Irregular GPGPU Applications.
45. Increasing TLB reach by exploiting clustering in page translations.
46. Last-level cache deduplication.
47. Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory.
48. Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance.
49. High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems.
50. Achieving Exascale Capabilities through Heterogeneous Computing.
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