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The reconstruction of 4°off 4H-SiC surfaces was investigated using Si melting at 1550°C in a SiC/Si/SiC sandwich configuration. Despite systematically obtaining a macrostepped morphology over the entire areas in contact with the liquid Si, the steps were found wavy when using as-received 4H-SiC wafers. The regularity and straightness of the steps were significantly improved when the surface reconstruction was performed on processed surfaces: on re-polished surfaces the steps were found to be regular and straight in some cases, while this was constantly observed on as-grown epitaxial layers. After a reconstruction process of 2h, the best regularity of the steps was obtained with an average width of ̴ 3-5 μm. Increasing the processed area from 1.44 to 4 cm2 did not affect the results which suggests a good scalability of the process.

4H-SiC/Si(liq)/4H-SiC stacks were treated at 1550-1600°C under H2 in a RF-heated cold-wall reactor in order to generate macrosteps-structuring of the 4°off SiC(0001) wafers. Using 400 μm thick liquid Si, the observed important matter transport from the edges to the center of the same wafer was attributed to RF-induced convection rolls inside the thick liquid Si. When the liquid thickness was reduced down to 30 μm, the matter transport followed this time the vertical thermal gradient like in the case of liquid phase epitaxy. The dissolution rate of the bottom (hotter) wafer was found to increase from 1.7 μm/h at 1550°C to 3.3 μm/h at 1600°C. The use of H2 gas was found essential to the system since it does not generate gas trapping (unlike Ar) and it participates to the creation of the vertical thermal gradient.

Scanning tunneling luminescence microscopy (STLM) along with scanning tunneling spectroscopy (STS) is applied to a step-bunched, oxidized 4H-SiC surface prepared on the silicon face of a commercial, n-type SiC wafer using a silicon melt process. The step-bunched surface consists of atomically smooth terraces parallel to the [0001] crystal planes, and rougher risers consisting of nanoscale steps formed by the termination of these planes. The rather striking topography of this surface is well resolved with large tip biases of the order of -8 V and set currents of magnitude less than 1 nA. Hysteresis in the STS spectra is preferentially observed on the risers suggesting that they contain a higher density of surface charge traps than the terraces where hysteresis is more frequently absent. Similarly, at 50 K intense sub-gap light emission centered around 2.4 eV is observed mainly on the risers albeit only with larger tunneling currents of magnitude equal to or greater than 10 nA. These results demonstrate that STLM holds great promise for the observation of impurities and defects responsible for sub-gap light emission with spatial resolutions approaching the length scale of the defects themselves., Comment: 13 pages, 5 figures; work presented at the International Conference on the Physics of Semiconductors, Sydney, 2022

This work investigates the 3C-SiC heteroepitaxial growth on silicon substrates having a wide variety of orientations, i.e. (100) on axis and 2°off, (111), (110), (211), (311), (331), (510), (553) and (995). All the 3C-SiC layers were grown using the same two-step CVD process with a growth rate of 2 μm/h. According to X-ray diffraction characterizations, direct heteroepitaxy (layer having exactly the same orientation as the substrate) was successful on most of the Si substrates except for (110) one which was the only orientation leading to obvious polycrystalline deposit. Each layer led to a specific surface morphology, the smoothest being the ones grown on Si (100)2°off, and (995) substrates. None of these layers cracked upon cooling though those grown on Si (111), (211) and (553) substrates were highly bowed.

Comumente encontramos estudantes que adotam uma postura passiva, com pouca participação em discussões sobre o conteúdo. A esse cenário estão associados os métodos de ensino tradicional, caracterizado por aulas expositivas. Nesse contexto, surgiram metodologias que buscam consolidar o saber. O TBL (Team Based Learning), é um elemento motivacional para o estudo, uma vez que exige a aplicação dos conhecimentos adquiridos individualmente.

International audience; This paper review the research works made so far in associating Ge isoelectronic element to SiC crystals, either by incorporating it inside SiC matrix or for assisting SiC epitaxial growth. The incorporation mechanism and level of incorporation of Ge in SiC during crystal growth with different techniques (sublimation, chemical vapor deposition, vapor-liquid-solid) are compared and discussed. Ge doping level as high as 2-3x10 20 at.cm-3 can be reached without affecting SiC crystalline quality but generating some strain. Higher Ge incorporation levels up to few at% can be reached using farer-toequilibrium conditions such as ion implantation or molecular beam epitaxy. The former allows retaining 4H-SiC polytype while the latter leads exclusively to defective 3C-SiC polytype. Adding Ge to SiC crystal growth was also used for promoting 3C-SiC heteroepitaxy on Si and on -SiC substrates, the latter case being more successful. The reported modifications and improvements of SiC crystalline and electronic properties by the incorporation of Ge element are discussed in order to draw or clearer picture of SiC:Ge material. Based on such discussion, some short-and long-term perspectives are proposed

International audience; Because the well-known site-competition and step-controlled epitaxy rules cannot reasonably describe all the incorporation processes of the main impurities (Al and N) into 4H-SiC during epitaxy, the concept of replacement incorporation was proposed and applied to explain the experimental results published so far. In this model, the transient formation of C or Si vacancies at the surface or sub-surface of terraces is proposed to play a key role by destabilizing the impurities sitting on them. In addition to the availability of these vacancies at the surface, desorption was proposed to be a very important limiting process for Al incorporation while only occasionally relevant for N incorporation. The main 4H-SiC epitaxial growth parameters are reviewed and discussed according to the proposed replacement model. Introduction.

We report for the first time the successful heteroepitaxial growth of Si(100) oriented layer on top of a 3C-SiC(001) seed. By using a post-growth modification of the 3C-SiC surface (pulse insertion of precursors during cooling), it led to a change in Si nucleation, favoring squared (100) islands instead of elongated (110) ones. Without this surface modification step, the Si layers grown on 3C-SiC were always polycrystalline with a mixture of (110) and (100) orientations. Using such Si(100) layer grown on top of 3C-SiC(100), a (100) oriented 3C-SiC single crystalline layer was successfully grown on top, fabricating thus for the first time a fully (100) oriented multilayer heterostructure made of Si(substrate)/SiC/Si/SiC.

The (001) surface of cubic silicon carbide (3C SiC) after cleaning, Ar sputtering and three different wet chemical etching procedures was thoroughly investigated via (angle resolved) XPS, HREELS, and LEED. While Ar sputtering was found to be unsuitable for surface preparation, all three employed wet chemical etching procedures (piranha/NH4F, piranha/HF, and RCA) provide a clean surface. HF as oxide removal agent tends to result in fluorine traces on the sample surface, despite thorough rinsing. All procedures yield a 1 × 1 Si–OH/C–H terminated surface. However, the XPS spectra reveal some differences in the resulting surface states. NH4F for oxide removal produces a flat band situation, whereas the other two procedures result in a slight downward (HF) or upward (RCA) band bending. Because the band bending is small, it can be concluded that the number of unsaturated surface defects is low.

Low temperature (500–800 °C) homoepitaxy of not intentionally doped GaN structures on GaN(0 0 0 1)/Si(1 1 1) seed has been investigated by Vapor-Liquid-Solid (VLS) approach. The growth sequence consists in the metalorganic chemical vapor deposition of a network of submicrometric liquid Ga droplets, followed by their nitridation under flowing ammonia diluted either in H 2 or Ar. When nitridation is performed under Ar carrier gas, GaN growth is very difficult to control due to too high N supersaturation within the droplets, despite very low NH 3 flows. Nucleation and growth at the droplets periphery are always favored and, in most cases, high growth rates induce a crust-like growth, forming hollow GaN gangues. The use of H 2 as carrier gas is detrimental to GaN (seed and grown material) stability, for nitridation temperatures ≥700 °C. But, compared to Ar atmosphere, a pronounced decrease of N supersaturation is demonstrated, allowing a better control of the growth mode. This is probably a consequence of a lower thermal decomposition efficiency of NH 3 at the droplets surface. Optimal growth conditions are found at relatively low temperature (600 °C) and NH 3 flow (20 sccm) for which a network of well-separated and faceted epitaxial GaN dots or rings is obtained. The growth mechanisms allowing these results are discussed.

This study deals with the electrical characterization of PiN diodes fabricated on a 4°off-axis 4H-SiC n+ substrate with a n- epilayer (1×1016 cm-3 / 10 µm). Optimized p++ epitaxial areas were grown by Vapour-Liquid-Solid (VLS) transport to form p+ emitters localized in etched wells with 1 µm depth. Incorporated Al level in the VLS p++ zones was checked by SIMS (Secondary Ion Mass Spectroscopy), and the doping level was found in the range of 1-3×1020 at.cm-3. Electrical characterizations were performed on these PiN diodes, with 800 nm deposit of aluminium as ohmic contact on p-type SiC. Electrical measurements show a bipolar behaviour, and very high sustainable forward current densities ≥ 3 kA.cm-2, preserving a low leakage current density in reverse bias. These measurements were obtained on structures without any passivation and no edge termination.

The aim of the present study is to evaluate the possibility of improving crystalline quality of AlN deposited on Si (111) substrates by implementation of substrate patterning. Growth on flat Si (111) substrates was conducted to investigate influence of deposition parameters on the growth behavior and quality of resulting AlN films. This investigation showed that SiC buffer layer is required to suppress disorientation of the AlN layer, optimum growth temperature is about 1260 °C, Al-rich conditions favor more rapid coalescence of the nucleation island while N-rich conditions lead to the formation of a smooth surface. Transposition of the resulting AlN growth recipe on to patterned Si (111) substrates revealed reduction of the stress in AlN, bending of the threading dislocations and formation of a dislocation free area in the overgrown region. For the formation of a continuous layer on silicon pillars, we propose a novel technique based on the decrease of the mean free path of gaseous species leading to localized growth of AlN on the top of the pillars. Such continuous layer exhibit lower crack density compared to that on a flat substrate. Thus, the growth of AlN on pillar patterned Si substrate is seen to be a promising way for the further improvement of the AlN films quality.

SiO 2 /SiC interfaces have been under intensive research, because the quality of the interfaces can significantly affect the performance and reliability of SiC power devices. For offering microscopic insights on the generation of interface defects, here we describe the application of our novel scanning probe microscopy method called local deep level transient spectroscopy (local DLTS) to a thermally oxidized Si-face 4H-SiC epitaxial layer. Our sample is an off-axially grown epitaxial layer which is intentionally modified to have wide flat terraces and macro-stepped features instead of typical terraces separated by atomic steps. A spatially resolved map of the interface defect density shows that the macro-steps have a significantly higher interface defect density than the wide flat terraces. The result suggests that high interface defect densities on typical off-axis SiO 2 /4H-SiC stacks might be related to the steps created during the step-controlled epitaxial growth. Local DLTS is useful for the microscopic evaluation of the interface quality.

International audience; 3C-SiC layers of different microstructures (monocrystalline (100) and (111) oriented and polycrystalline) were implanted with high energy (800 keV) 129Xe++ ions. Implantations were performed at room temperature (RT) and at 500 °C using two different fluences of Φ1 = 1x1016 and Φ2 = 1x1017 at/cm2. Surface blistering was only observed for RT and Φ2 implantations into poly-SiC material while mono-SiC kept rather smooth surface. This was due to more homogeneous Xe bubbles distribution (200 nm deep) in the mono-SiC than in the poly-SiC. Xe retention was found to be almost complete for all samples. Some Xe enhanced diffusion was detected in the poly-SiC material which was attributed to grain boundaries. Some irradiation-induced oxidation effect was evidenced, O element being located at the depth where Xe bubbles are accumulating. This was more pronounced for poly than for mono-SiC. These results demonstrate that SiC microstructure affects many aspects of its behavior upon Xe irradiation.

Desde la masificación del uso del automóvil, el crecimiento de las ciudades inició una tendencia hacia su dispersión. Esto, a su vez, cambió el carácter de la calle, convirtiendo a este espacio público por antonomasia en un “no-lugar”. En Quito, los espacios colectivos – centros comerciales o espacios deportivos privados – concentran la actividad “urbana”, dejando las calles en abandono, tanto por parte de los ciudadanos como de las autoridades. El cambio de paradigma actual, donde el cuidado del medio ambiente, de nuestra propia salud, y el uso responsable de los recursos obliga a repensar la ciudad que construimos, hace necesaria la compactación urbana y la recuperación de la calle como espacio público. Este artículo explora cómo las características físicas de la calle – ancho de vía, fachada urbana, relación acera-calzada, ubicación de “ganchos” o atractores – pueden consolidarla como un espacio público que propicie la compactación de la ciudad. Para ello, se analizan tres casos ejemplares: los ejes comerciales en Mollet del Vallès (Barcelona), las calles del Centro Histórico y la recuperación del Bulevar de la avenida Naciones Unidas (Quito). El resultado del análisis permite delinear estrategias de intervención para convertir las calles de “no-lugares” a paisajes urbanos articuladores, que propicien la compactación y densificación de los barrios. Estos lineamientos se aplican en una propuesta de intervención en el vacío urbano que deja la vía del eje del tren en Caupichu, parroquia dispersa y con baja densidad poblacional en el sur de la ciudad de Quito.

Current generations of 4H-SiC metal-oxide-semiconductor field-effect transistors are still challenged by the high number of defects at the SiO2/SiC interface that limit both the performance and gate reliability of these devices. One potential source of the high density of interface defect states (D-it) is the stepped morphology on commonly used off-axially grown epitaxial surfaces, favoring incomplete oxidation and the formation of defective transition layers. Here we report measurements on intentionally modified 4H-SiC surfaces exhibiting both atomically flat and stepped regions where the generation of interface defects can be directly linked to differences in surface roughness. By combining spatially resolving structural, chemical, optical, and electrical analysis techniques, a strong increase of D-it for stepped surfaces was revealed while regions with an atomically flat SiC surface exhibited close-to-ideal interface properties.

Thick layer of polycrystalline silicon (poly-Si) grown by Atmospheric Pressure Chemical Vapor Deposition (APCVD) is still a reference material in a number of applications, despite the high thermal budget of this technique. This work presents a material study of undoped poly-Si layers of different thicknesses, using different characterization techniques such as secondary electron microscope in backscattered detection configuration, electron backscattering diffraction imaging, secondary ion mass spectrometry and spreading resistance profiling. The poly-Si layers, grown at 1000 °C by APCVD on thermal oxide, were found to have a columnar microstructure with [110] main orientation. By correlating layer purity, grain size and electrical resistivity, no straightforward relation between grain size and resistivity could be found. The layers resistivity is found almost independent on thickness and thus grain size. The possible reasons for such difference with previous other works are discussed taking into account the grain size determination uncertainty and the electrical characterization limitations.

International audience; This paper reports on the successful elaboration of fully (100) oriented SiC/Si/SiC/Si multi-stack using chemical vapor deposition. Si(100) heteroepitaxyon 3C-SiC(100) is identified as the critical step which is solved by pulseinsertion of precursors during cooling. It lead to the roughening of the 3C-SiC surface which in turn lead to the quasi-exclusive nucleation of (100)oriented islands at the expanse of (110) ones. Subsequent Si epitaxy on suchmodified surface allows growing fully (100) oriented Si layer, as confirmed bystructural characterization of the layers. The 3C-SiC grown on top of suchSi(100) layer is again of (100) orientation, forming thus a fully (100) orientedstack. Due to the high lattice mismatch, each interface of the stack ischaracterized by a high density of crystalline defects which are shown torecombine along with thickness. Antiphase domains present inside the 3C-SiC seed are shown to have no detrimental influence on the Si layer quality.Without the surface modification step, the Si layers grown on 3C-SiC arealways polycrystalline with a mixture of (110) and (100) orientations.

International audience; In this paper are reviewed the main reported trends of Al incorporation as a function of the main 4H-SiC epitaxial growth parameters. Al incorporation was found to be limited by its high desorption rate for all the parameters investigated. Due to the lack of a general model describing reasonably the processes of Al incorporation, the concept of surface vacancy induced incorporation was proposed and applied to explain these experimental results. In this model, Al incorporation is mainly driven by the transient formation of Si vacancies at the surface or sub-surface of terraces. It was shown that for increasing Al incorporation, one needs to improve its stability upon adsorption on Si vacancy and/or to reduce its desorption time. In this model, the transient formation of C vacancies at the surface or sub-surface (favored at low C/Si ratio) is proposed to play also a role by destabilizing the incorporated Al atoms.

International audience; In this paper, the electrical properties of Ti3SiC2-based ohmic contacts formed on p-type 4H-SiC were studied. The growth of Ti3SiC2 thin films were studied onto 4H-SiC substrates by thermal annealing of Ti-Al layers deposited by magnetron sputtering. In this study, we varied the concentrations of Ti and Al (Ti20Al80, Ti30Al70, Ti50Al50, and Ti), and the annealing temperature from 900 °C to 1200 °C for each concentration. X-ray diffraction and transmission electron microscopy analyzes were performed on the samples to determine the microstructure of the annealed layers and to further investigate the compounds formed after annealing. Using the transfer length method structures, the specific contact resistance (SCR) at room temperature of all contacts was measured. The temperature dependence up to 600 °C of the SCR of the best contacts was studied to understand the current mechanisms at the Ti3SiC2/SiC interface. The experimental results are in agreement with the thermionic field emission theory. With this model, the barrier height of the contact varies between 0.71 and 0.85 eV. Finally, ageing tests showed that Ti3SiC2-based contacts were stable and reliable up to 400 h at 600 °C under Ar.

This work reports on the CVD heteroepitaxial growth of 3C-SiC layers on diamond (100) substrates. To obtain good layer quality, the growth procedure involves a “silicidation” step consisting in depositing a silicon layer by CVD on the diamond substrate, in order to elaborate a very thin SiC buffer layer. 3C-SiC growth is then performed on this SiC seeding layer. Silicidation and growth parameters have been studied in order to improve the quality and the morphology uniformity of the heteroepitaxial layer. The study points out the role of liquid silicon during the growth process.

In this study, the electrical properties of Ti3SiC2 based ohmic contacts formed on p-type 4H-SiC(0001) 4°-off substrates were studied. The Ti3SiC2 thin films were grown by thermal annealing (from 900°C to 1200°C) of Ti50Al50 layer deposited by magnetron sputtering. XRD analyzes were performed on the samples to further investigate the compounds formed after annealing. Using TLM structures, the Specific Contact Resistance (SCR) at room temperature of all contacts was measured. The temperature dependence (up to 600°C) of the SCR was studied to understand the current mechanisms at the interface and to determine the barrier height value by fitting the experimental results using the thermionic field emission theory. Aging tests showed that Ti3SiC2 based contacts were stable up to 200h at 600°C under Ar.

We fabricated and characterized record small microdisk resonators in thin (210 nm) 3C-SiC film grown on Si (100) substrate. It was found to support high quality factor whispering gallery modes at visible wavelengths. We demonstrated room temperature coupling of these modes to the intrinsic photoluminescence of 3C-SiC at room temperatures and identified their polarization. Finally, we discussed applications for quasi-phasematched second harmonic generation from infrared visible wavelengths.

We report on the electrical characterization of the Metal-Oxide-Semiconductor (MOS) interfacerealized on in-situ Ge-doped n-type 4H-SiC epilayers grown by Chemical Vapour Deposition(CVD). In order to study the relevance of this novel material for MOSFET technology, and in particularwhether the Ge presence deteriorates the SiC/SiO2 interface, we investigated the electrical propertiesof MOS capacitors realized on this novel substrate. Capacitance-Voltage measurements, performedto determine the quality of the SiC/SiO2 interface, show that the interface traps concentration is notincreased by the Ge content. The current through the oxide layer, monitored to study the bulk oxidequality and the tunneling mechanisms, indicates that Fowler-Nordheim conduction occurs and that thesubstrate-to-oxide barrier for electrons is comparable to the reported values for the SiC/SiO2 system.

Starting from the previously demonstrated twin-free 3C-SiC growth on 4H-SiC when using Ge pre-deposition treatment, this work focuses on the understanding of the growth mechanism that stands behind this result. Toward this end, short growth experiments were performed to allow the investigation of the nucleation stage. Based on the experimental observations, a mechanism is proposed which involves a Ge-induced transient homoepitaxial growth step followed by 3C nucleation when large terraces are formed by step faceting. Lateral expansion of the 3C islands leads to orientation selection and twin boundary elimination. Similar results can be obtained when applying a Si-based pre-deposition treatment so that the crucial transient homoepitaxial step is promoted in fact by the presence of a liquid phase itself, no by its chemical nature.

The present communication focuses on the bilayer graphene formation on a Ge doped 4H-SiC surface. The 4H-SiC epilayer was grown by CVD with Germane (GeH4) as the dopant precursor. This easily leads to the formation of Ge islands as well as graphene on the 4H-SiC surface. The Ge island decorated surface was studied by Raman spectroscopy, XPS, and TEM. It was found that the bilayer graphene is free standing and that the native oxides act as a buffer layer on the surface, covering the Ge islands. The intensity variations of the Ge component in the XPS spectra indicate that Ge atoms can be buried in the SiC surface. The TEM analysis revealed that the graphene layers are in the form of flakes, which can also be rived vertically with the support of the Ge islands on SiC surface.

In order to form Ti3SiC2 on 4H-SiC(0001) 8°-off, 200 nm of Ti30Al70 was deposited onto SiC substrates by magnetron sputtering from pure Ti30Al70 targets. The samples were then annealed at 1000°C for 10 min under Ar atmosphere in a Rapid Thermal Annealing (RTA) furnace. Structural analyses reveal the formation of epitaxial hexagonal Ti3SiC2 (0001) oriented. Elemental analyses show that high amount of Al and O elements are present inside the deposit. Obviously, the formation of Ti3SiC2 is accompanied by parasitic Al oxide, probably due to some unwanted oxygen residual in the RTA chamber. By using proper backing steps before the annealing, the deposit is not anymore composed of only Ti3SiC2 but accompanied with other compounds (Al3Ti, and Al). On the oxide-free sample, the specific contact resistance ρc of the Ti3SiC2 based contact on p-type 4H-SiC (having Na= 2×1019 cm-3) was measured to be as low as 6×10-5 Ω.cm2.

Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P+SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of the contacts, both on VLS grown P+and ion implanted N+layers, has been confirmed by Transfer Length Method (TLM) measurements. A premature leakage current is observed on the P/N junction created directly by the P+VLS gate layer, probably due to imperfect VLS (P+) / CVD (N+) SiC interface.

This work reports on the morphological and electrical characteristics of Ni/4H-SiC Schottky contacts, fabricated on epitaxial layers intentionally covered by micrometric size Ge-droplets. Specifically, the Ge-droplets behave as preferential paths for the vertical current conduction, as observed at nanometric scale by conductive atomic force microscopy. As a consequence, the electrical I-V characteristics of these Ni contacts revealed the presence of a double-barrier, thus indicating an inhomogeneity in the interface. This behavior was associated to the local Schottky barrier lowering contribution due to the Ge-presence. These results can be useful to explore the possibility of controlling the contact (Schottky or Ohmic) properties by changing the size and the distribution of the surface impurities.

The interaction of liquid Ge and Si droplets, deposited by CVD, on the surface of 4H-SiC single-crystals is studied. It was found that at 1500 °C Ge forms micrometric droplets while Si forms nanometric dots. While the Si dots do not seem to interact significantly with SiC, the Ge droplets have the tendency to dissolve the Si from the seed. This mechanism not only happens during deposition but also during the cooling. If the cooling rate is too slow, Ge evaporates from the droplets while dissolving Si so that, at the end, the droplets look like to have been fully converted from Ge to Si.

In this study, we compare the electrical properties of MOS capacitors fabricated on different surface morphologies. Comparing a standard, low-roughness (, Materials Science Forum, 897, ISSN:0255-5476, ISSN:1662-9752

Nitrogen doping of 4H-SiC during vapor phase epitaxy is still lacking of a general model explaining the apparently contradictory trends obtained by different teams. In this paper, the evolutions of nitrogen incorporation (on both polar Si and C faces) as a function of the main growth parameters (C/Si ratio, temperature, pressure and growth rate) are reviewed and explained using a model based on surface exchanges between the gas phase and the uppermost 4H-SiC atomic layers. In this model, N incorporation is driven mainly by the transient formation of C vacancies, due to H2 etching, at the surface or near the surface. It is shown that all the growth parameters are influencing the probability of C vacancies formation in a similar manner as they do for N incorporation. The surface exchange model proposes a new framework for explaining the experimental results even beyond the commonly accepted reactor type dependency.

This work reports on the improvement of ohmic contacts made on heavily p-type doped 4H-SiC epitaxial layer selectively grown by Vapor-Liquid-Solid (VLS) transport. Even before any annealing process, the contact is ohmic. This behavior can be explained by the high doping level of the VLS layer (Al concentration > 1020 cm-3) as characterized by SIMS profiling. Upon variation of annealing temperatures, a minimum value of the Specific Contact Resistance (SCR) down to 1.3x10-6 Ω.cm2 has been obtained for both 500 °C and 800 °C annealing temperature. However, a large variation of the SCR was observed for a same process condition. This variation is mainly attributed to a variation of the Schottky Barrier Height.

For a long time now, 3C-SiC has attracted attention of the semiconductor community due to its very interesting properties. The lack of commercial 3C-SiC seeds for epitaxy has forced researchers to prospect for different host materials in order to grow heteroepitaxial thin layers. Because of the obvious economical and technical advantages, silicon is a very attractive substrate so that more than 90% of the thin 3C-SiC heteroepitaxial films are grown on such seed. However, the obstacles to overcome, mainly lattice and thermal mismatch, are challenging. This article reviews the numerous attempts for growing high quality 3C-SiC heteroepitaxial layers on silicon substrate. The various aspects of the heteroepitaxial growth, from substrate carbonization to epitaxy, are discussed as a function of growth parameters. The difficulties encountered and the proposed solutions are described. Perspectives of this heteroepitaxial system are proposed.

Vapor–liquid–solid (V–L–S) growth of SiC on (100) diamond substrate is reported. The crystalline quality is evaluated by transmission electron microscopy (TEM). Diffraction contrast (CTEM) observations allowed confirming the growth of fully lattice relaxed SiC 3C-type crystalline structure. Defects as dislocations at the diamond/SiC interface and stacking faults, in the thick SiC layer are revealed by high resolution TEM and CTEM. From the invisibility criteria, using dark field observations, 〈110〉 type Burger vector are identified.

International audience; This work presents the successful CVD heteroepitaxial growth of 3C-SiC on diamond (100) substrates. When performing a direct SiC growth at 1500°C on such substrate, it leads to polycrystalline deposit. The use of a substrate pretreatment involving silicon deposition allows forming a more continuous and smoother layer. Electron BackScatter Diffraction and Transmission Electron Microscopy all revealed that the 3C-SiC layer grown on the (100) diamond substrate is monocrystalline and well oriented.

This work deals with two applications of the Selective Epitaxial Growth of highly p-type doped buried 4H-SiC in Vapor-Liquid-Solid configuration (SEG-VLS). The first application is the improvement of the Specific Contact Resistance (SCR) of contacts made on such p-type material. As a result of the extremely high doping level, SCR values as low as 1.3x10-6Ω.cm2have been demonstrated. Additionally, the high Al concentration of the SEG-VLS 4H-SiC material induces a lowering of the Al acceptor ionization energy down to 40 meV. The second application is the fabrication of PiN diodes with SEG-VLS emitter and guard-rings peripheral protection. Influence of some process parameters and crystal orientation on the forward and reverse characteristics of the PiN diodes is discussed.

International audience; This work deals with the localized epitaxial growth of SiC on (100) diamond substrate using the Vapour-Liquid-Solid (VLS) transport. An epitaxial relationship of grown SiC with the seed was succesfully achieved when inserting a silicidation step before the VLS growth. This silicidation consists in the formation of a SiC intermediate layer on the diamond substrate by solid-state reaction with a silicon layer deposited at 1000 or 1350 °C. On the 1350°C formed SiC buffer layer, p-doped 3C-SiC(100) islands elongated in the directions were obtained after VLS growth. For the 1000°C buffer layer, the SiC deposit after VLS growth is much denser but mostly polycrystalline. Interfacial reactivity and diffusion are considered to explain the obtained results.

The effect of germanium (Ge) on n-type 4H-SiC is experimentally studied by electrical characterization of homoepitaxial layers grown by chemical vapor deposition (CVD). Measurements show that electrical properties of epitaxial layers can be changed by intentional incorporation of germane (GeH4) gas during the deposition process. On the nanoscale, two-dimensional mappings acquired with conductive atomic force microscopy show preferential conductive paths on the surface of Gedoped samples, which are related to the presence of this isoelectronic impurity. Hall effect measurements confirm that also macroscopic electrical properties of n-type 4H-SiC are improved due to incorporation of Ge into SiC during CVD growth. In particular, despite equal free electron concentration, enhanced mobility in a wide temperature range is measured in Ge-doped samples as compared to a pure 4H-SiC layer. Based on our results from Hall effect measurements as well as admittance spectroscopy and deep level transient spectroscopy, it is speculated that Ge influences the generation and annealing of other point defects and thus helps to reduce the total concentration of defects.

We discuss the progress in integration of nanodiamonds with photonic devices for quantum optics applications. Experimental results in GaP, SiO2 and SiC-nanodiamond platforms show that various regimes of light and matter interaction can be achieved by engineering color center systems through hybrid approaches. We present our recent results on the growth of color center-rich nanodiamond on prefabricated 3C-SiC microdisk resonators. These hybrid devices achieve up to five-fold enhancement of diamond color center light emission and can be employed for integrated quantum photonics.