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Acoustic droplet ejection (ADE) has been proven to move liquids in droplet form from a container to mid-air. However, the droplet sizes produced using the traditional ADE setups are proportional to their heights if the physical framework is unchanged. This limitation obstructs further employment of ADE technology since having the exact sizes of droplets at a specific location or different sizes at different locations is required for many applications. To overcome this limitation and enable more possible applications of ADE, this study proposed an innovative ADE configuration that could manipulate the size and height of the ADE droplets with only electrical signals. To achieve this, a low-voltage driving period and a pinhole structure were added to create a water mound before ejection. First, simulations were conducted to validate the proposed method and find the parameters of the novel ADE setup. After that, a driving circuit featuring a high-voltage pulser and a field-programmable gate array was built. However, a 3D spherical resin model was printed to focus the acoustic wave on the water surface, and a cover with a pinhole was added to create water mound. To observe the behavior of the droplets, a recording system and detection algorithm were developed to capture and identify the dimension/height of the droplets, respectively. Finally, the proposed ADE configuration successfully manipulated the droplet size at the same ejecting height under three driving voltages (65, 70, and 75 V) and pinhole diameters (3.7, 4, and 4.4 mm). [ABSTRACT FROM AUTHOR]

This study addresses the challenges of human–robot interactions in real-time environments with adaptive field-programmable gate array (FPGA)-based accelerators. Predicting human posture in indoor environments in confined areas is a significant challenge for service robots. The proposed approach works on two levels: the estimation of human location and the robot's intention to serve based on the human's location at static and adaptive positions. This paper presents three methodologies to address these challenges: binary classification to analyze static and adaptive postures for human localization in indoor environments using the sensor fusion method, adaptive Simultaneous Localization and Mapping (SLAM) for the robot to deliver the task, and human–robot implicit communication. VLSI hardware schemes are developed for the proposed method. Initially, the control unit processes real-time sensor data through PIR sensors and multiple ultrasonic sensors to analyze the human posture. Subsequently, static and adaptive human posture data are communicated to the robot via Wi-Fi. Finally, the robot performs services for humans using an adaptive SLAM-based triangulation navigation method. The experimental validation was conducted in a hospital environment. The proposed algorithms were coded in Verilog HDL, simulated, and synthesized using VIVADO 2017.3. A Zed-board-based FPGA Xilinx board was used for experimental validation. [ABSTRACT FROM AUTHOR]

Neutrino mass estimation experiments and cosmic microwave background (CMB) radiation surveys both employ low-temperature detectors (LTD) known as calorimeters and bolometers, respectively. These detectors operate typically between 10 and 300 mK. LTDs multiplexed by means of a microwave superconducting quantum interference device multiplexer (µMUX) demonstrated to be an excellent device for the readout of several detectors in the microwave region. This entails generating a multi-tonal signal and its subsequent readout. A single-tone detection method based on a Goertzel filter bank (GFB) channelizer was used for the readout of the aforementioned signal, implemented in a software-defined radio readout architecture within a field-programmable gate array. The measurements presented here demonstrate remarkable results in validating the suitability of the GFB channelizer for this system. [ABSTRACT FROM AUTHOR]

The carrier modulated sinusoidal pulsewidth modulation scheme has been acknowledged for its fundamental fortification and harmonic reduction in DC–AC conversion. This study is focused on how to get a variable output voltage with the least harmonics by changing the amplitude of the carrier wave vertically instead of modulating the reference wave (conventional SPWM). This paper proposes four control schemes for achieving the maximum fundamental voltage in a three phase voltage source inverter. The four schemes are single edge carrier shifted with (i) fixed reference and (ii) variable reference, and double edge carrier shifted with (iii) fixed reference and (iv) variable reference. In addition, the reverse modulation index and mutual modulation index are introduced as new control variables for examination. These schemes are simulated with a three phase inverter and the performance is compared with conventional sinusoidal pulsewidth modulation using MATLAB R2021. The amplitude of the fundamental voltage and the corresponding THD are reported. Digital implementations of the proposed schemes are premeditated by using VHDL language and ModelSim. The validity of the proposed schemes is experimentally investigated through a laboratory prototype of a three phase inverter module incorporated with an FPGA Spartan 6 device. This prototype is tested with a three phase induction motor as the load. The fundamental voltage and THD for the existing and proposed schemes are reported. [ABSTRACT FROM AUTHOR]

This paper contributes to the fusion of metaheuristic fuzzy neural network (FNN) and self-tuning autonomous control for omnidirectional mobile platforms in robotic cyber-physical systems (RCPSs). A cyber grey wolf optimization (GWO)-based FNN computing is incorporated with the backstepping control scheme and dynamic modeling to achieve autonomous control for the omnidirectional Mecanum platforms with uncertainties for RCPSs, called GWOFNN. The proposed cyber GWOFNN computing method is employed to address the self-tuning autonomous control problem of RCPS omnidirectional platforms by considering modeling uncertainties and unknown frictions. Numerical simulations and real-time experiments via field-programmable gate array (FPGA) realization are provided to illustrate the efficacy, applicability and merits of the presented RCPS GWOFNN real-time self-tuning cyber control strategy. Through comparison works, the advantages of the proposed GWOFNN computing are validated to accomplish autonomous control for Mecanum mobile RCPSs in polar space. [ABSTRACT FROM AUTHOR]

'Frame blocking' or 'Framing' is a technique that divides a time-sampled speech or audio signal into consecutive and equi-sized short-time frames, either overlapped or non-overlapped, for analysis. The framing hardware architectures (FHA) in the literature support framing speech or audio samples of specific word size with specific frame size and frame overlap size. However, speech and audio applications often require framing signal samples of varied word sizes with varied frame sizes and frame overlap sizes. Therefore, the existing FHAs must be redesigned appropriately to keep up with the variability in word size, frame size and frame overlap size, as demanded across multiple applications. Redesigning the existing FHAs for each specific application is laborious, prompting the need for a configurable intellectual property (IP) core. The existing FHAs are inappropriate for creating configurable IP cores as they lack adaptability to accommodate variability in frame size and frame overlap size. Therefore, to address these issues, a novel FHA, adaptable to accommodate the desired variability, is proposed. Furthermore, the proposed FHA is transformed into a field-programmable gate array-based soft, ready-to-use and configurable frame blocking IP core using the Xilinx® Vivado™ tool. The resulting IP core is versatile, offering configurability for framing in numerous applications incorporating real-time digital speech and audio systems. This research article discusses the proposed FHA and frame blocking IP core in detail. [ABSTRACT FROM AUTHOR]

Domain-specific hardware to solve computationally hard optimization problems has generated tremendous excitement. Here, we evaluate probabilistic bit (p-bit) based Ising Machines (IM) on the 3-Regular 3-Exclusive OR Satisfiability (3R3X), as a representative hard optimization problem. We first introduce a multiplexed architecture that emulates all-to-all network functionality while maintaining highly parallelized chromatic Gibbs sampling. We implement this architecture in a single Field-Programmable Gate Array (FPGA) and show that running the adaptive parallel tempering algorithm demonstrates competitive algorithmic and prefactor advantages over alternative IMs by D-Wave, Toshiba, and Fujitsu. We also implement higher-order interactions that lead to better prefactors without changing algorithmic scaling for the XORSAT problem. Even though FPGA implementations of p-bits are still not quite as fast as the best possible greedy algorithms accelerated on Graphics Processing Units (GPU), scaled magnetic versions of p-bit IMs could lead to orders of magnitude improvements over the state of the art for generic optimization. Specialized hardware for hard optimization is gaining traction. Here, the authors introduce a sparse, multiplexed, and reconfigurable p-bit Ising Machine on Field-Programmable Gate Arrays, using adaptive parallel tempering and higher-order interactions to achieve competitive performance on the 3-Regular 3-XORSAT problem. [ABSTRACT FROM AUTHOR]

In the quest for computational efficiency, binary neural networks (BNNs) have emerged as a promising paradigm, offering significant reductions in memory footprint and computational latency. In traditional BNN implementation, the first and last layers are typically full-precision, which causes higher logic usage in field-programmable gate array (FPGA) implementation. To solve these issues, we introduce a novel approach named Ponte (Represent Totally Binary Neural Network Toward Efficiency) that extends the binarization process to the first and last layers of BNNs. We challenge the convention by proposing a fully binary layer replacement that mitigates the computational overhead without compromising accuracy. Our method leverages a unique encoding technique, Ponte::encoding, and a channel duplication strategy, Ponte::dispatch, and Ponte::sharing, to address the non-linearity and capacity constraints posed by binary layers. Surprisingly, all of them are back-propagation-supported, which allows our work to be implemented in the last layer through extensive experimentation on benchmark datasets, including CIFAR-10 and ImageNet. We demonstrate that Ponte not only preserves the integrity of input data but also enhances the representational capacity of BNNs. The proposed architecture achieves comparable, if not superior, performance metrics while significantly reducing the computational demands, thereby marking a step forward in the practical deployment of BNNs in resource-constrained environments. [ABSTRACT FROM AUTHOR]

This paper presents the design of an eight-channel digital receive beamformer application-specific integrated circuit (ASIC) based ultrasound (US) imaging system. The designed prototype system supports up to 64 transmit and 16 receive channels. ASIC-based 16-channel US transceiver board is designed for frontend processing, and for backend processing Intel® Core™-i5 based PC is employed. The transceiver board employs two ASICs for digital receive beamforming and a field-programmable gate array (FPGA) for transmit beamforming and system control. The necessary power supplies for the transceiver board are provided by a custom designed and developed high voltage (HV) and low voltage (LV) power supply board. The transceiver board performs the frontend processing like transmit beamforming, control, analog signal conditioning and digital receive beamforming. The received beamformed data are directly transferred to a host PC via the Gigabit Ethernet interface for image formation, post-processing and display. The ASIC-based system developed can provide real-time B-mode imaging with a maximum frame rate of 102 fps with a field of view (FOV) of 90∘. These results indicate that the ASIC-based US imaging systems can provide better processing capability and performance. [ABSTRACT FROM AUTHOR]

RDMA (Remote Direct Memory Access) technology has been widely applied due to its high-throughput and low-latency characteristics compared with traditional networks. Implementing RDMA with an FPGA (Field-Programmable Gate Array) is a feasible solution. This paper proposes an implementation method for the ROCE v2 (Remote Direct Memory Access) protocol packet parser and generator based on an FPGA, capable of supporting various transaction packet types, such as RDMA READ, RDMA WRITE, and SEND, under the Reliable Connection service. The RDMA READ and RDMA WRITE performance of RDMA is close to 100 Gbps, which provides a feasible solution for the application of wide-area networks. [ABSTRACT FROM AUTHOR]

Over the past decade, wearable medical devices (WMDs) have become the norm for continuous health monitoring, enabling real-time vital sign analysis and preventive healthcare. These battery-powered devices face computational power, size, and energy resource constraints. Traditionally, low-power microcontrollers (MCUs) and application-specific integrated circuits (ASICs) have been used for their energy efficiency. However, the increasing demand for multi-modal sensors and artificial intelligence (AI) requires more computational power than MCUs, and rapidly evolving AI asks for more flexibility, which ASICs lack. Field-programmable gate arrays (FPGAs), which are more efficient than MCUs and more flexible than ASICs, offer a potential solution when optimized for energy consumption. By combining real-time reconfigurability with intelligent energy optimization strategies, FPGAs can provide energy-efficient solutions for handling multimodal sensors and evolving AI requirements. This paper reviews low-power strategies toward FPGA-based WMD for physiological monitoring. It examines low-power FPGA families, highlighting their potential in power-sensitive applications. Future research directions are suggested, including exploring underutilized optimizations like sleep mode, voltage scaling, partial reconfiguration, and compressed learning and investigating underexplored flash and hybrid-based FPGAs. Overall, it provides guidelines for designing energy-efficient FPGA-based WMDs. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a real-time high-resolution analogue-to-digital-based free-space optics system. We utilise a field-programmable gate array platform complete with system-on-chip to flexibly implement the orthogonal frequency division multiplexing (OFDM) with up to 2048 sub-carriers and carrier-less amplitude and phase (m-CAP) modulation with up to 20 sub-bands in a real free-space optical link for the first time. We also consider high order modulation formats up to 64-QAM (6 bits/symbol) to achieve a raw data rate up to 1.8 Gb/s. Previous real-time free-space optics transceivers were either analog-based or restricted to on-off keying (1 bit/symbol). We emulate the fog environment utilising neutral density filters and evaluate the performance of the link under increasingly poor visibility conditions. We show that OFDM and m-CAP offer similar performances in the link environment, however, we finally show that m-CAP offers increased robustness and receiver sensitivity in low visibility settings. [ABSTRACT FROM AUTHOR]

Modern physics experiments rely on precise timing provided by programmable digital pulse generators. In many experimental control systems, this role is filled by custom devices built on field-programmable gate arrays. While highly flexible and performant, these devices can be difficult to scale to very large systems due to cost and complexity. Recent advances in microcontroller systems allow these much simpler devices to fill the role of digital pulse generators. Here, we demonstrate one such alternative based on the Raspberry Pi Pico microcontroller, which allows for timing resolution down to 7.5 ns with a minimum pulse width of 37.5 ns. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the successful implementation of reconfigurable field-programmable gate array technology into a pulse-resolved data acquisition system to achieve a femtosecond temporal resolution in ultrafast pump–probe experiments in real-time at large scale facilities. As proof of concept, electro-optic sampling of terahertz waveforms radiated by a superradiant emitter of a quasi-cw accelerator operating at a 50 kHz repetition rate and probed by an external laser system is performed. Options for up-scaling the developed technique to a MHz range of repetition rates are discussed. [ABSTRACT FROM AUTHOR]

Summary: A DC to AC converter is developed in this paper. This proposes a single‐phase five‐level inverter is developed in such a way that one DC source is used. The structure of the inverter is modular and the capacitor has self‐voltage balancing capability, which eliminates the need for sensors or an additional control loop. This paper presents the schematic diagram of the proposed topology, principle of operation, and the concepts of sinusoidal pulse width modulation (SPWM) for single‐phase and space vector pulse width modulation (SVPWM) for three‐phase. To further prove the advantage, power loss, and parameter computations are calculated mathematically. Low‐voltage stress is achieved in the proposed topology because the blocking voltages of all the switches are constrained to the input voltage. A comparison table is presented between SPWM and SVPWM schemes in three‐phase inverter. The proposed asymmetrical five‐level configuration setup is constructed, and experiments are performed inside the laboratory. The controller of the converter has been implemented in the field‐programmable gate array (FPGA) platform. In order to confirm the viability of the suggested topology, experimental results are provided for single‐phase arrangement. By using the FPGA platform, real‐time implementation is done for a three‐phase inverter topology. [ABSTRACT FROM AUTHOR]

The performance of space power systems is crucial for space products as it determines the operational capabilities, endurance, and efficiency of satellites, spacecraft, and other extraterrestrial devices. Unlike reliability analysis in aerospace systems, studying spacecraft power generation performance requires consideration of both hardware and software aspects. Existing failure models do not fully capture the self‐recovery process of control programs. Therefore, this study presents an impact degradation model for space power systems that incorporates competitive failures under irradiation conditions. The model analyzes solar arrays and power controllers to derive a performance degradation model by considering the defect formation mechanism of amorphous semiconductor materials. Additionally, two shock types are defined based on redundancy backup in power controllers and scrubbing frequency in field‐programmable gate array (FPGA) units. Within the case analysis section, the research meticulously investigates and elucidates the correlation probabilities among varying proton irradiation doses, scrubbing frequencies, and the aforementioned shock types. [ABSTRACT FROM AUTHOR]

To address the issue of suboptimal spectral purity in Direct Digital Frequency Synthesis (DDFS) within resource-constrained environments, this paper proposes an optimized DDFS technique based on cubic Hermite interpolation. Initially, a DDFS hardware architecture is implemented on a Field-Programmable Gate Array (FPGA); subsequently, essential interpolation parameters are extracted by combining the derivative relations of sine and cosine functions with a dual-port Read-Only Memory (ROM) structure using the cubic Hermite interpolation method to reconstruct high-fidelity target waveforms. This approach effectively mitigates spurious issues caused by amplitude quantization during the DDFS digitalization process while reducing data node storage units. Moreover, this paper introduces single-quadrant ROM compression technology to further diminish the required storage space. Experimental results indicate that, compared to traditional DDFS methods, the optimization scheme proposed in this work achieves a ROM resource compression ratio of 1792:1 and a 14-bit output Spurious-Free Dynamic Range (SFDR) of −88.134 dBc, effectively enhancing amplitude quantization precision and significantly lowering spurious levels. This significantly improves amplitude quantization precision and reduces spurious levels. The proposed scheme demonstrates notable advantages in both spectral performance and resource utilization efficiency, making it highly suitable for resource-constrained embedded systems and high-performance applications such as radar and communication systems. [ABSTRACT FROM AUTHOR]

A fiber Bragg grating (FBG) pulse and systolic blood pressure (SBP) measurement system based on the edge-filtering method is proposed. The edge filter is the Mach–Zehnder interferometer (MZI) fabricated by two fiber couplers with a linear slope of 52.45 dBm/nm. The developed system consists of a broadband light source, an edge filter, fiber Bragg gratings (FBGs), a coarse wavelength-division multiplexer (CWDM), and signal-processing circuits based on a field-programmable gate array (FPGA). It can simultaneously measure pulse pulsations of the radial artery in the wrist at three positions: Cun, Guan and Chi. The SBP can be calculated based on the pulse transit time (PTT) principle. The measurement results compared to a standard blood pressure monitor showed the mean absolute error (MAE) and standard deviation (STD) of the SBP were 0.93 ± 3.13 mmHg. The system meets the requirements of the Association for the Advancement of Medical Instrumentation (AAMI) equipment standards. The proposed system can achieve continuous real-time measurement of pulse and SBP and has the advantages of fast detection speed, stable performance, and no compression sensation for subjects. The system has important application value in the fields of human health monitoring and medical device development. [ABSTRACT FROM AUTHOR]

DC–DC buck converters have been designed by incorporating different control stages to drive the switches. Among the most commonly used controllers, the sliding mode control (SMC) and proportional-integral-derivative (PID) controller have shown advantages in accomplishing fast slew rate, reducing settling time and mitigating overshoot. The proposed work introduces the implementation of both SMC and PID controllers by using the field-programmable gate array (FPGA) device. The FPGA is chosen to exploit its main advantage for fast verification and prototyping of the controllers. In this manner, a DC–DC buck converter is emulated on an FPGA by applying an explicit multi-step numerical method. The SMC controller is synthesized into the FPGA by using a signum function, and the PID is synthesized by applying the difference quotient method to approximate the derivative action, and the second-order Adams–Bashforth method to approximate the integral action. The FPGA synthesis of the converter and controllers is performed by designing digital blocks using computer arithmetic of 32 and 64 bits, in fixed-point format. The experimental results are shown on an oscilloscope by using a digital-to-analog converter to observe the voltage regulation generated by the SMC and PID controllers on the DC–DC buck converter. [ABSTRACT FROM AUTHOR]

Solving the Perspective-n-Point (PnP) problem is difficult in low-power systems due to the high computing workload. To handle this challenge, we present an originally designed FPGA implementation of a PnP solver based on Vivado HLS. A matrix operation library and a matrix decomposition library based on QR decomposition have been developed, upon which the EPnP algorithm has been implemented. To enhance the operational speed of the system, we employed pipeline optimization techniques and adjusted the computational process to shorten the calculation time. The experimental results show that when the number of input data points is 300, the proposed system achieves a processing speed of 45.2 fps with a power consumption of 1.7 W and reaches a peak-signal-to-noise ratio of over 70 dB. Our system consumes only 3.9% of the power consumption per calculation compared to desktop-level processors. The proposed system significantly reduces the power consumption required for the PnP solution and is suitable for application in low-power systems. [ABSTRACT FROM AUTHOR]

Optical wireless video transmission technology combines the advantages of high data rates, enhanced security, large bandwidth capacity, and strong anti-interference capabilities inherent in optical communication, establishing it as a pivotal technology in contemporary data transmission networks. However, video data comprises a large volume of image information, resulting in substantial data flow with significant redundant bits. To address this, we propose an adaptive block sampling compressive sensing algorithm that overcomes the limitations of sampling inflexibility in traditional compressive sensing, which often leads to either redundant or insufficient local sampling. This method significantly reduces the presence of redundant bits in video images. First, the sampling mechanism of the block-based compressive sensing algorithm was optimized. Subsequently, a wireless optical video transmission experimental system was developed using a Field-Programmable Gate Array chip. Finally, experiments were conducted to evaluate the transmission of video optical signals. The results demonstrate that the proposed algorithm improves the peak signal-to-noise ratio by over 3 dB compared to other algorithms, with an enhancement exceeding 1.5 dB even in field tests, thereby significantly optimizing video transmission quality. This research contributes essential technical insights for the enhancement of wireless optical video transmission performance. [ABSTRACT FROM AUTHOR]

Spike timing-dependent plasticity (STDP) is crucial for training neural networks (SNNs), offering a hardware-compatible and energy-efficient alternative to backpropagation. Current STDP hardware platforms encounter significant challenges, such as slowness, high energy consumption, and limited configurability. To overcome these issues, this paper presents a high-performance SNN training platform. A parallel multi-ring first-in-first-out structure with event-driven processing for spike handling is proposed, which enhances training efficiency, and the flexible pre- and post-synaptic parallelism enhances speed and flexibility. A dataflow strategy that considers spike sparsity unifies spike representations by updating weights only upon spike arrival, thereby promoting logical symmetry and enabling parallelization. Additionally, three encoding strategies, including a hybrid encoding, are implemented to address diverse scenarios. Leveraging Xilinx field-programmable gate array and Jetson Xavier NX, the proposed platform achieved remarkable performance gains. On the MNIST dataset, the platform demonstrated a 22.51 × speedup, 2.13% accuracy boost, and 14.79 × reduction in energy consumption. On the Fashion-MNIST dataset, it improved accuracy by 10.74% and the training speed by 1.89 × . Thus, this platform can significantly advance the SNN training efficiency and performance. [ABSTRACT FROM AUTHOR]

With the development of mobile communication, digital signatures with low latency, low area, and high security are in increasing demand. Elliptic curve cryptography (ECC) is widely used because of its security and lightweight. Elliptic curve scalar multiplication (ECSM) is the basic arithmetic in ECC. Based on this background information, we propose our own research objectives. In this paper, a low-latency and low-area ECSM architecture based on the comb algorithm is proposed. The detailed methodology is as follows. The recoding-k algorithm and randomization-Z algorithm are used to improve security, which can resist sample power analysis (SPA) and differential power analysis (DPA). A low-area multi-functional architecture for comb is proposed, which takes into account different stages of the comb algorithm. Based on this, the data dependency is considered and the comb architecture is optimized to achieve a uniform and efficient execution pattern. The interleaved modular multiplication algorithm and modified binary inverse algorithm are used to achieve short clock cycle delay and high frequency while taking into account the need for a low area. The proposed architecture has been implemented on Xilinx Virtex-7 series FPGA to perform ECSM on 256-bits prime field  G F (p) . In the hardware architecture with only 7351 slices of resource usage, a single ECSM only takes 0.74 ms, resulting in an area-time product (ATP) of 5.41. The implementation results show that our design can compete with the existing state-of-the-art engineering in terms of performance and has higher security. Our design is suitable for computing scenarios where security and computing speed are required. The implementation of the overall architecture is of great significance and inspiration to the research community. [ABSTRACT FROM AUTHOR]

The current study uses Field-Programmable Gate Array (FPGA) hardware to advance smart home technology through a self-learning system. The proposed intelligent three-hidden layer system outperformed prior systems with 99.21% accuracy using real-world data from the MavPad dataset. The research shows that FPGA solutions can do difficult computations in seconds. The study also examines the difficulties of maximizing performance with limited resources when incorporating deep learning technologies into FPGAs. Despite these challenges, the research shows that FPGA-based solutions improve home technology. It promotes the integration of sophisticated learning algorithms into ordinary electronics to boost their intelligence. [ABSTRACT FROM AUTHOR]

This research work focuses on the design and implementation of a highly advanced field-programmable gate array (FPGA)-based system-on-chip (SoC) solution for real-time edge detection. By utilizing a Zynq processor and leveraging the powerful Vivado software, the aim is to overcome the significant computational challenges associated with achieving real-time edge detection. Edge detection in real-time scenarios presents several obstacles, including the possibility of missing edges due to noise and the substantial processing requirements of any edge detection technique. To address these challenges, the proposed SoC system synergistically combines the computational capabilities of an FPGA board and a Zynq processor, harnessing hardware acceleration to achieve high-performance edge detection. The OV7670 camera module serves as the primary input medium, capturing image frames for subsequent processing. These captured frames undergo initial processing before being seamlessly transferred to the FPGA fabric through customized intellectual property (IP) blocks. These IP blocks efficiently handle crucial tasks such as frame capturing, conversion to AXI Stream interface signals, and integration with the video direct memory access (VDMA) IP. The VDMA IP plays a pivotal role by facilitating high-speed data movement between the FPGA fabric and the Zynq processor IP, thereby enabling streamlined and efficient data transfer and processing. At the heart of this project lies the real-time edge detection algorithm, which is skillfully implemented on the Zynq processor. The resulting edge-detected frames are then visually presented and displayed on an output device utilizing the AXI4-Stream to Video Out IP. To ensure optimal utilization of available hardware resources, the comprehensive Vivado software suite provides a wide array of tools for designing, implementing, and programming the FPGA fabric. By leveraging FPGA-based systems, this project effectively addresses the critical need for real-time edge detection in time-sensitive scenarios. The result is a portable and manageable device that exhibits versatility, as it can be employed in various applications while reliably detecting edges in real-time situations. [ABSTRACT FROM AUTHOR]

In the domain of hardware security, Physical Unclonable Functions (PUFs) offer a unique method for securing Field-Programmable Gate Arrays (FPGAs) by generating distinct identifiers. Despite their potential, FPGA-based PUFs often struggle with issues of uniqueness, reliability, and resource efficiency. Addressing these challenges, this paper introduces a novel FPGA-based PUF-IDG designed to significantly improve reliability and stability. Through dynamic environmental compensation, the system adeptly adjusts to fluctuations, ensuring consistent performance. Energy-efficient strategies are implemented, facilitating deployment in resource-constrained settings. Enhanced security features, including quantum-resistant elements and sophisticated countermeasures, shield against modern attacks. With real-time monitoring and the capacity for firmware updates, the PUF-IDG aligns with current cryptographic protocols and is built to withstand evolving security threats. This research lays the groundwork for a new generation of robust, adaptable hardware security solutions. [ABSTRACT FROM AUTHOR]

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick's signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively. [ABSTRACT FROM AUTHOR]

Artificial Intelligence (AI) is rapidly transforming the healthcare, finance and transportation industries. This paper presents a field-programmable gate array (FPGA)-based neural network accelerator (NNA) design for power allocation in downlink nonorthogonal multiple access (NOMA) networks. The proposed hardware accelerator effectively cuts computational costs while delivering performance on par with the highest sum capacity. Numerical results show that this NNA offers a remarkable computational speed increase of up to 99% compared to the conventional exhaustive search method. Furthermore, the deep learning (DL) model achieved high accuracy (0.92 training, 0.93 testing), and the hardware accelerator design for this DL inference model was implemented on the PYNQ-Z2 board-constrained edge device to predict power allocation coefficients in NOMA systems. [ABSTRACT FROM AUTHOR]

Continuous fire models are not suitable for the implementation of hardware units for applications and hence, suitable discrete versions need to be selected. Moreover, the nonlinear components in the neuronal equations reduce system performance (in the case of frequency and number of resources). This research paper focuses on implementing efficient Spiking Neural Networks (SNNs) using Field-Programmable Gate Array (FPGA), with a specific emphasis on the Leaky Integrate and Fire (LIF) neuron model. Its objective is to optimize the mathematical equations of the LIF model by approximating nonlinear functions. This approach enables the development of a simple, cost-effective and high-speed design. Existing LIF Neuron Hardware Blocks (NHBs) are based on the approximation of continuous models by standard difference schemes such as the Euler method or R–K method etc. Mathematically, such approximations do not exactly represent all dynamics of continuous systems. There are good approximations for small step sizes but they behave oddly when the approximation step size increases. Hence, the corresponding discrete, digital versions are not suitable for applications in all cases. This paper utilizes a Nonstandard Finite Difference (NSFD) scheme for the hardware (FPGA) implementation of the exact model of LIF-based NHB that works for all step sizes. The model presented here has a speed of 438.686MHz which is more than other existing models presented in this paper. It is multiplier-less, unlike earlier models. Further, it is implemented for SNN for basic pattern recognition and established that the proposed model works properly for given patterns. The system was evaluated using large datasets such as MNIST handwritten digit recognition, achieving a classification accuracy of 97.8%. Additionally, it underwent testing for COVID-19 chest CT scan image classification, demonstrating an 84% accuracy rate which is 6% more compared to existing Spiking Neural Networks (SNNs). [ABSTRACT FROM AUTHOR]

Currently, there is a demand for an increase in the diversity and quality of new products reaching the consumer market. This fact imposes new challenges for different industrial sectors, including processes that integrate machine vision. Hardware acceleration and improvements in processing efficiency are becoming crucial for vision-based algorithms to follow the complexity growth of future industrial systems. This article presents a generic library of pre-processing filters for execution in field-programmable gate arrays (FPGAs) to reduce the overall image processing time in vision systems. An experimental setup based on the Zybo Z7 Pcam 5C Demo project was developed and used to validate the filters described in VHDL (VHSIC hardware description language). Finally, a comparison of the execution times using GPU and CPU platforms was performed as well as an evaluation of the integration of the current work in an industrial application. The results showed a decrease in the pre-processing time from milliseconds to nanoseconds when using FPGAs. [ABSTRACT FROM AUTHOR]

With the rapid development of the Internet of Vehicles (IoV), the demand for secure and efficient signature verification is becoming increasingly urgent. To meet this need, we propose an efficient SM9 aggregate signature scheme implemented on Field-Programmable Gate Array (FPGA). The scheme includes both fault-tolerant and non-fault-tolerant aggregate signature modes, which are designed to address challenges in various network environments. We provide security proofs for these two signature verification modes based on a K-ary Computational Additive Diffie–Hellman (K-CAA) difficult problem. To handle the numerous parallelizable elliptic curve point multiplication operations required during verification, we utilize FPGA's parallel processing capabilities to design an efficient parallel point multiplication architecture. By the Montgomery point multiplication algorithm and the Barrett modular reduction algorithm, we optimize the single-point multiplication computation unit, achieving a point multiplication speed of 70776 times per second. Finally, the overall scheme was simulated and analyzed on an FPGA platform. The experimental results and analysis indicate that under error-free conditions, the proposed non-fault-tolerant aggregate mode reduces the verification time by up to 97.1% compared to other schemes. In fault-tolerant conditions, the proposed fault-tolerant aggregate mode reduces the verification time by up to 77.2% compared to other schemes. When compared to other fault-tolerant aggregate schemes, its verification time is only 28.9% of their consumption, and even in the non-fault-tolerant aggregate mode, the verification time is reduced by at least 39.1%. Therefore, the proposed scheme demonstrates significant advantages in both error-free and fault-tolerant scenarios. [ABSTRACT FROM AUTHOR]

This paper presents a new boot loader scheme for embedded devices with file system support built as a hardware module. The work focuses on improving the boot loader hardware and the possibility of carrying out a full boot-up process from the dedicated on-chip hardware, using a light file system to store an operating system kernel. To do so, the new full-hardware boot loader is integrated into two Field-Programmable Gate Array (FPGA) System-on-Chip (SoC), capable of launching a Linux kernel from a formatted removable media. [ABSTRACT FROM AUTHOR]

The fast Fourier transform (FFT) is a widely used algorithm for computing the discrete Fourier transform (DFT) in real-time signal processing. Achieving high performance with minimal resource usage is crucial for any real-time application. This paper introduces an architecture based on coordinate rotation digital computer (CORDIC) for implementing a radix-22 FFT. Traditional FFT implementations require complex twiddle factor multiplications, which is not cost-effective in terms of hardware utilization. To address this issue, we have proposed a radix-8 CORDIC-based approach integrated with FFT computation. The proposed radix-8 CORDIC requires fewer stages than the conventional radix-2 CORDIC, enhancing computational efficiency and reducing hardware utilization. The feedforward radix-22 FFT architecture is presented where the butterflies of the FFT are computed with the help of radix-8 CORDIC. A total of three FFT architectures are developed supporting 16-, 1024- and 2048-point FFTs. The proposed FFT architectures are developed using Verilog-HDL code and implemented on a Virtex-7 field-programmable gate array (FPGA). The FPGA-based radix-22 FFT achieves a clock frequency of 323.4MHz and utilizes minimal FPGA resources. Processing of 2048 data samples takes only 4.06μS by the proposed FPGA-based design. Additionally, two ASICs have been designed: the 1024-point FFT ASIC occupies an area of 1.079mm2, and the 2048-point FFT ASIC occupies an area of 1.544 mm2. The proposed FFT ASICs have better-normalized area per FFT and energy per FFT than the state-of-the-art designs. [ABSTRACT FROM AUTHOR]

Semiconductor spin qubits represent a promising platform for future large-scale quantum computers owing to their excellent qubit performance, as well as the ability to leverage the mature semiconductor manufacturing industry for scaling up. Individual qubit control, however, commonly relies on spectral selectivity, where individual microwave signals of distinct frequencies are used to address each qubit. As quantum processors scale up, this approach will suffer from frequency crowding, control signal interference and unfeasible bandwidth requirements. Here, we propose a strategy based on arrays of degenerate spins coherently dressed by a global control field and individually addressed by local electrodes. We demonstrate simultaneous on-resonance driving of two degenerate qubits using a global field while retaining addressability for qubits with equal Larmor frequencies. Furthermore, we implement SWAP oscillations during on-resonance driving, constituting the demonstration of driven two-qubit gates. Significantly, our findings highlight how dressing can overcome the fragility of entangling gates between superposition states and increase their noise robustness. These results constitute a paradigm shift in qubit control in order to overcome frequency crowding in large-scale quantum computing. Global control of a qubits using a single microwave field is a promising strategy for scalable quantum computing. Here the authors demonstrate individual addressability vial local electrodes and two-qubit gates in an array of Si quantum dot spin qubits dressed by a global microwave field and driven on-resonance. [ABSTRACT FROM AUTHOR]

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented. [ABSTRACT FROM AUTHOR]

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process–Voltage–Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field. [ABSTRACT FROM AUTHOR]

Convolutional neural networks (CNNs) are now often used in deep learning and computer vision applications. Its convolutional layer accounts for most calculations and should be computed fast in a local edge device. Field‐programmable gate arrays (FPGAs) have been adequately explored as promising hardware accelerators for CNNs due to their high performance, energy efficiency, and reconfigurability. This paper developed an efficient FPGA‐based 16‐bit fixed‐point hardware accelerator unit for deep learning applications on the 32‐bit low‐memory edge device (PYNQ‐Z2 board). Additionally, singular value decomposition is applied to the fully connected layer for dimensionality reduction of weight parameters. The accelerator unit was designed for all five layers and employed eight processing elements in convolution layers 1 and 2 for parallel computations. In addition, array partitioning, loop unrolling, and pipelining are the techniques used to increase the speed of calculations. The AXI‐Lite interface was also used to communicate between IP and other blocks. Moreover, the design is tested with grayscale image classification on MNIST handwritten digit dataset and color image classification on the Tumor dataset. The experimental results show that the proposed accelerator unit implementation performs faster than the software‐based implementation. Its inference speed is 89.03% more than INTEL 3‐core CPU, 86.12% higher than Haswell 2‐core CPU, and 82.45% more than NVIDIA Tesla K80 GPU. Furthermore, the throughput of the proposed design is 4.33GOP/s, which is better than the conventional CNN accelerator architectures. [ABSTRACT FROM AUTHOR]

In this study, a phase-generated carrier (PGC) demodulation algorithm combined with the extended Kalman filter (EKF) algorithm based on an electro-optic modulator (EOM) is proposed, which can achieve nonlinear distortion (such as modulation depth drift and carrier phase delay) suppression for high-frequency phase carrier modulation. The improved algorithm is implemented on a field-programmable gate array (FPGA) hardware platform. The experimental results by the PGC-EKF method show that total harmonic distortion (THD) decreases from −32.61 to −54.51 dB, and SINAD increases from 32.59 to 47.86 dB, compared to the traditional PGC-Arctan method. This indicates that the PGC-EKF demodulation algorithm proposed in this paper can be widely used in many important fields such as hydrophone, transformer, and ultrasound signal detection. [ABSTRACT FROM AUTHOR]

This study aims to devise a traffic electronic information signal acquisition system employing Internet of Things and artificial intelligence technologies, offering a novel approach to address prevailing challenges related to traffic congestion and safety. Initially, the hardware circuit for the high-speed signal acquisition control core is developed, leveraging Field-Programmable Gate Array technology. This facilitates wireless monitoring of signal acquisition. Subsequently, a comprehensive time signal acquisition system is formulated, encompassing modules for communication, acquisition, storage, adaptive measurement, and signal analysis. The geomagnetic acquisition module within this system is utilized for collecting geomagnetic signals, which are then translated into switch signals indicating the presence or absence of vehicles. These signals are subsequently transmitted to the geomagnetic signal processor. Experimental results pertaining to the signal acquisition system reveal a notable peak storage speed of 200KB/s, considering the utilization of one million sampling points. Across a series of tests, the maximum relative error of the obtained results ranges from 2.2% to 2.7%, underscoring the consistency and reliability of the measurements. In comparison to existing testing devices, the system exhibits heightened accuracy in test results, rendering it more apt for traffic signal acquisition applications. In conclusion, this study accomplishes the collection and dissemination of diverse traffic information, furnishing robust support for traffic control and ensuring safe operations. [ABSTRACT FROM AUTHOR]

The range-Doppler algorithm (RDA), a key technique for generating synthetic aperture radar (SAR) images, offers high-resolution images but requires significant memory resources and involves complex signal processing. Moreover, the multitude of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations in RDA necessitates high bandwidth and lacks data reuse, leading to bottlenecks. This paper introduces a synthetic aperture radar dual in-line memory module (SARDIMM), which executes RDA operations near memory via near-memory processing (NMP), thereby effectively reducing memory accesses, execution time, and energy consumption. The embedded NMP module in SARDIMM optionally supports a combination of FFT, IFFT, and matched filter operations of the RDA for range and azimuth compression. The operator within the NMP module accelerates the FFT by performing two radix-2 single butterfly operations in parallel. The NMP module was implemented and validated on a Xilinx UltraScale+ field-programmable gate array (FPGA) using Verilog-HDL. The acceleration performance of RDA for images of various sizes was evaluated through a simulator modified with gem5 and DRAMSim3 and achieved a 6.34–6.93× speedup and 41.9–48.2% energy savings. [ABSTRACT FROM AUTHOR]

This paper presents the design of a predictive controller for a boost converter and validation through real-time simulation. First, the boost converter was mathematically modeled, and then the electronic components were designed to meet the operation requirements. Subsequently, a model-based predictive controller (MBPC) and a digital PI (Proportional–Integral) controller were designed, and their performance was compared using MATLAB/SIMULINK®. The controls were further verified by implementing test benches based on an FPGA (Field-Programmable Gate Array) with an OPAL-RT real-time simulator, which included the RT-LAB and RT-eFPGAsim simulation packages. These tests were successfully carried out, and the methodology used for this design was validated. The results showed a better response obtained with MBPC, both in terms of stabilization time and lower overvoltage. [ABSTRACT FROM AUTHOR]

Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern recognition. Recently, the Discrete Orthonormal Stockwell Transform (DOST) has become increasingly utilized in many specialized signal processing tasks. Given its growing importance, this work proposes a reconfigurable field-programmable gate array (FPGA) architecture designed to efficiently implement the DOST algorithm on cost-effective FPGA chips. An accompanying MATLAB app enables the automatic configuration of the DOST method for varying sizes (64, 128, 256, 512, and 1024 points). For the implementation, a Cyclone V series FPGA device from Intel Altera, featuring the 5CSEMA5F31C6N chip, is used. To provide a complete hardware solution, the proposed DOST core has been integrated into a hybrid ARM-HPS (Advanced RISC Machine–Hard Processor System) control unit, which allows the control of different peripherals, such as communication protocols and VGA-based displays. Results show that less than 5% of the chip's resources are occupied, indicating a low-cost architecture that can be easily integrated into other FPGA structures or hardware systems for diverse applications. Moreover, the accuracy of the proposed FPGA-based implementation is underscored by a root mean squared error of 6.0155 × 10−3 when compared with results from floating-point processors, highlighting its accuracy. [ABSTRACT FROM AUTHOR]

The increasing complexity of modern networks and their evolving needs demand flexible, high-performance packet processing solutions. The P4 language excels in specifying packet processing in software-defined networks (SDNs). Field-programmable gate arrays (FPGAs) are ideal for P4-based packet parsers due to their reconfigurability and ability to handle data transmitted at high speed. This paper introduces three FPGA-based P4-programmable packet parsing architectural designs that translate P4 specifications into adaptable hardware implementations called base, overlay, and pipeline, each optimized for different packet parsing performance. As modern network infrastructures evolve, the need for multi-tenant environments becomes increasingly critical. Multi-tenancy allows multiple independent users or organizations to share the same physical network resources while maintaining isolation and customized configurations. The rise of 5G and cloud computing has accelerated the demand for network slicing and virtualization technologies, enabling efficient resource allocation and management for multiple tenants. By leveraging P4-programmable packet parsers on FPGAs, our framework addresses these challenges by providing flexible and scalable solutions for multi-tenant network environments. The base parser offers a simple design for essential packet parsing, using minimal resources for high-speed processing. The overlay parser extends the base design for parallel processing, supporting various bus sizes and throughputs. The pipeline parser boosts throughput by segmenting parsing into multiple stages. The efficiency of the proposed approaches is evaluated through detailed resource consumption metrics measured on an Alveo U280 board, demonstrating throughputs of 15.2 Gb/s for the base design, 15.2 Gb/s to 64.42 Gb/s for the overlay design, and up to 282 Gb/s for the pipelined design. These results demonstrate a range of high performances across varying throughput requirements. The proposed approach utilizes a system that ensures low latency and high throughput that yields streaming packet parsers directly from P4 programs, supporting parsing graphs with up to seven transitioning nodes and four connections between nodes. The functionality of the parsers was tested on enterprise networks, a firewall, and a 5G Access Gateway Function graph. [ABSTRACT FROM AUTHOR]

Electron beam lithography (EBL) involves the transfer of a pattern onto the surface of a substrate by first scanning a thin layer of organic film (called resist) on the surface by a tightly focused and precisely controlled electron beam (exposure) and then selectively removing the exposed or nonexposed regions of the resist in a solvent (developing). It is widely used for fabrication of integrated circuits, mask manufacturing, photoelectric device processing, and other fields. The key to drawing circular patterns by EBL is the graphics production and control. In an EBL system, an embedded processor calculates and generates the trajectory coordinates for movement of the electron beam, and outputs the corresponding voltage signal through a digital-to-analog converter (DAC) to control a deflector that changes the position of the electron beam. Through this procedure, it is possible to guarantee the accuracy and real-time control of electron beam scanning deflection. Existing EBL systems mostly use the method of polygonal approximation to expose circles. A circle is divided into several polygons, and the smaller the segmentation, the higher is the precision of the splicing circle. However, owing to the need to generate and scan each polygon separately, an increase in the number of segments will lead to a decrease in the overall lithography speed. In this paper, based on Bresenham's circle algorithm and exploiting the capabilities of a field-programmable gate array and DAC, an improved real-time circle-producing algorithm is designed for EBL. The algorithm can directly generate circular graphics coordinates such as those for a single circle, solid circle, solid ring, or concentric ring, and is able to effectively realizes deflection and scanning of the electron beam for circular graphics lithography. Compared with the polygonal approximation method, the improved algorithm exhibits improved precision and speed. At the same time, the point generation strategy is optimized to solve the blank pixel and pseudo-pixel problems that arise with Bresenham's circle algorithm. A complete electron beam deflection system is established to carry out lithography experiments, the results of which show that the error between the exposure results and the preset patterns is at the nanometer level, indicating that the improved algorithm meets the requirements for real-time control and high precision of EBL. HIGHLIGHTS: • To improve the accuracy and speed of production of circular patterns in electron beam lithography, a method of directly exposing circular patterns by controlling the electron beam is proposed, in which the trajectory coordinates of the beam are generated in real time without image stitching. • Bresenham's circle algorithm encounters two problems in circle production: blank pixels will appear when solid circles are generated, and pseudo-pixels occur when a circle of a specific radius is generated. In this paper, Bresenham's algorithm is optimized and improved to solve these two problems, and the effectiveness of the improved algorithm is demonstrated by simulation and experiment. • Experimental results show that the proposed method can effectively control electron beam photolithography of single-line-wide circles, solid circles, solid rings, concentric circles, etc. The error between the lithography results and the preset parameters is at the nanometer level. [ABSTRACT FROM AUTHOR]

There is a currently a lack of large-area plasma sterilization devices that can intelligently identify the shape of a wound for automatic sterilization. For this reason, in this work, a plasma sterilization device with wound-edge recognition was developed using a field-programmable gate array (FPGA) and a high-performance image-processing platform to realize intelligent and precise sterilization of wounds. SOLIDWORKS was used to design the mechanical structure of the device, and it was manufactured using 3D printing. The device used an improvement of the traditional Sobel detection algorithm, which extends the detection of edges in only the x and y directions to eight directions (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°), completing the wound-edge detection by adaptive thresholding. The device can be controlled according to different shapes of sterilization area to adjust the positioning of a single plasma-jet tube in the horizontal plane for two-dimensional movement; the distance between the plasma-jet tube and the surface of the object to be sterilized can be also adjusted in the vertical direction. In this way, motors are used to move the plasma jet and achieve automatic, efficient, and accurate plasma sterilization. It was found that a good sterilization effect could be achieved at both the culture-medium level and the biological-tissue level. The ideal sterilization parameters at the culture-medium level were a speed of 2 mm/s and a flow rate of 0.6 slm, while at the biological-tissue level, these values were 1 mm/s and 0.6 slm, respectively. ARTICLE HIGHLIGHTS: • Image processing combining eight-direction Sobel edge detection and a median-filtering adaptive threshold was used for wound-edge recognition. • A device with x, y, and z degrees of freedom was designed and 3D printed. • An FPGA-based sterilization platform combining edge-recognition detection, a three-degree-of-freedom kinematic device, and a plasma injector was built to precisely sterilize wounds. [ABSTRACT FROM AUTHOR]

When synthesizing systems for railway interlocking, it is recommended to use automated models to implement the logic of railway automation and remote control units. Finite-state machines (FSMs) can be implemented on any hardware component. When using relay technology, the functional safety of electrical interlocking is achieved by using uncontrolled (safety) relays with a high coefficient of asymmetry of failures in types 1 → 0 and 0 → 1. When using programmable components, the use of backup and diverse protection methods is required. This paper presents a flexible approach to synthesizing FSMs for railway automation and remote control units that offer both individual and route-based control. Unlike existing solutions, this proposal considers the pre-failure states of railway automation and remote control units during the finite-state machine synthesis stage. This enables the implementation of self-checking and self-diagnostic modules to manage automation units. By increasing the number of states for individual devices and considering the states of interconnected objects, the transition graphs can be expanded. This expansion allows for the synthesis of the transition graph of the control subsystem and other systems. The authors used a field-programmable gate array (FPGA) to implement a finite-state machine. In this case, the proposal is to encode the states of a finite-state machine using weight-based sum codes in the residue class ring based on a given modulus. The best coverage of errors occurring at the outputs of the logic converter in the structure of the FSM can be ensured by selecting the weighting coefficients and the value of the module. This paper presents an example of synthesizing an FPGA-based FSM using state encoding through modular weight-based sum codes. The operation of the synthesized device was modeled. It was found to operate according to the same algorithm as the real devices. When synthesizing self-checking and self-controlled train control devices, it is recommended to consider the solutions proposed in this paper. [ABSTRACT FROM AUTHOR]

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler's method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we propose an energy-efficient design of architecture for digit-serial multiplication over generic GF( 2 m ), which could be used for different fields as and when required and to enhance the security by changing the fields. An efficient input scheduling scheme is proposed to reduce the required number of input pins and a digit extraction circuit for digit-serial multiplication. Besides, to reduce the dynamic power consumption, we have proposed a simple technique using an array of m AND gates that minimizes the output bit-switching. To study the impact of digit size, the digit-serial multipliers for m = 163 and 233 are synthesised by Xilinx Vivado for FPGA implementation. It is found that the required number of slices, power consumption, and energy per multiplication increase while the computational delay falls with the increase in digit size. Therefore, larger digit sizes could be considered only when fast multiplication is necessary. The array of AND gates for output bit control helps in reducing the dynamic power consumption and energy per multiplication, respectively, by 50.4% and 57.7% for m = 163 and 49.8 % and 51.8 % , for m = 233 , on average, for different digit sizes over the conventional least-significant-digit-first design. [ABSTRACT FROM AUTHOR]