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The growing demands of large-capacity flash-based storages have facilitated the downscaling process of NAND flash memory. However, the downscaling of traditional planar floating-gate flash memory faces several challenges. Therefore, new NAND flash technologies have been explored to provide larger capacity with low cost. Among these new technologies, the 3-D charge-trap flash is regarded as one of the most promising candidates. The 3-D charge-trap flash is composed of several gate-stack layers and vertical cylindrical channels to provide high-density and low cell-to-cell interference. Owing to the cylindrical geometry of vertical channels, the access performance of each page in one block is distinctive, and this situation is exacerbated in the 3-D charge-trap flash with the fast-growing number of gate-stack layers. In this paper, a progressive performance boosting strategy is proposed to boost the performance of 3-D charge-trap flash by utilizing its asymmetric page access speed feature. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the access performance of 3-D charge-trap flash. [ABSTRACT FROM AUTHOR]

Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches $10^{4}$ . [ABSTRACT FROM AUTHOR]

This paper describes actor system of a new functional language called Anemone and compares it with actor systems of Scala and Erlang. Implementation details of the actor system are described. Performance evaluation is provided on sequential and concurrent programs. [ABSTRACT FROM AUTHOR]

Flash-based storage systems offer high performance, robustness, and reliability for embedded applications; however the physical nature of flash memory means that there are limitations to its usage in high reliability applications. In previous work, we have developed RAID architectures and associated controller hardware that increase the reliability and lifespan of these storage systems. However, flash memory needs regular garbage collection and this presents two issues in a high reliability context. The first issue concerns response times as when a garbage collector is active, the flash memory cannot be used by the application layer. This non-determinism in terms of response is problematic in high reliability systems that require real-time guarantees. The second issue concerns lifespan of flash chips. If the garbage collector is allowed free rein over erase operations while garbage collecting, this affects management of the lifespan of each SSD in the array. In this paper we present an enhanced, dynamic, real-time garbage collection method for SSD RAID that does not ignore the strict age distribution management, while offering deterministic response times for access. Real-time efficiency is further improved by dynamically coordinating garbage collection across each device in the array. Our simulation results indicate that the dynamic garbage collection technique maintains the age distribution at a level that does not affect reliability of individual devices. This is evidences using various synthetic and realistic traces dominated by random I/O loads. [ABSTRACT FROM AUTHOR]

In multi-level cell (MLC) NAND flash memory, two logical pages are overlapped on a single physical page. Even after a logical page is programmed, the data can be corrupted if the programming of the coexisting logical page is interrupted. This phenomenon is called paired page interference. This article proposes a novel software technique to deal with the paired page interference without any additional hardware or extra page write. The proposed technique utilizes valid pages in the victim block during garbage collection (GC) as the backup against the interference, and pairs them with incoming pages written by the host. This approach eliminates undesirable page copy to backup pages against the interference. However, such a strategy has an adverse effect on the hot/cold separation policy, which is essential to improve the efficiency of GC. To limit the downside, we devise a metric to estimate the benefit of GCMix on-the-fly so that GCMix can be adaptively utilized only when the benefit outweighs the overhead. Evaluations using synthetic and real workloads show GCMix can effectively deal with the paired page interference, reducing the write amplification factor by up to 17.5%compared to the traditional technique, while providing comparable I/O performance. [ABSTRACT FROM AUTHOR]

Emerging nonvolatile RAM (NVRAM) technologies have a limit on the number of writes that can be made to any cell, similar to the erasure limits in NAND Flash. This motivates the need for wear leveling techniques to distribute the writes evenly among the cells. Unlike NAND Flash, cells in NVRAM can be rewritten without the need for erasing the entire containing block, avoiding the issues of space reclamation and garbage collection, motivating alternate approaches to the problem. In this article, we propose a hierarchical wear-leveling model called Ouroboros wear leveling. Ouroboros uses a two-level strategy whereby frequent low-cost intraregion wear leveling at small granularity is combined with interregion wear leveling at a larger time interval and granularity. Ouroboros is a hybrid migration scheme that exploits correct demand predictions in making better wear-leveling decisions while using randomization to avoid wear-leveling attacks by deterministic access patterns. We also propose a way to optimize wear-leveling parameter settings to meet a target smoothness level under limited time and space overhead constraints for different memory architectures and trace characteristics. Several experiments are performed on synthetically generated memory traces with special characteristics, two block-level storage traces, and two memory-line-level memory traces. The results show that Ouroboros wear leveling can distribute writes smoothly across the whole NVRAM with no more than 0.2% space overhead and 0.52% time overhead for a 512GB memory. [ABSTRACT FROM AUTHOR]

NAND flash memory is the major storage media for both mobile storage cards and enterprise Solid-State Drives (SSDs). Log-block-based Flash Translation Layer (FTL) schemes have been widely used to manage NAND flash memory storage systems in industry. In log-block-based FTLs, a few physical blocks called log blocks are used to hold all page updates from a large amount of data blocks. Frequent page updates in log blocks introduce big overhead so log blocks become the system bottleneck. To address this problem, this paper presents BLog, a block-level log-block management scheme for MLC NAND flash memory storage system. In BLog, with block-level management, the update pages of a data block can be collected together and put into the same log block as much as possible; therefore, we can effectively reduce the associativities of log blocks so as to reduce the garbage collection overhead. We also propose a novel partial merge operation strategy called reduced-order merge by which we can effectively postpone the garbage collection of log blocks so as to maximally utilize valid pages and reduce unnecessary erase operations in log blocks. Based on BLog, we design an FTL called BLogFTL for Multi-Level Cell (MLC) NAND flash. We conduct a set of experiments on a real hardware platform. Both representative FTL schemes and the proposed BLogFTL have been implemented in the hardware evaluation board. The experimental results show that our scheme can effectively reduce the garbage collection operations and reduce the system response time compared to the previous log-block-based FTLs for MLC NAND flash. [ABSTRACT FROM PUBLISHER]

Data compression is beneficial to flash storage lifespan. However, because the design of mobile flash storage is highly cost-sensitive, hardware compression becomes a less attractive option. This study investigates the feasibility of data compression on mobile flash storage. It first characterizes data compressibility based on mobile apps, and the analysis shows that write traffic bound for mobile storage volumes is highly compressible. Based on this finding, a lightweight approach is introduced for firmware-based data compression in mobile flash storage. The controller and flash module work in a pipelined fashion to hide the data compression overhead. Together with this pipelined design, the proposed approach selectively compresses incoming data of high compressibility, while leaving data of low compressibility to a compression-aware garbage collector. Experimental results show that our approach greatly reduced the frequency of block erase by 50.5% compared to uncompressed flash storage. Compared to unconditional data compression, our approach improved the write latency by 10.4% at a marginal cost of 4% more block erase operations. [ABSTRACT FROM AUTHOR]

NAND flash memory is widely used in various systems, ranging from real-time embedded systems to enterprise server systems. Because the flash memory has erase-before-write characteristics, we need flash-memory management methods, i.e., address translation and garbage collection. In particular, garbage collection (GC) incurs long-tail latency, e.g., 100 times higher latency than the average latency at the 99th percentile. Thus, real-time and quality-critical systems fail to meet the given requirements such as deadline and QoS constraints. In this study, we propose a novel method of GC based on reinforcement learning. The objective is to reduce the long-tail latency by exploiting the idle time in the storage system. To improve the efficiency of the reinforcement learning-assisted GC scheme, we present new optimization methods that exploit finegrained GC to further reduce the long-tail latency. The experimental results with real workloads show that our technique significantly reduces the long-tail latency by 29-36% at the 99.99th percentile compared to state-of-the-art schemes. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturbance, and lower access latency. In contrast to conventional planar flash memory, 3D flash memory adopts chargetrapping mechanism. NAND strings punch through multiple stacked layers to form the three-dimensional infrastructure. However, the etching processes for NAND strings are unable to produce perfectly vertical features, especially on the scale of 20 nanometers or less. The process variation will cause uneven distribution of electrons, which poses a threat to the integrity of data stored in flash. This paper present P-Alloc, a process-variation tolerant reliability management strategy for 3D chargetrapping flash memory. P-Alloc offers both hardware and software support to allocate data to the 3D flash in the presence of process variation. P-Alloc predicts the state of a physical page, i.e., the basic unit for each write or read operation in flash memory, and tries to assign critical data to more reliable pages. A hardwarebased voltage threshold compensation scheme is also proposed to further reduce the faults. We demonstrate the viability of the proposed scheme using a variety of realistic workloads. Our extensive evaluations show that, P-Alloc significantly enhances the reliability and reduces the access latency compared to the baseline scheme. [ABSTRACT FROM AUTHOR]

As the cost-per-bit of solid state disks is decreasing quickly, SSDs are supplanting HDDs in many cases, including the primary storage of key-value stores. However, simply deploying LSM-tree-based key-value stores on commercial SSDs is inefficient and induces heavy write amplification and severe garbage collection overhead under write-intensive conditions. The main cause of these critical issues comes from the triple redundant management functionalities lying in the LSM-tree, file system and flash translation layer, which block the awareness between key-value stores and flash devices. Furthermore, we observe that the performance of LSM-tree-based key-value stores is improved little by only eliminating these redundant layers, as the I/O stacks, including the cache and scheduler, are not optimized for LSM-tree's unique I/O patterns. To address the issues above, we propose FlashKV, an LSM-tree based key-value store running on openchannel SSDs. FlashKV eliminates the redundant management and semantic isolation by directly managing the raw flash devices in the application layer. With the domain knowledge of LSM-tree and the open-channel information, FlashKV employs a parallel data layout to exploit the internal parallelism of the flash device, and optimizes the compaction, caching and I/O scheduling mechanisms specifically. Evaluations show that FlashKV effectively improves system performance by 1.5× to 4.5× and decreases up to 50% write traffic under heavy write conditions, compared to LevelDB. [ABSTRACT FROM AUTHOR]

In the near future, data is expected to double in every two years, which translates to more than one terabyte of data for every person on earth. The difficulty of storing and fetching required data from data centers and servers will consequently increase. As a result, significant attention has been given to the flash memory-based solid state drive (SSD) from consumer electronics companies, which has begun to replace the existing hard disk drive and is highly likely to be used as a storage unit for most of consumer electronics to achieve low power consumption. In contrast to traditional disk, SSD uses semiconductor chips to store data. This structure enjoys original technical characteristics, including low power consumption, shock resistance, and high performance in random access. Such features can overcome the shortcomings of magnetic disks. However, flash memory, the basic unit of SSD, has many distinctive characteristics that cause various challenges. Flash memory does not support updating in the place method. A write operation can be performed only on an empty or erased unit, making the process more time-consuming. Moreover, each storage unit has a limited number of erase cycles, after which the block becomes invalid. This research proposes a new scheme called performance and reliability concern to increase the reliability and performance of SSDs. The eligibility of the proposed scheme is proven through EagleTree simulator. The scheme is also compared with other state-of-the-art techniques in terms of effectiveness and efficiency. Experimental results show that the proposed scheme provides sufficient performance and reliability for SSD. [ABSTRACT FROM AUTHOR]

Redundant array of independent disk (RAID) offers a good option to provide device-level fault tolerance for solid-state drives (SSDs). However, parity update with either read–modify–write or read–reconstruct–write may introduce a lot of extra I/Os and thus significantly degrades SSD RAID performance. To reduce the parity update cost, elastic striping chooses to reconstruct new stripes with only the newly updated data chunks instead of directly updating parity chunks. However, it necessitates an RAID-level garbage collection (GC) process, which may incur a very high cost due to the mixture of hot and cold data chunks. To address this problem, we follow the idea of elastic striping and propose a workload-aware scheme (WAS) to reduce the RAID-level GC cost so as to improve the performance and endurance of SSD RAID. In particular, we first develop a novel lightweight hot data identification scheme which requires only a very small computation time and memory cost, then propose a hotness-aware elastic striping approach to separately write data chunks with different hotness to different regions in SSD RAID. To evaluate the effectiveness and efficiency of our WAS, we implement a prototype system on RAID-5 and RAID-6 arrays composed of commercial SSDs. Experimental results show that compared to original elastic striping, our scheme reduces 30.0%–70.6% (and 23.9%–63.2%) of chunk writes under the RAID-5 (and RAID-6) settings, and also reduces the average response time by 60.9%–79.3% (and 56.8%–80.9%) for RAID-5 (and RAID-6), respectively. Besides, our scheme also improves the endurance and reliability of SSD RAID compared to original elastic striping. [ABSTRACT FROM AUTHOR]

Solid-state drives (SSDs) are rapidly replacing hard disk drives in enterprise data centers due to their higher throughput and reliability. However, the SSD's random write performance is limited by the NAND flash memories within the SSD, which require garbage collection (GC). To improve the write throughput, a logical block address (LBA) scrambler has been previously proposed. However, there are two issues associated with this solution. First, with the LBA scrambler, SSD throughput actually worsens for some types of workloads, such as prxy_0. Second, a large table size is needed. In this paper, the first problem is solved by a write order (WO)-based GC scheme. In order to choose the victim block, the parameters of valid page ratio, write order, and erase count of the NAND flash blocks are collectively considered according to a new formula. A key advantage of utilizing the relative write order of the blocks is that an internal timer is not needed to monitor the ages of the blocks. Second, a sector bundling scheme is proposed to reduce the table size of the LBA scrambler. Based on the experimental results, with the two proposals, SSD throughput is improved by 2.4 times, and the table size of the LBA scrambler is reduced by 45%. [ABSTRACT FROM AUTHOR]

The flash-memory based Solid State Drive (SSD) presents a promising storage solution for increasingly critical data-intensive applications due to its low latency (high throughput), high bandwidth, and low power consumption. Within an SSD, its Flash Translation Layer (FTL) is responsible for exposing the SSD’s flash memory storage to the computer system as a simple block device. The FTL design is one of the dominant factors determining an SSD’s lifespan and performance. To reduce the garbage collection overhead and deliver better performance, we propose a new, low-cost, adaptive separation-aware flash translation layer (ASA-FTL) that combines sampling, data clustering and selective caching of recency information to accurately identify and separate hot/cold data while incurring minimal overhead. We use sampling for light-weight identification of separation criteria, and our dedicated selective caching mechanism is designed to save the limited RAM resource in contemporary SSDs. Using simulations of ASA-FTL with both real-world and synthetic workloads, we have shown that our proposed approach reduces the garbage collection overhead by up to 28% and the overall response time by 15% compared to one of the most advanced existing FTLs. We find that the data clustering using a small sample size provides significant performance benefit while only incurring a very small computation and memory cost. In addition, our evaluation shows that ASA-FTL is able to adapt to the changes in the access pattern of workloads, which is a major advantage comparing to existing fixed data separation methods. [ABSTRACT FROM AUTHOR]

Many Java applications instantiate objects within the Java heap that are persistent but seldom if ever referenced by the application. Examples include strings, such as error messages, and collections of value objects that are preloaded for fast access. This paper describes a stack-based framework for detecting these 'cold' objects at runtime, with a view to marshaling and sequestering them in designated regions of the heap where they may be preferentially paged out to a backing store, thereby freeing physical memory pages for occupation by more active objects. Furthermore, we evaluate the correctness and efficiency of stack-based approach with an access barrier. The experimental results from a series of SPECjvm2008 benchmarks are presented. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The migration of application logic to the client side of modern web applications and the use of JavaScript as the main language for client-side development have made memory leaks in JavaScript an issue for web applications. Client-side web applications communicate with the server asynchronously, remaining on the same web page during their lifetime. Thus, even minor memory leaks can eventually lead to excessive memory usage, negatively affecting user-perceived response time and possibly causing page crashes. To detect memory leaks and guide developers in fixing the leaks quickly and easily, this paper introduces LeakSpot, a tool that creates a run-time heap model by modifying the application code in a browser-agnostic way to record object allocations, accesses, and references created to objects. LeakSpot reports those allocation sites causing the leaks instead of all the leaky allocation sites. It also identifies the locations in the code where leaked objects are accumulated, for example, the locations where a reference from a data structure is created but forgotten to be removed by the developer. To facilitate debugging and fixing the leaks, for every leaked object, LeakSpot reports all the locations in the code that create a reference to the object. To confirm usefulness and efficacy of LeakSpot experimentally, we have used LeakSpot to find and fix four memory leaks in a JavaScript benchmark suite and in open-source web applications. LeakSpot is also shown to be effective in pointing out the potential causes of three leaks in large and popular web applications. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents our work on the inception of RTDroid, a variant of Android that provides predictability to Android applications. Although there has been much interest in adopting Android in real-time contexts, surprisingly little work has been done to examine the suitability of the Android franework layer for real-time systems. Existing work only provides solutions to traditional problems, including adding support for real-time garbage collection at the virtual machine layer as well as kernel-level real-time scheduling and resource management. While it is critical to address these issues, it is by no means sufficient. After all, Android is a vast system that is more than a Java virtual machine and a kernel. Thus, this paper goes beyond existing work and examines the internals of Android, the Android programming model, libraries, and core systems services. We discuss the implications and challenges of adapting Android constructs and core system services for real-time and present a solution for each. Our system is unique in that it redesigns Androids internal components, replaces Androids Dalvik VM with a real-time VM, and leverages off-the-shelf real-time OSes. We demonstrate the feasibility and predictability of our solution on three different platforms. The evaluation results show that our design can successfully provide predictability to Android applications even under heavy loads. [ABSTRACT FROM PUBLISHER]

Dynamic memory management is an important and essential part of computer systems design. Efficient memory allocation, garbage collection, and compaction are becoming critical in parallel and distributed applications using object oriented languages like C++ and Java. In addition to achieving fast allocation/de-allocation of memory objects and fragmentation, memory management techniques should strive to improve the overall execution performance of object oriented applications. In this paper, we introduce Address Ordered and Segregated Binary Trees, two memory management techniques particularly efficient for object oriented applications. Our empirical results manifest that both ABT and SBT, when accompanied by coalescing, outperform the existing allocators such as Segregated free lists in terms of storage utilization and execution performance. We also show that these new allocators perform well in terms of storage utilization, even without coalescing. This is in particular suitable for web-applications. [ABSTRACT FROM AUTHOR]

Parity protection at the system level is typically employed to compose reliable storage systems. However, careful consideration is required when SSD-based systems employ parity protection. First, additional writes are required for parity updates. Second, parity consumes space on the device, which results in write amplification from less efficient garbage collection at higher space utilization. This article analyzes the effectiveness of SSD-based RAID and discusses the potential benefits and drawbacks in terms of reliability. A Markov model is presented to estimate the lifetime of SSD-based RAID systems in different environments. In a small array, our results show that parity protection provides benefit only with considerably low space utilizations and low data access rates. However, in a large system, RAID improves data lifetime even when we take write amplification into account. [ABSTRACT FROM AUTHOR]

The approach for fast application relaunching on the current Android system is to cache background applications in memory. This mechanism is limited by the available memory size. In addition, the application state may not be easily recovered. We propose a prototype system, MARS, to enable page swapping and cache more applications. MARS can speed up the application relaunching and restore the application state. As a new page swapping design for optimizing application relaunching, MARS isolates Android runtime Garbage Collection (GC) from page swapping for compatibility and employs several flash-aware techniques for swap-in speedup. Two main components of MARS are page slot allocation and read/write control. Page slot allocation reorganizes page slots in swap area to produce sequential reads and improve the performance of swap-in. Read/Write control addresses the read/write interference issue by reducing concurrent and extra internal writes. Compared to the conventional Linux page swapping, these two components can scale up the read bandwidth up to about 3.8 times. Application tests on a Google Nexus 4 phone show that MARS reduces the launching time of applications by 50 $\sim$ 80 percent. The modified page swapping mechanism can outperform the conventional Linux page swapping up to four times. [ABSTRACT FROM AUTHOR]

In this paper the authors have proposed a new 3x3 reversible gate and also proposed the reversible combinational logic circuits with better optimized quantum cost, garbage outputs and delay. The proposed new reversible logic gate is used to design of reversible 1-bit comparator circuit and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed new reversible logic gate is represented by quantum implementation. The quantum cost of proposed gate is 4. The quantum cost, garbage output and delay of proposed reversible 1-bit comparator circuit are 6 which is better w. r. t. previously reported results. [ABSTRACT FROM AUTHOR]

This article presents how the compiler from the OCaml-Java project generates Java bytecode from OCaml sources. Targeting the Java Virtual Machine (JVM) is a technological challenge, but gives access to a platform where OCaml can leverage multiple cores and access numerous libraries. We present the main design choices regarding the runtime and the various optimizations performed by the compiler that are crucial to get decent performance on a JVM. The challenge is indeed not only to generate bytecode but to generate efficient bytecode, and to provide a runtime library whose memory footprint does not impede the efficiency of the garbage collector. We focus on the strategies that differ from the original OCaml compiler, as the constraints are quite different on the JVM when compared to native code. The level of performance reached by the OCaml-Java compiler is assessed through benchmarks, comparing with both the original OCaml implementation and the Scala language. [ABSTRACT FROM AUTHOR]

Memory fragmentation is a serious obstacle preventing efficient memory usage. Garbage collectors may solve the problem; however, they cause serious performance impact, memory and energy consumption. Therefore, various memory allocators have been developed. Software developers must test memory allocators, and find an efficient one for their programs. Instead of this cumbersome method, we propose a novel approach for dynamically deciding the best memory allocator for every application. The proposed solution tests each process with various memory allocators. After the testing, it selects an efficient memory allocator according to condition of operating system (OS). If OS runs out of memory, then it selects the most memory efficient allocator for new processes. If most of the CPU power was occupied, then it selects the fastest allocator. Otherwise, the balanced allocator is selected. According to test results, the proposed solution offers up to 58% less fragmented memory, and 90% faster memory operations. In average of 107 processes, it offers 7.16±2.53% less fragmented memory, and 1.79±7.32% faster memory operations. The test results also prove the proposed approach is unbeatable by any memory allocator. In conclusion, the proposed method is a dynamic and efficient solution to the memory fragmentation problem. [ABSTRACT FROM AUTHOR]

Hot data identification plays a very important role in NAND flash memory because it can improve the efficiency of garbage collection and decrease the degree of wear leveling. Existing hot data identification mechanisms have drawbacks in terms of their memory-space overhead and the true identification of hot data. To address these problems, this paper proposes a novel hot data identification mechanism. This mechanism mainly consists of kernel density estimation and a hot degree function. The kernel density estimation is used to build the kernel density function of the read and write operations by monitoring them in the NAND flash memory. That is, the kernel density function can be used for preliminary estimation of the probability distribution of the hot and cold data in NAND flash memory. After preliminary estimation of the kernel density function, the hot degree function is introduced to accurately identify the hot data in the NAND flash memory. Experimental results show that the proposed mechanism performs better than existing hot data identification mechanisms in terms of the false identification ratio between hot data and memory-space overheads. [ABSTRACT FROM AUTHOR]

NAND flash memory has become the dominant storage device for consumer electronics such as smart phones, portable personal computers, and digital cameras. Because NAND flash memory often introduces an out-of-place update scheme to solve its erase-before-write hardware constraint, these consumer electronics devices should perform garbage collection to reclaim garbage and obtain free space. However, existing garbage collection schemes usually suffer from the high garbage collection overhead and the high degree of wear leveling. In this paper, a dynamic garbage collection scheme based on past update times is proposed for NAND flash-based consumer electronics. The proposed scheme can achieve a balance between the garbage collection overhead and the degree of wear leveling. Experimental results show that the proposed scheme is better than existing garbage collection schemes in terms of the number of copy operations, the number of erase operations, the energy consumption, and the degree of wear leveling. [ABSTRACT FROM AUTHOR]

Platforms with automatic memory management, such as the JVM, are usually considered free of memory leaks. However, memory leaks can happen in such environments, as the garbage collector cannot free objects, which are not used by the application anymore, but are still referenced. Such unused objects can eventually fill up the heap and crash the application. Although this problem has been studied extensively, nevertheless, there are still many rooms for improvement in this area. This paper describes the statistical approach for memory leak detection, as an alternative, along with a commercial tool, Plumbr, which is based on the method. The tool is later analyzed with three case studies of real applications and in the process also analyzes strengths and weaknesses of the statistical approach for memory leak detection. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Hot data identification in flash memory is of great interest because it significantly affects the garbage collection and wear-leveling performance. Presently, certain hot and cold data classification schemes based on Bloom filters (BFs) have been proposed. Although BFs are efficient in most cases, there is a significant trade-off between false positive rates, which are the result of hash value collisions and memory utilization. In this paper, we suggest a better data categorization mechanism that is based on a hashing technique called Fingerprinting by Random Polynomials with the aim of reducing false positive rates and achieving lower memory consumption compared to the BF-based schemes. We also introduce a new methodology for classifying write requests by linking the definition of hot and cold write requests to the flash memory software layer, the flash translation layer (FTL) characteristics. Our approach improves space utilization by representing each logical block number (lbn) by one counter in the hash table, and achieves an extremely low error rate by choosing the degree of the hash function based on the address space of the flash memory. In addition, we achieved lower false identification rates. We demonstrate the performance using mathematical analysis and trace-driven simulation. [ABSTRACT FROM AUTHOR]

Solid-state drives (SSD) are popular storage media devices alongside magnetic hard disk drives (HDD). SSD flash chips are packaged in HDD form factors and SSDs are compatible with regular HDD device drivers and I/O buses. This compatibility allows easy replacement of individual HDDs with SSDs in existing storage systems. However, under certain circumstances, SSD write performance can be significantly slowed by garbage collection (GC) processes. The frequency of GC activity is directly correlated with the frequency of inside-SSD write operations and the amount of data written to it. GC scheduling is locally controlled by an internal SSD logic. This paper studies the feasibility of Redundant Arrays of Independent Flash-based Solid-state drives (RAIS). We empirically analyze the RAIS performance using commercially-off-the-shelf (COTS) SSDs. We investigate the performance of various RAIS configurations under a variety of I/O access patterns. Finally, we present our performance and cost comparisons of RAIS with a fast, PCIe-based COTS SSD, in terms of performance and cost. [ABSTRACT FROM AUTHOR]

In many NAND flash-memory storage systems, invalidated pages can occupy the storage space until being erased. In order to preserve sustained write performance and effective storage capacity, the flash translation layer (FTL) must recycle these pages through garbage collection (GC) operations. Many previous studies have investigated GC techniques, most of which have focused on the effective selection of victim blocks to reduce the operational overhead. However, methods to reduce the cost overhead of the victim selection process, as well as to improve the responsiveness of storage systems during GC, have not yet been explored. In this paper, therefore, we propose a novel GC mechanism, called link-based GC (LINK-GC), which provides fast victim selection and preemptive operation with small additional space overhead to existing page-mapped FTLs. In our experiments, when compared with a GC scheme based on an on-demand victim search, the proposed mechanism increases the average input–output operations per second (IOPS) by up to 15.8% and decreases the standard deviation of IOPS by up to 6.16 times. Additionally, the LINK-GC shows better performance than the existing preemptive GC techniques in terms of responsiveness to host requests. [ABSTRACT FROM PUBLISHER]