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Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130degC and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent H2O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in H2. Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for H2 diffusion are considerably different than for H2O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects.

The impact of heavy ion energy on SEU and SEL in commercial and radiation-hardened CMOS SRAMs is explored. Provided the ion range is large enough for the ions to reach the sensitive device region, standard low-energy heavy ion testing is conservative with respect to high-energy heavy ions, at least for LETs above the threshold for direct ionization-induced upsets. However, below the threshold LET for direct ionization-induced effects we find some differences between low- and high-energy tests. These differences are attributed to the effects of nuclear reaction-induced secondary particles. Implications for hardness assurance testing and error rate calculations are discussed.

The radiation hardness of nominally identical SRAM test chips fabricated in five commercial foundries is examined. Large variations in single-event latchup and total dose response are observed. The softest SRAMs fail functionally at ~200 krad(SiO2) and have a fairly large single-event latchup cross section. This is in contrast to the hardest foundry split which is nearly immune to single-event latchup at room temperature, and remains functional to a total dose of 400 krad(SiO 2). Three of the splits show a similar increase in radiation induced leakage current, which is dependent on both the characterization bias as well as the pattern written to the memory array. The other two splits show neither a pattern nor a bias dependence on the leakage current. Heavy-ion microbeam experiments confirm that the most latchup sensitive area of these SRAMs is the peripheral circuitry, not the memory array itself. Qualification and hardened-by-design integrated circuit implications are discussed

To explore the impact of temperature on the post-irradiation response of ICs, we characterized the temperature response of transistors, SRAMs, and a custom mixed-signal ASIC. Devices were irradiated at room temperature and electrically characterized post irradiation as a function of temperature. Devices exhibit significantly more parametric degradation when characterized at elevated temperatures. In addition to parametric degradation, it is demonstrated that post-irradiation elevated temperature characterization can also induce functional failures at significantly lower total dose levels than at room temperature. As a result, to ensure system functionality, it is essential that devices be characterized over the full system temperature range pre- and post-irradiation. Recommendations for incorporating temperature testing into a hardness assurance test method (i.e., Method 1019) are suggested. Methods for minimizing the detrimental effects of elevated temperature anneals on hardness assurance testing are also discussed

The effect of total dose on SEU hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from six different vendors were characterized for single-event upset (SEU) hardness at proton energies from 20 to 500 MeV and at temperatures of 25 and 80degC after total dose irradiating the SRAMs with either protons, Co-60 gamma rays, or low-energy x-rays. It is shown that total dose irradiation and the memory pattern written to the memory array during total dose irradiation and SEU characterization can substantially affect SEU hardness for some SRAMs. For one SRAM, the memory pattern made more than two orders of magnitude difference in SEU cross section at the highest total dose level examined. For all SRAMs investigated, the memory pattern that led to the largest increase in SEU cross section was the same memory pattern that led to the maximum increase in total-dose induced power supply leakage current. In addition, it is shown that increasing the temperature during SEU characterization can also increase the effect of total dose on SEU hardness. As a result, worst-case SEU hardness assurance test conditions are the maximum total dose and temperature of the system environment, and the minimum operating voltage of the SRAM. Possible screens for determining whether or not the SEU cross section of an SRAM will vary with total dose, based on the magnitude of the increase in power supply leakage current with total dose or the variation in SEU cross section with power supply voltage, have been suggested. In contrast to previous works, our results using selective area x-ray irradiations show that the source of the effect of total dose on SEU hardness is radiation-induced leakage currents in the memory cells. The increase in SEU cross section with total dose appears to be consistent with radiation-induced currents originating in the memory cells affecting the output bias levels of bias level shift circuitry used to control the voltage levels to the memory cells and/or due to the lowering of the noise margin of individual memory cells caused by radiation-induced leakage currents

The impact of total ionizing dose and displacement damage on single-event upset and single-event latchup hardness assurance testing of present-day commercial SRAMs is studied over a wide range of proton energies and fluence levels. Commercial SRAMs from six different vendors were irradiated at proton energies from 8 to 500 MeV and at total doses from 0 to 100 krad(Si) using multiple radiation sources. For some SRAMs, the single-event upset cross section increased with total dose. The amount of increase in SEU cross section strongly depended on the bias configuration during total dose irradiation and single-event upset characterization. For most of the SRAMs that showed an increase in single-event upset cross section with total dose, the static power supply leakage current also increased. Light emission microscopy photographs identified the source of the increase in power supply leakage current for these SRAMs as originating in peripheral transistors outside the memory array. This suggests a new single-event upset mechanism for present-day devices, which may be due to a reduction in the internally supplied memory array bias level with total dose, increasing memory cell sensitivity to single-event upset. The proton energy at which the single-event latchup cross section saturated varied considerably between devices. For one technology, the single-event latchup cross section did not saturate until the proton energy was increased to 200 MeV. These data indicate that single-event latchup hardness assurance testing should be performed at high proton energies (>100 MeV). For fluence levels less than 10/sup 11/ protons/cm/sup 2/ at a proton energy of 105 MeV, proton-induced displacement damage had no observable affect on single-event latchup cross section. The implications of these effects on single-event upset and latchup hardness assurance testing are discussed.

Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate increased saturation upset cross sections recently observed in some silicon-on-insulator (SOI) integrated circuits (ICs). Experiments performed on capacitors show a very strong bias and oxide thickness dependence for charge collection. In combination with three-dimensional (3-D) simulations, these data suggest that the mechanism for charge collection in capacitors is due to perturbation of the substrate electric fields by charge deposition in the substrate. For substrates biased in depletion, these perturbations induce displacement currents through the oxide. Charge collection by displacement currents can be substantially reduced or mitigated by using heavily doped substrates. Experiments performed on SRAMs also show enhanced charge collection from displacement currents. However, experimental data and 3-D simulations show that for SRAMs, a second mechanism also contributes to charge collection. The 3-D simulations suggest that the charge collection results from drain and body-tie heavy-ion strikes within a few tenths of a micron of the body-to-drain junctions. These charge collection mechanisms can substantially reduce the SEU hardness and soft-error reliability of commercial SOI ICs.

Final chip passivation layers are shown to have a major impact on the total dose hardness of bipolar linear technologies. It is found that devices fabricated without passivation layers do not exhibit enhanced low-dose-rate sensitivity (ELDRS) or pre-irradiation elevated-temperature stress (PETS) sensitivity, whereas devices from the same production lot fabricated with either oxide/nitride or doped-glass passivation layers are ELDRS and PETS sensitive. In addition, removing the passivation layers after fabrication can mitigate ELDRS and PETS effects. ELDRS and PETS effects do not appear to be inherently related to circuit design or layout, but are related to mechanical stress effects, hydrogen in the device, or a combination of the two. These results suggest that proper engineering of the final chip passivation layer might eliminate ELDRS and PETS effects in bipolar integrated circuits.

The geometric component of charge pumping current was examined in n-channel metal-oxide-silicon field effect transistors (MOSFETs) following low-temperature irradiation. In addition to the usual dependencies on channel length and gate bias transition time, the geometric component was found to increase with radiation-induced oxide-trapped charge density and decreasing temperature. A postirradiation injection of electrons into the gate oxide reduces the geometric component along with the density of oxide-trapped charge, which clearly demonstrates that the two are correlated. A fit of the injection data to a first-order model for trapping kinetics indicates that the electron trapping occurs predominantly at a single type of Coulomb-attractive trap site. The geometric component results primarily from the bulk recombination of channel electrons that fail to transport to the source or drain during the transition from inversion to accumulation. The radiation response of these transistors suggests that Coulomb scattering by oxide-trapped charge increases the bulk recombination at low temperatures by impeding electron transport. These results imply that the geometric component must be properly accounted for when charge pumping irradiated n-channel MOSFETs at low temperatures.

Generally good agreement is obtained between the single-event output voltage transient waveforms obtained by exposing individual circuit elements of a bipolar comparator and operational amplifier to an ion microbeam, a pulsed laser beam, and circuit simulations using SPICE. The agreement is achieved by adjusting the amounts of charge deposited by the laser or injected in the SPICE simulations. The implications for radiation hardness assurance are discussed.

The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

A pre-irradiation elevated-temperature stress is shown to have a significant impact on the radiation response of a linear bipolar circuit. Thermal cycling can lead to part-to-part variability in the radiation response of circuits packaged from the same wafer. In addition, it is demonstrated that a pre-irradiation elevated-temperature stress can significantly impact the enhanced low dose rate sensitivity (ELDRS) of the LM111 voltage comparator. Thermal stress moderates and, in some cases, eliminates ELDRS. The data are consistent with space charge models. These results suggest that there may be a connection between the mechanisms responsible for thermal-stress effects and ELDRS in linear circuits. Implications of these results for hardness assurance testing and mechanisms are discussed.

This paper addresses key issues for the cost-effective use of COTS (Commercially available Off The Shelf) microelectronics in radiation environments that enable circuit or system designers to manage risks and ensure mission success. We review several factors and tradeoffs affecting the successful application of COTS parts including (1) hardness assurance and qualification issues; (2) system hardening techniques, and (3) life-cycle costs. The paper also describes several experimental studies that address trends in total-dose, transient, and single-event radiation hardness as COTS technology scales to smaller feature sizes. As an example, the level at which dose-rate upset occurs in Samsung SRAMs increases from 1.4/spl times/10/sup 8/ rad(Si)/s for a 256 K SRAM to 7.7/spl times/10/sup 9/ rad(Si)/s for a 4 M SRAM, indicating unintentional hardening improvements in the design or process of a commercial technology. Additional experiments were performed to quantify variations in radiation hardness for COTS parts. In one study, only small (10-15%) variations were found in the dose-rate upset and latchup thresholds for Samsung 4 M SRAMs from three different date codes. In another study, irradiations of 4 M SRAMs from Samsung, Hitachi, and Toshiba indicate large differences in total-dose radiation hardness. The paper attempts to carefully define terms and clear up misunderstandings about the definitions of "COTS" and "radiation-hardened (RH)" technology.

The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and high-energy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 /spl mu/m and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central fore of the track structures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard low-energy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 /spl mu/m. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance.

No correlation was observed between single-event gate rupture (SEGR) and precursor damage by heavy-ion irradiation for 7-nm thermal and nitrided oxides. Precursor ion damage at biases below SEGR threshold for fluence variations over three orders of magnitude had no significant effect on SEGR thresholds. These data support a true single ion model for SEGR. A physical model based on the concept of a conducting pipe is developed that explains the empirical equation for the linear dependence of inverse critical field to rupture with LET. This model also explains the dependence of critical voltage on angle of incidence. As the oxide thickness approaches the diameter of the conducting pipe, the angular dependence of the critical voltage disappears. A model fit to the data suggests a central core diameter of 6 and 8 nm for conducting pipes induced in MOS oxides by Br and Au ions, respectively. The buildup of precursor ion damage in the oxides depends on ion species and bias during irradiation, but is not consistent with the accumulation of total ionizing dose damage. Some 5-nm oxides exhibited the characteristic high leakage current of SEGR; however, most 5-nm devices showed only soft breakdown during heavy ion exposure with electric fields up to 12 MV/cm.

Reactor neutron environments can be used to test/screen the sensitivity of unhardened commercial SRAMs to low-LET neutron-induced upset. Tests indicate both thermal/epithermal (

Identifying aging effects that impact radiation hardness of microelectronics is becoming increasingly important as military weapon systems are kept in the stockpile for times beyond their originally intended use period. In this work, burn-in effects are used to demonstrate the potential impact of thermally-activated aging effects on integrated circuit radiation hardness. Static random access memories (SRAMs) from three different commercial technologies were irradiated with different pre-irradiation stress conditions. A reduction in the total dose functional failure level was observed for SRAMs from two of the technologies subjected to pre-irradiation elevated temperature stresses. This is the first time the burn-in effect has been shown to degrade the radiation-induced functional failure level of an IC. SRAM data also show no indication that the burn-in effect will saturate, at least for the conditions examined in this work. These data indicate that long-term aging can result in more device degradation than is accounted for by present hardness assurance test guidelines, potentially causing device and/or system failure during the aging period. While only a few technologies have been examined to date, we suspect other technologies may exhibit similar long-term aging effects. Technique for including aging effects within a hardness assurance test program is outlined.

The dependence of single event gate rupture (SEGR) critical field on oxide thickness is examined for gate oxides from 6 to 18 nm. Capacitor data are compared to SEGR data from full integrated circuits. A 1/E/sub CR/ dependence is found for critical field to rupture as a function of ion linear energy transfer (LET), consistent with earlier work for power MOSFETS with oxide thicknesses from 30 to 150 nm. More importantly, critical field to rupture increases with decreasing oxide thickness, consistent with increasing oxide breakdown field prior to heavy-ion exposure. This suggests that SEGR need not be a limiting factor as future technologies scale into the deep submicron region. However, there is a great deal of uncertainty in how voltage may scale with decreasing oxide thickness, and SEGR may continue to be a concern for devices that operate at electric fields significantly higher than 5 MV/cm.

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation, to the development of a 0.5-/spl mu/m radiation-hardened CMOS SRAM is presented.

A wide range of advanced III-V components suitable for use in high-speed satellite communication systems were evaluated for displacement damage and single-event effects in high-energy, high-fluence proton environments. Transistors and integrated circuits (both digital and MMIC) were irradiated with protons at energies from 41 to 197 MeV and at fluences from 10/sup 10/ to 2/spl times/10/sup 14/ protons/cm/sup 2/. Large soft-error rates were measured for digital GaAs MESFET (3/spl times/10/sup -5/ errors/bit-day) and heterojunction bipolar circuits (10/sup -5/ errors/bit-day). No transient signals were detected from MMIC circuits. The largest degradation in transistor response caused by displacement damage was observed for 1.0-/spl mu/m depletion- and enhancement-mode MESFET transistors. Shorter gate length MESFET transistors and HEMT transistors exhibited less displacement-induced damage. These results show that memory-intensive GaAs digital circuits may result in significant system degradation due to single-event upset in natural and man-made space environments. However, displacement damage effects should not be a limiting factor for fluence levels up to 10/sup 14/ protons/cm/sup 2/ [equivalent to total doses in excess of 10 Mrad(GaAs)]. >

Several devices fabricated in the AT&T/Sandia CMOSV 1.25 mu m technology have been characterized for transient radiation hardness. Dose rate upset levels exceeding 10/sup 9/ rad(Si)/s were obtained on 16-bit microprocessor, 64 K SRAM and 256 K SRAM ICs. Experimental data on neutron irradiated parts is given. Secondary photocurrents are shown to exist in logic structures which do not have adequate p-well contact placement. Layout guidelines are developed which allow the IC designer to eliminate secondary photocurrents in a given design. >

The SEU tolerance of the SA3300 microprocessor with feedback resistors is presented and compared to the SA3300 without feedback resistors and to the commercial version (NS32016). Upset threshold at room temperature increased from 23 MeV-cm/sup 2//mg with no feedback resistors to 60 MeV-cm/sup 2//mg and 180 MeV-cm/sup 2//mg with feedback resistors of 50 k Omega and 160 k Omega , respectively. The performance goal of 10 MHz over the full temperature range of -55 degrees C to +125 degrees C is exceeded for feedback resistors of 160 k Omega and less. Error rate calculations for this design predict that the error rate is less than once every 100 years when 50 k Omega feedback resistors are used in the D-latch design. Analysis of the SEU response using a lumped-parameter circuit simulator imply a charge collection depth of 4.5 mu m. This is much deeper than what one would expect for prompt collection in the epi and funnel regions and has been explained in terms of diffusion current in the heavily doped substrate. >

A detailed characterization is presented of the single-event upset (SEU) sensitivity of the SA3300 microprocessor focusing specifically on the internal general-purpose registers. SEU response is explored as a function of temperature and logic state of the registers. The effects of two different design variations on SEU vulnerability are outlined. Microprobe measurements using a pulsed Nd:YAG laser suggest that the observed pattern dependence for both design revisions is due to bipolar photocurrent in a vertical n/sup +/pn transistor. A slight temperature dependence was observed in both design revisions. This is consistent with the use of oversized restoring transistors to minimize SEU vulnerability rather than polysilicon feedback resistors. More recent data show threshold above 120 MeV-cm/sup 2//mg with 80-k Omega feedback resistors. >

The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton energies and temperature. SRAMs from five different vendors were irradiated at proton energies from 20 to 500 MeV and at temperatures of 25/spl deg/ and 85/spl deg/C. For the SRAMs and radiation conditions examined in this work, proton energy SEL thresholds varied from as low as 20 MeV to as high as 490MeV. To gain insight into the observed effects, the heavy-ion SEL linear energy transfer (LET) thresholds of the SRAMs were measured and compared to high-energy transport calculations of proton interactions with different materials. For some SRAMs that showed proton-induced SEL, the heavy-ion SEL threshold LET was as high as 25MeV-cm/sup 2//mg. Proton interactions with Si cannot generate nuclear recoils with LETs this large. Our nuclear scattering calculations suggest that the nuclear recoils are generated by proton interactions with tungsten. Tungsten plugs are commonly used in most high-density ICs fabricated today, including SRAMs. These results demonstrate that for system applications where latchups cannot be tolerated, SEL hardness assurance testing should be performed at a proton energy at least as high as the highest proton energy present in the system environment. Moreover, the best procedure to ensure that ICs will be latchup free in proton environments may be to use a heavy-ion source with LETs /spl ges/40 MeV-cm/sup 2//mg.

The Westinghouse SA3823 64K E/sup 2/PROM radiation-hardened SONOS non-volatile memory exhibited a single-event-upset (SEU) threshold in the read mode of 60 MeV-cm/sup 2//mg and 40 MeV-cm/sup 2//mg for data latch errors. The minimum threshold for address latch errors was 35 MeV-cm/sup 2//mg. Hard errors were observed with Kr at V/sub P/= 8.5 V and with Xe at programming voltages (V/sub P/) as low as 7.5 V. No hard errors were observed with Cu at any angle up to V/sub P/=11 V. The system specification of no hard errors for Ar ions or lighter was exceeded. No single-event latchup (SEL) was observed in these devices for the conditions examined. The Analog Devices AD7876 12-bit analog-to-digital converter (ADC) had an upset threshold of 2 MeV-cm/sup 2//mg for all values of input voltage (V/sub in/), while the worst-case saturation cross section of /spl sim/2/spl times/10/sup -3/ cm/sup 2/ as measured with V/sub in/=4.49 V. No latchup was observed. The Intel 82C527 serial communications controller exhibited a minimum threshold for upset of 2 MeV-cm/sup 2//mg and a saturation cross section of about 5/spl times/10/sup -4/ cm/sup 2/. For latchup the minimum threshold was measured at 17 MeV-cm/sup 2//mg, and cross section saturated at about 3/spl times/10/sup -4/ cm/sup 2/. Error rates for the expected applications are presented.

A BESOI 4K SRAM was characterized in transient and total dose radiation environments. Transient upset level was explored as a function of radiation pulse width. A total dose experiment was performed to determine the level at which read or write failures occurred. In addition the total dose level at which imprinting occurred was determined. It was shown that devices fabricated in bonded and etchback (BESOI) technology should exhibit high dose-rate upset levels (above 10/sup 10/ rad(Si)/s) but may not be applicable for high total dose uses, especially if total dose imprinting is detrimental to the system. Total dose failures were observed above 4.3/spl times/10/sup 5/ rad(SiO/sub 2/) and imprinting occurred between 4 and 6/spl times/10/sup 4/ rad(SiO/sub 2/).

Neutron-induced single-event latchup has been studied in SRAMs manufactured by several different vendors. These SRAMs span different cell designs (six-transistor and four-transistor cells), technology generations (0.25 /spl mu/m to 0.14 /spl mu/m) and power supplies (5 V to 1.5 V). While some technologies appear to be latchup-free in neutron environments, others have neutron-induced latchup failure-in-time (FIT) rates as high as 300 FIT/Mbit at room temperature and maximum rated voltage. Latchup FIT rates increase dramatically with temperature. The observed latchup rates can lead to very high failure rates in systems with large amounts of memory, and cannot be circumvented using error correction.

In this work we compare neutron-induced soft error rates (SER) and latchup in SRAMs from a variety of manufacturers. SER is found to vary widely between different vendors and technology generations, and some SRAMs show extreme sensitivity to neutron-induced latchup. Continuous spectrum neutron and monoenergetic proton accelerated soft error rate test methods are compared.

A monolithic dose-rate nuclear event detector (NED) has been evaluated as a function of radiation pulse width. The dose-rate trip level of the NED was evaluated in 'near' minimum and maximum sensitivity configurations for pulse widths from 20 to 250 ns and at dose rates from 10/sup 6/ to 10/sup 9/ rads(Si)/s. The trip level varied up to a factor of approximately 16 with pulse width. At each pulse width the trip level can be varied intentionally by adding external resistors. Neutron irradiations caused an increase in the trip level, while electron irradiations, up to a total-dose of 50 krads(Si), had no measurable effect. This adjustable dose-rate-level detector should prove valuable to designers of radiation-hardened systems. >

A comparison of the radiation tolerance of three commercial and one radiation hardened SRAM is presented for total dose, dose rate, and single event effects environments. The devices are categorized according to radiation hardness within each environment and the necessity of considering all applicable environments is enforced. Burn-in effects on radiation hardness are shown for each of the environments.

We present a compendium of optocoupler radiation test data including data on neutron, proton and heavy ion displacement damage (DD), single event transients (SET) and degradation due to total ionizing dose (TID). Proton data includes ionizing and non-ionizing damage mechanisms.

The single-event upset (SEU) responses of 16 Kbit to 1 Mbit SRAMs irradiated with low and high-energy heavy ions are reported. Standard low-energy heavy ion tests appear to be sufficiently conservative for technologies down to 0.5 {micro}m.

Reactor neutron environments can be used to test/screen the sensitivity of unhardened commercial SRAMs to low-LET neutron-induced upset. Tests indicate both thermal/epithermal (< 1 keV) and fast neutrons can cause upsets in unhardened parts. Measured upset rates in reactor environments can be used to model the upset rate for arbitrary neutron spectra.

A comparison of the radiation tolerance of three commercial, and one radiation hardened SRAM is presented for four radiation environments. This work has shown the difficulty associated with strictly categorizing a device based solely on its radiation response, since its category depends on the specific radiation environment considered. For example, the 3.3-V Paradigm SRAM could be considered a radiation-tolerant device except for its SEU response. A more useful classification depends on the methods the manufacturer uses to ensure radiation hardness, i.e. whether specific design and process techniques have been used to harden the device. Finally, this work has shown that burned-in devices may fail functionally as much as 50% lower in total dose environments than non-burned-in devices. No burn-in effect was seen in dose-rate upset, latchup, or SEE environments. The user must ensure that total dose lot acceptance testing was performed on burned-in devices.

Total-dose failure mechanisms are identified over a wide range of dose rate for 2K and 16K SRAMs from hardened and commercial CMOS technologies. Failure was defined "parametrically," such that an IC fails if one of its parameters, e.g., static power supply current or timing, exceeds a preset specification following irradiation. These studies demonstrate that the dominant failure mechanisms of SRAMs in space radiation environments are often quite different than those observed at considerably higher laboratory dose rates specified by DoD test guidelines, i.e., 100 to 300 rad(Si)/s. In addition, the total-dose hardness of SRAMs varied significantly between laboratory and space dose rates. Several approaches are discussed for predicting total-dose hardness of ICs in space from laboratory measurements. Results are also presented for transistors irradiated over the same range of dose rate (200 to 0.02 rad(Si)/s) and at all biases, i.e., N-on/off and P-on/off. These transistor measurements are used to characterize the physical mechanisms that govern the radiation response of the more complex SRAMs. In a surprising result, a dose-rate dependence for the buildup of radiation-induced interface states was observed. At dose rates from 200 to 0.02 rad(Si)/s, the number of interface states at a given total dose increased as the dose rate decreased.

A correlation is made between observed photoionization induced avalanche breakdown in epitaxial structures and the analysis of high-current effects in these devices using Poisson's equation. The analysis shows that a photocurrent-stimulated conductivity modulation mechanism can lead to avalanche at the epitaxial-substrate junction at bias levels far below the usual breakdown voltages for the structures. Experimental data are presented for both VDMOS power-FET devices and bipolar npn epitaxial transistors which show junction avalanche at low bias levels.

N-channel MOS transistors used in nMOS and in CMOS microelectronic circuits have a drain-to-source breakdown characteristic showing a negative resistance region. Activating this mode of operation leads to a drop in source-to-drain voltage and to a large drain current. Snap-back is not a four-layer (SCR, latch-up) phenomenon, but, like latch-up, can be initiated by current injection into the p-well, by avalanching junctions or by exposure to ionizing radiation. The sustaining voltage can be significantly below the drain-substrate avalanche voltage thereby limiting the maximum operating voltage. In this paper we present a qualitative model for snapback--local conductivity modulation occurring in the intrinsic base region of the parasitic bipolar transistor leading to regenerative feedback. Effects of process variations on the snap-back characteristics are presented as are triggering sensitivities to ionizing radiation.

A radiation hardened nonvolatile MNOS RAM (SA2998) is being developed at Sandia National Laboratories. The memory organization is 128 × 8 bits and utilizes two p-channel MNOS transistors per memory cell. The peripheral circuitry is constructed with CMOS metal gate and is processed with standard Sandia rad-hard processing techniques. The device requires +10 V and +25 V for operation. The devices have memory retention after a dose-rate exposure of lE12 rad(Si)/s, are functional after total dose exposure of 1E6 rad(Si), and are dose-rate upset resistant to levels of 7E8 rad(Si)/s.