1. Management of Power and Performance with Stress Memorization Technique for 45nm CMOS
- Author
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Naoki Nagashima, Y. Shiozaki, M. Nakazawa, A. Eiho, K. Ota, M. Ikeda, T. Kuwata, M. Iwai, Y. Enomoto, Kitano, T. Sawada, T. Sanuki, M. Saito, Toshiyuki Iwamoto, Kiyotaka Imai, Eiji Morifuji, K. Ohno, G. Sudo, K. Nagaoka, O. Fuji, Hiroshi Naruse, K. Fukasaku, Mitsuhiro Togo, Takahiro Ito, H. Nii, H. Tsuda, Fumiyoshi Matsuoka, N. Fuji, H. Yamazaki, S. Muramatsu, K. Yoshida, S. Yamada, and S. Iwasa
- Subjects
Power management ,Stress (mechanics) ,Surface-mount technology ,chemistry.chemical_compound ,Materials science ,chemistry ,CMOS ,Energy management ,Capacitive sensing ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Leakage (electronics) ,Silicon-germanium - Abstract
The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule (190 nm) in 45 nm technology node.
- Published
- 2007