1. Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology
- Author
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Ph. Galy, M. Vinet, Sorin Cristoloveanu, G. Delahaye, Lorena Anghel, L. de Conti, STMicroelectronics [Crolles] (ST-CROLLES), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
- Subjects
Silicon ,Computer science ,chemistry.chemical_element ,Silicon on insulator ,Topology (electrical circuits) ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Topology ,01 natural sciences ,Porting ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Electrical and Electronic Engineering ,Thin film ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Safety, Risk, Reliability and Quality ,ComputingMilieux_MISCELLANEOUS ,010302 applied physics ,Electrostatic discharge ,020208 electrical & electronic engineering ,Condensed Matter Physics ,Atomic and Molecular Physics, and Optics ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,PACS 8542 ,chemistry ,CMOS ,Node (circuits) - Abstract
The electrostatic discharge (ESD) protection is always a challenge for fully depleted silicon on insulator (FD-SOI) CMOS technology. Today, several efficient and robust solutions are available. In the framework of optimized solutions, it is interesting to investigate a protection according to its topology and design. First of all, this study will be based on 3D TCAD analysis of thin silicon film Bipolar MOS (BIMOS) devices with standard topology and with optimized body access. Then the design will be modified by adding new devices or by adjusting the parasitic elements. The aim is to better understand the device behavior and to push the performance. Additionally, silicon demonstrators have been fabricated, characterized and investigated. It appears that each design has advantages and drawbacks and should be chosen in accordance with the final implementation. The proposed design can also be ported to another technology node with an adaptation.
- Published
- 2019
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