Search

In this article, the development and optimization of carrier-selective and passivating contacts by industry-scale inline plasma-enhanced chemical vapor deposition and their successful integration into solar cells are reported. Amorphous Si thin films with varying carbon content (SiC x ) were deposited on a thermally grown ultrathin tunnel oxide (TOPCon) and electrically characterized. Furthermore, the impact of a vacuum break (VB) during the deposition of a layer stack consisting of intrinsic amorphous Si [a-Si:H(i)] and boron-doped SiC x was investigated. That is, samples that were processed with VB were exposed to ambient air, and hence, a thin native oxide was formed on the a-Si:H(i) layer, which affected the boron diffusion into the absorber resulting in a distinct anneal behavior of the contacts. Upon optimization, these layers provided an excellent surface passivation quality, which was reflected in an implied open-circuit voltage of 733 mV for n-type and 716 mV for p-type TOPCon structures, respectively. In addition, very low contact resistivities of 0.3 mO⋅cm² for n-type and 0.5 mO⋅cm² for p-type TOPCon were measured, respectively. These optimized TOPCon structures were implemented into both sides contacted p-type laboratory solar cells. After a two-step furnace anneal, these cells achieved a maximum energy conversion efficiency of 22.7% with evaporated contacts.

The performance of a low-resistive p + /n + poly-Si tunneling junction (SiTJ) based on a tunnel oxide passivating contact in dependence on the thermal budget of the applied post-deposition treatment is studied. We present two approaches to reduce the performance limiting parasitic dopant interdiffusion and, thus, the contact resistivity, without impairing the passivation quality. Both, carbon-alloying of poly-Si layers and the application of diffusion blocking interlayers are effective means to maintain a low contact resistivity of ∼24 mOcm 2 at high thermal process temperatures of up to 950 °C. Those low values are obtained using either a standard furnace anneal or a rapid thermal process (RTP). We report on promising results toward a lean process sequence using only one single fast thermal treatment (RTP-only). As a main result, the flexibility for engineering and fabrication of our SiTJ was markedly improved, eventually facilitating industrially feasible perovskite/silicon tandem solar cells. One aspect being higher post-deposition temperatures needed for, e.g., bottom cell rear side contact formation and the first layers of the perovskite to cell.

The discovery of ferroelectricity in thin films of doped hafnium oxide has led to a renaissance of ferroelectric (FE) memory concepts. Compared to all inspected dopants, zirconium doped hafnium oxide (HZO) crystallizes at the lowest temperatures. Thus, this material system is ideal for the implementation of FE functionalities into the back-end-of-line (BEoL). So far, the FE phase is achieved by rapid thermal annealing (RTA) of prior amorphous HZO films. Recently, it was shown that a sole furnace anneal at 400°C is sufficient to functionalize the films. Herein, a wide range of annealing conditions are compared in order to further reduce the thermal budget and the number of process steps. It is found that furnace-annealing at 300°C for 1 h crystallizes the HZO films in the FE phase. With respect to crystallinity, these films show no significant degradation compared to films annealed at 400°C. Nevertheless, the remanent polarization reduces slightly with temperature, but is still sufficient even at 300°C.

A novel firing stable $n^{+}/p^{+}$ poly-Si tunnel junction (TJ) was realized for the first time using industrial tools on 6-inch Czochralski (Cz) silicon substrates. After being subjected to a fast firing furnace anneal, the TJ showed minimal degradation from its peak iV OC of 700mV and the contact resistance, $\rho_{\mathrm{c}}$ decreased from 0.9 to 0.5 Ohmcm2. To further test the viability of the TJ, it was integrated onto a bi-polysilicon double-side passivated-contact solar cell, achieving a fill factor (FF) of approximately 80% and an absolute infrared efficiency of up to 26.7% (1 cm2). The successful proof-of-concept demonstration creates an opportunity for an entirely new type of TJ to be seamlessly deployed on top of a silicon cell for 2-terminal thin-film on silicon tandems.

As novel semiconductor and dielectric materials become more prevalent in MOS device technology, MOS capacitors are used to investigate the quality of semiconductor/dielectric, semiconductor/contact, and dielectric/metal gate interfaces, through capacitance-voltage (C-V) and I-V testing along with physical materials characterization. Thermal processes such as implant stabilization, contact annealing, and dielectric postdeposition annealing must be managed to accomplish the desired results while minimizing undesirable side effects such as interdiffusion or dopant migration in devices. This can be done through a combination of device and process design, which prevents these unwanted effects through careful material selection, ordering of process steps, temperature adjustments where possible, and selection of process gases used during thermal treatments. This study focuses on the effects of a 430 °C forming gas anneal, which produced an unusual brown layer on Ti/Au metal-oxide-semiconductor capacitor gates. A series of experiments, XPS analysis, and C-V electrical data revealed that the brown layer was not an organic residue but a thin layer of TiO2 on the gold surface, which formed due to Ti diffusion to the Au surface during the forming gas anneal. Oxygen plasma treatment before the furnace anneal enhanced the undesirable diffusion effect. Replacing the Ti/Au gates with Cr/Au gates prevented the brown layer and improved capacitance-voltage characteristics.

The radiation damage effects and enhancement the thermoluminescence (TL) efficiency of LiF:Mg,Ti (TLD-700)dosimeters via sensitization method were discussed. Attempts to eliminate the effects of damage and sensitization were made using different types of annealing processes. The results showed that after irradiating the dosimeters with dose > 250 Gy of 60Co gamma source, damage effects were observed. The sensitivity of the total area under the curve was decreased by a factor of ∼0.5 after irradiation at a pre-test dose of 2 kGy. However, the effects of radiation damage on each glow-peak are different. The glow-peak 2 was the only peak that was not affected by the high-dose irradiation. It has been shown that the degree of the radiation damage effect is related to the maximum dose-response function, f ( D ) max of the glow-peak. In general, significant radiation damage effects were observed for the glow-peaks of high f ( D ) max . Post-irradiation anneal at 280 °C for 30 min causes dramatic effects on the shape of the glow-curve and as well as on the sensitivity of the dosimeters. An increasing by a factor of ∼35 in the sensitivity of the total area under the curve was observed at a pre-test dose of 2 kGy. Improving the sensitivity of peak 7 by a factor of∼22 was the dominant factor in increasing the sensitivity of the dosimeters. On the other hand, an increasing by factors of ∼2.5 and ∼4 was found for peaks 2 and 5 respectively. On the other hand, a decreasing by a factor ∼0.5 was observed for peaks 3 and 4. At pre-test dose levels >250 Gy, a very strange and high intensity tail was observed in the high-temperature region of the glow-curves. The readout anneal was not enough to remove this tail. While, the furnace anneal could eliminate the sensitization effects but not the radiation damage effects on the sensitivity of the dosimeters.

Every advance in technology node challenges the semiconductor industry to achieve even tighter on-product overlay (OPO) requirements. With the latest immersion scanners performing well below the sub-2-nm overlay level, the OPO budget is more and more determined by non-lithography contributors. Achieving the tight overlay specifications in a high-volume manufacturing environment is therefore far from trivial, especially in the wafer edge region where processing is even less well controlled. For example, Reactive Ion Etch (RIE), the deposition of stressed thin films and the presence of significant intra-field (or intra-die) stress distributions are all known to cause localized distortions in the wafer edge region. Annealing steps during integrated circuit manufacturing are another source of wafer deformation. Furnace anneal is one particular type of annealing step. During furnace anneal processing, many wafers are heated-up simultaneously and wafers stay at elevated temperatures for a fixed time on the order of minutes to hours. Although in general, furnace anneal does not cause significant wafer deformations, local distortions are sometimes observed in the wafer edge region by using standard boats at higher anneal temperatures. In this work, we have setup a controlled experiment to characterize the local distortions that can be induced by furnace anneal processes. To this end, wafers are processed with various furnace anneal settings, i.e. temperature and ramp rate, and two different boat types are used. The induced distortions are accurately and densely measured on an NXT:1970Ci scanner using its SMASH alignment system. We will see that, depending on the process conditions and boat type, local distortions occur at the wafer edge. The locations of these distortions coincide with the wafer support positions of the boat and therefore they are also referred to as boat marks. Several solution directions for mitigating furnace anneal induced distortions will be discussed. A very effective solution is the employment of an optimized boat design that, depending on the process conditions, can prevent the localized distortions at elevated temperatures. It would therefore be beneficial to have a detection system in place that can detect and consequently trigger actions to mitigate furnace anneal induced distortions during the development phase of anneal processing steps. We will demonstrate that the scanner can be used as such a detection system as its inline metrology is able to detect signatures related to the boat marks.

We present a p+/n+ poly-Si tunneling junction (TJ) based on a tunnel oxide passivated contact (TOPCon) that enables both low contact resistivity ρc and high implied open-circuit voltages iVoc. It will be shown that the charge carrier profile of the TJ and the junction resistance are strongly affected by the applied thermal budget, consisting of a furnace anneal and/or a rapid thermal processing treatment, and the deposition parameters of the a-Si layers. A minimum combined junction resistance of the p+/n+ poly-Si/SiOx stack of less than 10 mΩ cm2 and iVoc of up to 726 mV at 1 sun illumination is reported. This work aims for incorporation of our p+/n+ poly-Si TJ into an industrially feasible tandem solar cell featuring a Si bottom cell with a TOPCon front emitter and the industrial standard technology of a passivated emitter and rear cell rear structure.

Nitrogen-doped Czochralski (NCZ) silicon has been a base material for integrated circuits. The interaction between nitrogen (N) and interstitial oxygen (Oi) atoms in the low temperature regime (300–650 °C), which leads to N–O complexes in the form of NOx (x = 1, 2, or 3), forms a series of shallow thermal donors (denoted as N–O STDs). Such N–O STDs are detrimental to the stability of electrical resistivity of NCZ silicon. In this work, we have experimentally investigated the elimination of N–O STDs in NCZ silicon by means of conventional furnace anneal (CFA) and rapid thermal anneal at elevated temperatures ranging from 900 to 1250 °C, aiming to explore the underlying mechanism. It is found that most of the N–O STDs formed in NCZ silicon can be eliminated by a very short period of anneal at the aforementioned temperatures, providing solid evidence for the viewpoint that the elimination of N–O STDs is ascribed to the decomposition of N O x complexes. Somewhat unexpectedly, the residual N–O STDs are much more after the 1250 °C/2 h CFA than after the 900 °C/2 h or 1000 °C/2 h counterpart, which is found to be due to the fact that more nitrogen pairs [(N2)s] are remaining after the 1250 °C/2 h CFA. It is proposed that most of the (N2) atoms are involved in the growth of grown-in oxide precipitates during the 900 or 1000 °C/2 h CFA. The first-principles calculations and molecular dynamics simulation indicate that the elimination of N–O STDs is essentially ascribed to the destruction of “NO ring” that is the core of NOx complexes. Furthermore, based on the experimental and theoretical results, we have made a thorough thermodynamic analysis to account for the details of elimination of N–O STDs as revealed in this work. It is believed that our experimental and theoretical studies have gained more insight into the N–O STDs in NCZ silicon.

In this paper, the charge trapping and decay mechanism is investigated in post deposition rapid thermal anneal (RTA) and furnace anneal (FA) erbium oxide (Er2O3) ultrathin films by Kelvin probe force microscopy (KPFM) technology. The trap density is calculated by the contact potential difference measurements obtained from KPFM. Furthermore, it is compared with the trap density calculated from the electrical measurements for Er2O3 MOS capacitors to give an insight on the reliability of KPFM for trap density estimation. Experimental results showed that post deposition RTA treatment results in higher trapping as compared to FA treatment on Er2O3 ultrathin films. It was observed that vertical charge leakage plays a dominant role in Er2O3 as compared to lateral charge spreading. The space-charge-limited conduction mechanism was observed in Er2O3 MOS capacitors, which was used to study the charge injection and decay mechanism. This investigation may help to fill the trap density computation gaps between nanoscopic KPFM and macroscopic capacitance–voltage-based electrical measurements for nanoscale MOS-based applications.

The formation of high resistivity phases of nickel silicide in a small silicide area is a problem for the uniformity of the sheet resistance. It was found that implementing furnace annealing method, as the first annealing step, improves the nickel silicide sheet resistance uniformity at small areas. Low ramp rate and prolonged annealing duration by furnace anneal promote grain size growth of Ni 2 Si phase, which decreases the free energy change and suppresses the formation of high resistivity phases of nickel silicide. Increasing the first anneal temperature was also found to improve the sheet resistance uniformity of only p + active areas. Furthermore, increasing the temperature of Ni PVD stage or second anneal, promotes the formation of NiSi 2 phase.

The structural and morphological transformations of TiO 2 nanotube arrays (TNAs) treated by excimer laser annealing (ELA) were investigated as a function of the laser fluence using parallel and tilted modes. Results showed that the crystallinity of the ELA-treated TNAs reached only about 50% relative to that of TNAs treated by furnace anneal at 400 °C for 1 h. The phase transformation starts from the top surface of the TNAs with surface damage resulting from short penetration depth and limited one-dimensional heat transport from the surface to the bottom under extremely short pulse duration (25 ns) of the excimer laser. When a tilted mode was used, the crystallinity of TNAs treated by ELA at 85° was increased to 90% relative to that by the furnace anneal. This can be attributed to the increased area of the laser energy interaction zone and better heat conduction to both ends of the TNAs.

A deep level transient spectroscopy (DLTS) study of defects created by low-fluence, low-energy ion implantation for development of ion-implanted silicon field-effect transistors for spin-dependent transport experiments is presented. Standard annealing strategies are considered to activate the implanted dopants and repair the implantation damage in test metal-oxide-semiconductor (MOS) capacitors. Fixed oxide charge, interface trapped charge and the role of minority carriers in DLTS are investigated. A furnace anneal at 950 $\rm ^{o}$C was found to activate the dopants but did not repair the implantation damage as efficiently as a 1000 $\rm ^{o}$C rapid thermal anneal. No evidence of bulk traps was observed after either of these anneals. The ion- implanted spin-dependent transport device is shown to have expected characteristics using the processing strategy determined in this study., 4 pages, 6 figures

Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called ‘impurity engineering (IE)’, is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

It is well known that Si ion implantation into SiO 2 and subsequent high temperature anneals induce the formation of embedded luminescent Si nanocrystals. In this work, the potentialities of rapid thermal annealing to enhance the photoluminescence as well as those to induce low temperature formation of luminescent Si nanocrystals have been investigated. Ion implantation was used to synthesize specimens of SiO 2 containing supersaturated Si with different concentrations. The implanted samples were rapidly annealed only for a few minutes. After that, in some cases before that, the samples were annealed for a few hours using a conventional tube furnace to induce Si precipitation. Photoluminescence spectra were measured at various stages of anneal processes. The luminescence intensity is strongly enhanced with a rapid thermal annealing prior to a conventional furnace anneal. The luminescence intensity, however, decreases when rapid thermal annealing follows conventional furnace annealing. It is found that the order of heat treatment is an important factor in intensities of the luminescence. Enhancement is found to be typical for low dose samples. Moreover, the visible photoluminescence is found to be observed even after conventional furnace anneal below 1000 °C, only for rapidly thermal annealed samples. Based on our experimental results, we discuss the mechanism for the enhancement of the photoluminescence, together with the mechanism for the initial formation process of Si nanocrystals.

Si ion implantation into SiO 2 and subsequent high temperature anneals induce the formation of embedded luminescent Si nanocrystals. The potentialities of rapid thermal annealing to enhance the photoluminescence as well as those to induce low temperature formation of luminescent Si nanocrystals have been investigated. Si ion implantation was used to synthesize specimens of SiO 2 containing supersaturated Si with different concentrations, from 4 to 16% in excess. The implanted samples were rapidly annealed only for a few minutes. After that, in some cases before that, the samples were annealed for a few hours using a conventional quartz tube furnace to induce Si precipitation. Photoluminescence spectra were measured at various steps of anneal processes. The luminescence intensity is strongly enhanced with a rapid thermal annealing prior to a conventional furnace anneal. The luminescence intensity, however, decreases when rapid thermal annealing follows conventional furnace annealing. It is found that the order of heat treatment is an important factor in intensities of the luminescence. Enhancement is found to be typical for low dose samples. Moreover, the visible photoluminescence is found to be observed even after conventional furnace anneal below 1000 °C, only for rapidly thermal annealed samples. Based on our experimental results, we discuss the mechanism for the enhancement of the photoluminescence, together with the mechanism for the initial formation process of luminescent Si nanocrystals.

For Ni silicidation a lamp based anneal, a furnace anneal and a heater based anneal have been used. Ni silicidation on unstructured Si wafers is characterized by means of sheet resistance, XRD and AES. In the second part of this paper the characterization is extended to product wafers using sheet resistance measurements, transistor performance and product yield to investigate the suitability of the different techniques and processes. We will show that all of the above techniques are suitable for NiSi formation if the thermal budget of the 1st anneal step is sufficient to react enough Ni to Ni rich silicide phases or NiSi. A 2nd anneal step after sequential Ni strip has been found to be of minor importance as the backend processing will finish the NiSi formation in case of Nickel rich phases being left after the Ni 1st anneal step. In the direct comparison of NiSi vs. CoSi the former showed equivalent or better yield and performance.

It is well known that Si ion implantation into SiO 2 and subsequent high-temperature anneals induce the formation of embedded luminescent Si nanocrystals. In this work, the potentialities of rapid thermal annealing to enhance the photoluminescence intensity have been investigated. Ion implantation was used to synthesize specimens of SiO 2 containing excess Si with different concentrations. Si precipitation to form nanocrystals in implanted samples takes place with a conventional furnace anneal. The photoluminescence intensity and the peak energy of emission from Si nanocrystals depend on implanted ion dose. Moreover, the luminescence intensity is strongly enhanced with a rapid thermal annealing prior to a conventional furnace anneal. The luminescence intensity, however, decreases when rapid thermal annealing follows conventional furnace annealing. It is found that the order of heat treatment is an important factor in intensities of the luminescence and that the luminescence peak energy is found to be dependent, but only by a small factor, on the thermal history of specimens. Enhancement is found to be typical for low dose samples. Furthermore, the observation that the prolonged anneal induces saturation and a blue shift of the luminescence strongly indicates the emission is not simply due to electron–hole recombination inside the Si nanocrystals. Based on our experimental results, we discuss the mechanism for the enhancement of the photoluminescence, together with the mechanism of photoemission.

The effect of the prior conventional furnace anneal at 1250 °C with different cooling rates on oxygen precipitation in Czochralski silicon during the subsequent low–high two-step heat treatment was investigated. In comparison with oxygen precipitation in the as-received sample, that in the samples with the prior 1250 °C anneal with fast or slow cooling rate was significantly enhanced. It is believed that the prior 1250 °C anneal with fast cooling rate introduced a considerable amount of vacancies, thus enhancing oxygen precipitation in the subsequent anneal; while, that with slow cooling rate substantially removed the silicon interstitials generated during the formation of grow-in oxygen precipitates, thus eliminating the retard effect on oxygen precipitation in the subsequent anneal.

Potentialities of rapid thermal annealing to enhance the photoluminescence emission of Si nanocrystals in SiO2 have been investigated. Ion implantation was used to synthesize specimens of SiO2 containing excess Si with different concentrations. Si precipitation to form nanocrystals in implanted samples takes place with a conventional furnace anneal. The photoluminescence intensity and the peak energy of emission from Si nanocrystals depend on implanted ion fluence. Moreover, the luminescence intensity is strongly enhanced with a rapid thermal anneal prior to a conventional furnace anneal. The luminescence intensity, however, decreases with a rapid thermal anneal following a conventional furnace anneal. It is found that the order of heat treatment is an important factor in intensities of the luminescence. Moreover, the luminescence peak energy is found to be dependent, but a little, on thermal history of specimens. Based on our experimental results, we discuss about the mechanism of an enhancement of the photoluminescence, together with the mechanism of photoemission from encapsulated Si nanocrystals produced in a SiO2 matrix by ion implantation and annealing.

We report the direct correlation between chemical bonding and the physical-electrical properties of oxynitride (SiON). Through comparing oxynitrides grown by furnace anneal and by plasma method in the low-nitrogen-concentration region (

With the integration of copper as a conductive material in interconnects, post-electroplating anneal plays a key role in controlling the copper characteristics. Meanwhile, there is a constant need to reduce the thermal budget in the back-end processes. In this context, short on-board anneals are an interesting alternative to long batch furnace thermal treatments. In this work, we evaluate the impact of such short anneals on copper properties. Microstructural, mechanical and contamination results show that short on-board anneals at 400 °C offer performances that are similar to longer furnace anneals at the same temperature, whereas 250 °C anneals are clearly insufficient. Integration issues such as copper adhesion are investigated.

The transient ion drift (TID) technique has been recently proposed for copper trace detection in silicon. Cu atoms may be present either in the vicinity of the Si surface or within the volume. In the latter case they are either gathered at secondary defects or form precipitates believed to be silicides. In order to become detectable by TID Cu atoms must be put into the highly mobile interstitial state. Depending on the initial configuration of the Cu/Si system different physical mechanisms may enable Cu atoms to become ‘TID active’. In this work we study the Cu activation process using rapid thermal processing (RTP) in an attempt to minimise the thermal budget required to achieve a complete activation. Both, surface and volume contaminated samples are investigated. During RTP treatments the activation of surface Cu atoms is found to proceed significantly faster than during standard furnace anneal. We tentatively attribute this behaviour to the UV light exposure associated with the RTP, which may enhance the release of copper atoms from the surface. The dissolution kinetics of the Cu precipitates occurring during RTPs are found to be only limited by Cu diffusion. The RTP/TID process is used to study the low temperature reaction path of supersaturated Cu. If prior to the RTP process, Cu atoms are chemically removed from the surface or near surface region, TID measures only the residual bulk Cu atoms. Our results show that out-diffusion and near-surface precipitation are reducing mostly the copper supersaturation.

Ultra-shallow junction layers are required for deep submicron CMOS and quantum devices. Low-temperature (320 °C) molecular-beam epitaxy was used to form highly conductive, ultra-shallow layers in silicon using boron delta doping. The as-grown junction depths, determined with secondary ion mass spectrometry, ranged from 7 to 18 nm. A minimum resistivity of 3 x 10 -4 Ω-cm was obtained when the delta-doped layers were spaced 2.5 nm apart. The sheet resistances of the epitaxial layers, plotted as a function of junction depth, followed the theoretical curve for a box-doped layer having a boron doping concentration equal to the solid solubility limit, 6 x 10 20 cm -3 . Minimal change was detected in either the atomic profiles or the resistivity after a 10 s rapid thermal anneal (RTA) or a 10 min furnace anneal (FA) up to 700 °C. The sheet resistance of the as-grown shallow junction are substantially less than that obtained by ion implantation. Only after the 800 °C FA did the MBE-grown layers degrade to have as large a sheet resistance as the best ion implanted layers.

The complementary metal oxide semiconductor (CMOS) process technology in a 300 mm wafer fab experienced wafer center yield loss. In-line wafer defect inspection revealed gross silicon pitting at the wafer center as the root cause of the yield loss. Affected dies showed pitting at the interfacial corner between the silicon substrate and the isolation oxide. The mechanism of silicon pitting involves creation of silicon microdefects during several high-temperature furnace anneal process steps (liner oxide and posthigh energy phosphorus implant anneals) because of local die and global wafer level thermally induced mechanical stress at the silicon substrate to isolation oxide interfacial corner. In addition, implant-induced silicon microdefects from a high energy (>2 MeV) phosphorus implant, extending to the silicon surface provide a further significant contribution to the silicon microdefect population. The overall microdefect population is further aggravated by Ostwald ripening during a subsequent thick silicon-oxide furnace growth process, resulting in sufficient corner silicon microstructure damage to enhance wet-etching during a subsequent wet-clean leading to gross silicon pitting. Silicon pitting is eliminated by lowering either the liner oxide or postimplant anneal temperatures or skipping the high energy phosphorus implant. Incorporating a reduced liner oxide anneal temperature into the CMOS process flow eliminated the wafer-level yield loss at the wafer center associated with gross silicon pitting defects.

Lead scandium titanate (PST) thin films were deposited by RF dual magnetron sputtering and then annealed either by vacuum furnace or combined rapid thermal annealing (RTA) and furnace anneal. The film structure was investigated by x-ray diffraction, scanning electron microscopy and transmission electron microscopy (TEM) and energy dispersive x-ray spectroscopy techniques. Lead loss was more severe using furnace annealing than the combined RTA and furnace anneal. The annealed films were characterized by the presence of voids and exhibited relaxor ferroelectric characteristics. PST perovskite crystal grains were found to co-exist with pyrochlore matrix in the furnace-only annealed films, whilst in RTA annealed films no apparent pyrochlore morphology was observed in the TEM image. Lead was found to diffuse through the bottom electrode Pt layer during the annealing. Films treated by combining RTA and furnace annealing have shown pyroelectric coefficients under field of up to 500 µC m-2 K-1, a dielectric loss of below 0.007 and a merit figure for thermal detection of 2.5×10-5 Pa-1/2.

This paper describes the deposition of thin film lead scandium tantalate (Pb2ScTaO6) using a novel two target sputtering technique and reports on the effect of post-deposition annealing. The films are deposited on platinum-coated silicon wafers at 300°C and are annealed at a range of temperatures up to 800°C. Vacuum furnace and rapid thermal annealing (RTA) methods are compared. Materials are characterised by X-ray diffraction and show that the as-deposited films form a weak pyrochlore phase which is transformed to perovskite PST by annealing. At anneal temperatures of 750°C and above superlattice ordering is observed. Compositional measurements using Energy Dispersive Spectroscopy show that Lead loss is more severe using furnace annealing than RTA, and a combined RTA/furnace anneal method is proposed. The films demonstrate relaxor dielectric characteristics. Induced pyroelectric measurements have been made to assess the potential of this material for ferroelectric micro-bridge thermal detectors.

This paper investigates the barrier capability of tantalum nitride (TaNx) layers against Cu diAusion. The TaNx layers were reactively sputtered in contact holes to a thickness of 50 nm by using a diAerent nitrogen flow rate. Results indicate that the TaNx layers fail to be a diAusion barrier due to a relative high resistivity for nitrogen flow ratios exceeding 10%. In addition, we found that the phase of a-Ta(‐N) functions as an eAective barrier against Cu diAusion and that Cu/ TaN(3‐5%)/n a ‐p junction diodes are able to sustain a 30 min furnace anneal up to 500∞C without causing degradation of the electrical characteristics. The high-temperature failure of barrier capability for the TaNx layers is due to interdiAusion of Cu and Si across the TaNx film structure to form Cu3Si. The surface roughness and the film structure of TaNx layers determine the ability of Cu and Si interdiAusion. ” 2001 Elsevier Science Ltd. All rights reserved.

Diffusion of boron in compressively strained Si1 –xGex alloy layers grown by rapid pressure chemical vapor deposition has been studied as a function of the composition for 0.0006 ≤ x ≤ 0.15 and annealing temperature. The comparison of the Si1 –xGex samples to the Si samples after rapid thermal and furnace annealing revealed a retarded B diffusion inside the strained Si1 –xGex layers. The influence of the Ge content on the dopant diffusion was also measured and simulated, demonstrating that the diffusion of B was found to decrease with the Ge alloy content and annealing temperature. A simple empirical expression for the B retardation is presented and incorporated into a diffusion model for dopants in heterostructures. Good agreement between the measured and simulated diffusivity that includes the model for strain and chemical effects are obtained. By comparing with experimental values, our extracted (by using experiment and simulation) B diffusivity predicted a lower value (retardation).

In this paper, the diAusion enhanced intermixing eAect in strained InGaAsP multiquantum wells due to plasma immersion ion implantation (PIII) of Ar a and post-implant annealing is presented. Firstly, we report that a 20 kV Ar a PIII at a fluency of 10 16 cm ˇ2 together with a furnace anneal at 650∞C resulted in an enhanced blue shift in the photoluminescence (PL) peak. It was also found that by varying the Ar a dose or the implantation energy, we could control the extent of the implantation induced intermixing. For a sample that had half of the surface shielded during implantation, a bandgap step was observed between the implanted and non-implanted regions. Our results indicate that one can use this technique for localised fine-tuning of the bandgap energy, thus demonstrating its potential as a processing step for the fabrication of integrated photonic devices. ” 2001 Elsevier Science B.V. All rights reserved.

Transient enhanced diffusion of indium implanted in silicon is studied in the presence of the end-of-range (EOR) damage layer. To investigate the effect of EOR defects on the indium diffusion, the samples that were implanted with indium at a high dose (1×1013–5×1014/cm2) sufficient to produce the amorphous layer were prepared. Transmission electron microscopy measurements and Rutherford backscattering spectrometry reveal the amorphization threshold of indium implantation is around 5×1013/cm2 for 200 keV, 115In+ implanted with 100 μA/cm2 beam current density at room temperature. These results are consistent with Monte Carlo simulation of implantation. Monte Carlo simulations indicate the deviation from the plus one model due to the mass effect of indium. After amorphization, following both RTA at 1000 °C and furnace anneal at low temperature (650 and 850 °C) in nitrogen ambient showed the formation of extrinsic EOR dislocation loops below the original amorphous/crystalline interface. During this process, s...

The influence of thermal drive-in and oxidation conditions on minority carrier diffusion length, surface lifetime and density of states at the Si/SiO2 interface is evaluated. The following is found. (a) Wafer-to-wafer variation of crystal-defect concentration leads to a large spread of diffusion length values if furnace anneal is used to drive in metals from the wafer surface into the bulk. The spread is reduced if rapid thermal processing is used instead. (b) Poor Si/SiO2 interface quality (i.e. high density of interface states and low minority carrier surface recombination lifetime) is measured if oxygen contamination during ramp-down is not controlled or test wafers are not protected by dummy wafers during oxidation. The consequences of these results for in-line monitoring of metal contamination and furnace integrity are discussed.

Iron gettering at both implantation‐induced cavities and oxygen precipitates in silicon was experimentally measured and theoretically modeled. Since impurity removal from the near‐surface region is crucial for proper integrated circuit device operation, these experiments strictly tested the viability of each mechanism to sufficiently reduce the near‐surface Fe concentration. Cavities and oxygen precipitates were formed by helium implantation in the near surface region and specific heat treatments, respectively. Low doses of intentionally introduced Fe were gettered with either a short rapid thermal anneal or a long furnace anneal, both at moderate temperatures. The Fe concentration was measured in the near surface region as well as in the cavities. The cavities were found to drastically reduce near‐surface Fe concentrations for both anneals while the oxygen precipitates were only fairly effective for long furnace anneals. Furthermore, for samples with both cavities and oxygen precipitates, the gettering of Fe was only slightly enhanced over samples with only cavities. The experimental results were supported by a semiquantitative agreement with modeling based on previously derived theoretical formalisms. These experimental results clearly show an increased gettering effectiveness of implantation‐induced cavities over oxygen precipitates for impurity removal from the near‐surface region.

The objective of this paper is to understand and quantify the effects of rapid thermal anneal (RTA) on refractive index, thickness, and hydrogen content of plasma‐enhanced, chemical vapor‐deposited (PECVD) silicon nitride films. It is shown that RTA is more effective than identical furnace anneal. A threshold in as‐deposited refractive index value is found, above which the index of a silicon nitride film increases, while the thickness and bonded hydrogen content decreases as result of the RTA. In addition, the magnitude of increase in the index is proportional to the as‐deposited index value. The threshold index value increases with the increase in silicon nitride deposition temperature. A direct correlation is found between the annealing‐induced increase in refractive index and the corresponding decrease in total bonded hydrogen concentration in the PECVD silicon nitride films. Finally, it is shown that the release of bonded hydrogen from the film can passivate defects in the underlying silicon substrate and increase the performance of silicon devices such as solar cells.

Ten nanometers of oxides grown in a conventional diffusion furnace have been annealed at 1050°C in the same diffusion furnace and in a rapid thermal reactor. Their interfacial electrical properties (V FB and D it at midgap) have been determined, and their breakdown quality has been assessed by means of both time zero and time-dependent dielectric breakdown (TZDB, TDDB) experiments. We observed overall improvement of the annealed samples over the control ones that can be explained by the stress relaxation the anneal step provided. In spite of its much shorter duration, however, the rapid thermal anneal (RTA) outperformed the furnace anneal, thus indicating that the improvement is beyond a conventional viscoelastic stress relaxation. In fact the samples that underwent the RTA process exhibited a distinct electron trapping reduction that may explain their better performance. The contradictory results recorded during this investigation between TZDB and TDDB measurements have been shown to arise from the different trapping behavior of the different samples considered.

The effect of ion‐implantation‐induced damage on the resistivity of n‐type GaN has been investigated. H, He, and N ions were studied. The resistivity as a function of temperature, implant concentration, and post‐implant annealing temperature has been examined. Helium implantation produced material with an as‐implanted resistivity of 1010 Ω‐cm. He‐implanted material remained highly resistive after an 800 °C furnace anneal. The damage associated with H implantation had a significant anneal stage at 250 °C and the details of the as‐implanted resistivity were sample dependent. N implants had to be annealed at 400 °C to optimize the resulting resistivity but were then thermally stable to over 800 °C. The 300 °C resistivity of thermally stabilized He‐ and N‐ implanted layers was 104 Ω‐cm, whereas for H‐implanted layers the 300 °C resistivity was less than 10 Ω‐cm.

This work demonstrates the application of pulsed-laser processing for sealing release holes in silicon membranes. Holes in the membrane are sealed without deposition, similar to the silicon surface migration sealing process. In contrast to the 1100°C furnace anneal required for the migration process, the pulsed-laser process localizes the heat to the top few microns of the substrate, with the bulk kept at near to room temperature. In addition, there is no need for special surface treatment, or for a controlled environment. Furthermore, the treatment can be applied to selected regions of the substrate.

The diffusion of boron in single crystal Si from a BF2-implanted polycrystalline Si film deposited on single crystal Si has been accurately modeled. The effective diffusivities of boron in the single crystal Si substrate have been extracted using Boltzmann-Matano analysis and the new phenomenological model for B diffusivity has been implemented in the PEPPER simulation program. The model has been implemented for a range of furnace anneal conditions (800 to 950°C, from 30 min to 6h) and implant conditions (BF2 doses varied from 5×1015 to 2×1016 cm−2 at 70 keV).

A surface-emitting light source array of homojunction visible (660 nm) GaAsP light-emitting diodes (LEDs) has been developed to demonstrate the feasibility of new microimaging techniques in vertical optical interconnects. The fabrication process used to create arrays of these independently addressable light sources is described. A study of contact annealing showed that a two-step furnace anneal yielded higher radiance devices than rapid thermally annealed devices. A 4*4 array was used with a reflective focusing diffractive optic element to image light onto photodetectors, thereby proving the usefulness of this source in developing vertical optical interconnects. >

LPCVD Ge films are deposited onto bulk Si substrates and subjected to either a rapid thermal anneal (RTA) or furnace anneal (FA) at a temperature that is higher than the melting point of Ge in an attempt to induce epitaxial recrystallization. Spiking into the Si and voids in the Ge film are observed after the anneal. This is attributed to defect-assisted Ge diffusion into the Si substrate caused by strain at the Ge-Si interface. Simple diffusion theory using published diffusivity values predicts diffusion depths similar to the spiking depths observed by scanning electron microscopy and transmission electron microscopy. Approaches to reduce the strain at the interface are explored. It is found that the quasi-equilibrium nature of FA reduces spiking and that there is an area dependence. Grazing-incidence x-ray diffraction analysis suggests that this technique for epitaxial recrystallization does not result in single-crystalline Ge.