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Evans syndrome presents as concurrent autoimmune hemolytic anemia (AIHA) and immune thrombocytopenia (ITP). Systemic lupus erythematosus (SLE) is the most frequent autoimmune disorder associated with Evans syndrome. We herein report a case of new-onset Evans syndrome associated with SLE after BNT162b2 mRNA coronavirus disease 2019 (COVID-19) vaccination in a 53-year-old woman. Blood examination at diagnosis showed hemolytic anemia with a positive Coombs test and thrombocytopenia. Hypocomplementemia and the presence of lupus anticoagulant indicated a strong association with SLE. Prednisolone administration rapidly restored hemoglobin level and platelet count. This case suggests that mRNA COVID-19 vaccination may cause an autoimmune disorder. Physicians should be aware of this adverse reaction by mRNA COVID-19 vaccination and should consider the benefits and risks of vaccination for each recipient.

In our previous study, we argued that stabilization of power source voltage by optimizing a chip wiring feature was essential to achieving high performance transmission for over 40 Gbps I/O on an interface circuit. This region frequency transmission approach is fairly important to solve communication bottleneck. We will examine power supply wiring for more high frequency (over 40 Gbps) which is significant to maintain signal integrity from the viewpoint of an eye diagram and driver device metrics. This focuses a inverter CMOS driver and a differential 40mm-long transmission line using a Synopsys HSPICE simulator with a pseudorandom binary sequence (PRBS32) input signal and simulation models of TSMC 65nm IP's (Intellectual Property), Arizona State University Predictive Technology 32nm and FinFET. In the previous study, simulated results show that configuration of the power source wiring should be carefully considered. A parallel plate structure provides good eye diagrams at 20Gbps in the TSMC 65nm IP's compared to the Loop structure. VDD fluctuation is also fairly low for the parallel plate structure circuit and very high for the Loop Structure circuit. In this study, we focus on other device metrics and higher frequency for 56Gbps region.

To achieve high performance communication it is necessary to consider all the design parameters for the switching circuit, interconnection and power supply. As these parameters definitely affect each other for over 20Gbps. These must be included for their optimization. These parameters are driver on-resistance (drivability), characteristic impedance of all connection routs, dependent frequency load with termination condition, receiver sensitivity and input impedance of power source within 1/4 wave length. Synopsys HSPICE is used for the simulation of the I/O interfaces with actual measurement S-parameter and 65nm process node in the TSMC IP's. In our study, we concluded that the power source line should be low impedance transmission line even 1mm length as similar as 1/4 wavelengths.

Recent communication for cloud computing strongly requires one order magnitude wider bandwidth than current one, such as over 28Gbps in SerDes and Interlaken protocols. So the technology of IO transmitter and receiver becomes to one of key issues. In generally, those high bandwidth IO systems consume relative high power due to relate with fCV^2 by CMOS transistor and parasitic capacitances. Additional problem is that the transmitter needs to drive long wiring of mother board or plug-in board. Some adaptive equalizer and timing adjust circuits must be implemented in the IO circuit that subsequently requires power consumption. Our research has been aimed to save to quarter times power of current ones even in over 28Gbps band width operation. The key was for balanced concurrent design from chip design to board design and open termination circuit system. These will be mentioned here.

Recent communication for cloud computing strongly requires an order of magnitude wider bandwidth than current one, such as over 28Gbps in SerDes and Interiaken protocols. So the IO transmitter and receiver becomes to one of key issues. In generally, those high bandwidth IO systems consume relative high power due to relate with fCJ⁁2 by CMOS transistor and parasitic capacitances. Additional problem is that the transmitter needs to drive long wiring of mother board or plug-in board. Some adaptive equalizer and timing adjust circuits must be implemented in the IO circuit that also requires power consumption. Our research has been aimed to save to quarter times power of current ones even in over 28Gbps band width operation. The key was for balanced concurrent design from chip design to board design and open termination circuit system. These will be mentioned here.

We investigated the transient response characteristic of through silicon via (TSV) in a high-resistivity silicon interposer. For this investigation, signal ground (SG)-TSV-chain pairs in high-resisitivity silicon (>1000 Ω·cm) were prepared. Various pulse waves (swing: -1.8-0 V or 0-+1.8 V, pulse width: 250 ps-100 ms, duty ratio: 1/1) were applied to a SG-TSV-chain pair by using a pulse generator, and output signal was obtained using a sampling oscilloscope. From the rise and fall time of output signal, it was found that the change in transient response characteristic according to the frequency and voltage of the applied pulse wave was very small. This result demonstrates that the change in TSV capacitance with the input signal is very small and that high-resistivity silicon is effective for high speed signal processing.

We have proposed to use the electrostatic capacitance of through-silicon-vias (TSV) in the silicon interposer as the decoupling capacitor. Because the electrostatic capacity of the TSV acts as a decoupling capacitor, it is enabled to decrease the power distribution network (PDN) impedance. Therefore, the dependency to the PDN impedance in the effect of the layout and the shape of the TSV capacitor was analyzed. By introducing the 3-D electromagnetic field simulator, precise PDN impedance analysis was carried out. As a result, TSV functions enough as a decoupling capacitor. PDN impedance of the silicon inter-poser with TSV-decoupling capacitor decrease compared with that of the silicon interposer without TSV. Especially, PDN impedance of the silicon interposer with 200-micrometer pitch TSVs shows PDN impedance without the resonance peak from the low-frequency region to the high frequency area.

Presented in this paper is a feasibility study of a chip stacking technology for very high bandwidth communication. This technology utilizes transmission line coupling between coplanar differential lines constructed in metal layers of two chips placed facing each other such that the differential pairs are overlapped with a spacing of many microns. In previous study we demonstrated communication at 12.5 GHz between two differential pairs of transmission lines fabricated on different metal layers in a single chip [1,2]. As the next step of the study, we developed the second test chip to demonstrate actual communication between two LSI chips using this technology. The test chip includes a high-speed hysteresis-type receiver that extracts the original digital signals from differentiated signals result from the coupling region. In this chip, effect of AC coupling capacitors placed between the driver output and the transmission-line-coupling region in order to reduce power consumption can be also investigated. Evaluation of the second test chip is in progress.