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In this study, we designed a terahertz (THz) detector chip based on field-effect transistors utilizing a standard 55-nm complementary metal–oxide–semiconductor process. The chip includes eight different detector structures to explore the impact of various factors on detector performance. Each detector, characterized by its unique structural design, exhibited varying levels of parasitic capacitance, port impedance matching, and asymmetry, all impacting the detector's responsivity (Rv). Building on the previous nonquasi-static model, this research introduced a comprehensive THz detector model by incorporating plasma wave detection theory, antenna impedance, parasitic effects of the detector, port impedance, and load effects. We also derived the mathematical expression for Rv in the nonresonant mode. The multiple different structures detectors integrated with antenna-on-chip achieved the maximum Rv of 437.6V/W and the minimum noise-equivalent power (NEP) of 119 pW/Hz1/2 at 2.58 THz. We then conducted scanning imaging on a paper envelope containing a screw. The appearance of the screw and the details of creases at various thicknesses on the envelope were clearly visible. Analysis indicated that the detector's Rv and NEP are closely linked to several factors, including the match between the antenna and the detector, the parasitic capacitance at the THz wave coupling site, the maximization of THz wave energy coupled to the detector, the appropriate size of the detector, and the asymmetry between the source and drain.

This article proposes a novel 360° continuously tunable phase shifter employing a synergy of high-pass and low-pass networks. The analysis of the L-type high-pass and low-pass networks elucidates the correlation between phase shift and phase slope, alongside capacitance and frequency. Exploiting the divergent phase slope of high-pass and low-pass networks at different frequencies and circuit parameters, a 180° continuously tunable phase shifter with low in-band phase error is designed by utilizing the eight orders of high-pass and low-pass networks to compensate for each other. Further innovation yields a 360° phase shifter, achieved by integrating a 180° switch-type phase shifter (STPS) reliant on dual $\pi $ -type pathways. The proposed phase shifter is fabricated and measured, confirming the efficacy of the proposed phase shifter, revealing a maximal in-band phase error of merely 4.98° within the 2.3–2.6 GHz. The incorporation of substrate-integrated suspended line (SISL) double-side inductors and capacitors consolidates its advantages, this phase shifter achieving a compact size which is only $0.335\lambda _{{\text {g}}} \times 0.085\lambda _{{\text {g}}}$ .

In this article, a novel tunable phase shifter operating in the ultra-wideband (UWB) is proposed. The transmission phase can be changed by tuning the length of the transmission line. A stretchable line is utilized according to this theory, consisting of eutectic gallium-indium (EGaIn) liquid metal (LM) as the inner conductor and a flexible polydimethylsiloxane (PDMS) tube as the outer shell. The LM line is placed in substrate integrated suspended line (SISL) cavity. To accurately calculate the characteristic impedance of the LM line within the SISL cavity, a coaxial model comprising a circular inner conductor and rectangular outer conductor is employed. A high-pass and low-pass matching circuit is designed using SISL double metal layers on Sub3 to improve matching and out-of-band suppression of the LM phase shifter at UWB. Two types of LM phase shifters were designed and manufactured: the basic LM phase shifter meeting 5.3–7.6 GHz frequency band with a phase shift range from 308° to 450°, and the UWB LM phase shifter operating at 3.1–10.6 GHz with a phase shift range from 164° to 552°, respectively. Additionally, an automatic control system based on microcontroller and stepper motors is implemented for mechanical elongation in achieving precise control over desired phase shifts through mechatronics.

This article presents a fully integrated high-power and high-efficiency $D$ -band power amplifier (PA) with two-way differential power combining in a 28-nm bulk CMOS process. The overall performance improvement is achieved mainly from three aspects. First, the effect of resistance brought by the actual matching network on performance above 100 GHz is considered in transistor selection, and the deoverstabilization technique is proposed to select structures with high output power and high efficiency at stabilization. Meanwhile, the compensating inductors are introduced in the distributed active transformer (DAT) network to reduce RF signal leakage and insertion loss of the power combiner. Finally, considering the low intrinsic transistor gain above 100 GHz in CMOS, the effect of different interstage matching network losses on the overall efficiency is analyzed to guide the optimization objectives of different matching networks, taking into account both gain and chip area. The three-stage four-way power combining PA achieves a peak gain of 19.2 dB, a measured maximum saturated output power of 15.4 dBm, a peak power-added efficiency (PAE) of 14.25%, and a high power density of 381 mW/mm2. To the best of our knowledge, the proposed PA achieves the highest PAE in bulk CMOS-based ${D}$ -band PAs with an output power greater than 15 dBm.

A reconfigurable injection-locked local oscillator (RE-ILO) generator that leverages a multitanks wideband-harmonic-shaping Class-F23 voltage-controlled oscillator (VCO), a RE injection-locked frequency multiplier (RE-ILFM), and a power-efficient injection-locked frequency amplifier (ILFA) for multiple fifth-generation (5G) millimeter-wave (mm-wave) bands is hereby presented. For the VCO, an inductive multiplier inside the positive feedback loop boosts the drain-to-gate voltage gain (Av). Besides, a source-inductive loaded on the output buffer, coupled with a separated inductor, is feedback to the drain of the cross-coupled transistors to expand the impedance peak at the 3rd harmonic for a small fluctuation of 1/ $f^{3}$ phase noise (PN) corner over the entire tuning range (TR). The measured results of the VCO prototype in 55-nm CMOS achieved the VCO measures a TR of 10.65–14.37 GHz, i.e., 29.74%. The FOM $_{T}$ is 192.2 dBc/Hz and the 1/ $f^{3}$ PN corner is 380 ± 100 kHz. Additionally, a RE-ILFM with both frequency $\times 2$ doubler mode (DM) and $\times 3$ tripler mode (TM) is introduced to expand the operation band of the VCO. The ILFA is cascaded for harmonic rejection and power improvement. The proposed RE-ILO generator achieves a frequency TR from 22.25 to 28.61 GHz, i.e., 25% and 35.9–42.04 GHz, i.e., 15.75% with a 1-MHz-offset PN from −102.78 to −104.1 dBc/Hz at DM, −98.48 to −100.67 dBc/Hz at TM, and consumes 66 mW power with an output power of 1.3 dBm.