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• The impact of the gamma irradiation environment in a fusion reactor on the electronic systems was introduced, and experimental verification was conducted through long-term Co-60 gamma irradiation experiments. • Gamma irradiation provides valuable reference for the design of electronic systems in fusion reactors. • Verified the operational condition of some chips under a long-term gamma irradiation environment (2000 Gy). • Provides reference for the verification of radiation resistance of electronic systems in a fusion reactor environment. In the environment of a fusion reactor, electronic systems are subjected to various influences including vibration, electromagnetic pulses, as well as irradiation from neutrons and gamma rays. Diagnostics systems on fusion reactors can accumulate radiation doses to a level where issues such as signal attenuation and system interruption can occur. Additionally, maintenance of electronic systems during fusion reactor experiments is often not feasible. Therefore, assessing the radiation tolerance of electronic systems used in fusion reactors is of paramount importance. To validate the radiation resistance of front-end electronics and cable in various diagnostic systems, a test circuit board was designed. This board integrates a variety of commonly used amplification chips and power supply chips to assess their performance in the environment of a fusion reactor. The experiment selected three different types of cables commonly used in fusion reactors for separate testing, to assess their parameter changes before and after irradiation experiments. Gamma Irradiation Experiments were conducted using a cobalt-60 (Co-60) radiation source at the Irradiation Center of Nanjing University of Aeronautics and Astronautics. The test circuit board was exposed to continuous gamma irradiation at two test points, with dose rates of 6 Gy/min and 1 Gy/min, respectively, for a total of 6.5 h, Data from the irradiation experiments were collected and analyzed. The results show that under continuous gamma irradiation, CJ7805 and AMS1117–5 chips stopped working at 586 Gy and 776 Gy, respectively. The output of the LT1175I5 chip dropped from -5 V to -1 V at 447 Gy. Apart from the radiation-resistant power supply chips, the output of other power supply chips slightly decreased. The signal reference of the charge amplifier dropped at 741 Gy but then slowly rose again, and the signal amplitude decreased at 900 Gy. The signal reference of the current amplification circuit remained unchanged, with a slight decrease in amplitude. The signal reference of the voltage amplifier exhibited jitter, with no change in amplitude. The experiment provides valuable data support for the radiation-resistant design of electronic systems in the environment of a nuclear fusion reactor. [ABSTRACT FROM AUTHOR]

Depleted Monolithic Active Pixel Sensors (DMAPS) constitute a promising low cost alternative for the outer layers of the ATLAS experiment Inner Tracker (ITk). Realizations in modern, high resistivity CMOS technologies enhance their radiation tolerance by achieving substantial depletion of the sensing volume. Two DMAPS prototypes that use the same "column-drain" readout architecture and are based on different sensor implementation concepts named LF-Monopix and TJ-Monopix have been developed for the High Luminosity upgrade of the Large Hadron Collider (HL-LHC). LF-Monopix was fabricated in the LFoundry 150 nm technology and features pixel size of 50 × 250 μ m 2 and large collection electrode opted for high radiation tolerance. Detection efficiency up to 99% has been measured after irradiation to 1 ⋅ 1 0 15 n e q ∕ cm 2. TJ-Monopix is a large scale (1 × 2 cm 2) prototype featuring pixels of 36 × 40 μ m 2 size. It was fabricated in a novel TowerJazz 180 nm modified process that enables full depletion of the sensitive layer, while employing a small collection electrode that is less sensitive to crosstalk. The resulting small sensor capacitance (≤ 3 fF) is exploited by a compact, low power front end optimized to meet the 25 ns timing requirement. Measurement results demonstrate the sensor performance in terms of Equivalent Noise Charge (ENC) ≈ 11 e − , threshold ≈ 300 e − , threshold dispersion ≈ 30 e − and total power consumption lower than 120 mW/cm 2. • Depleted monolithic pixel sensors developed for the ATLAS ITk. • Different implemenation concepts featuring large and small collection electrodes. • Process modification to combine small capacitance with enhanced radiation tolerance. • Full functionality after irradiation. • High efficiency (LF-Monopix), High analog performance (TJ-Monopix). [ABSTRACT FROM AUTHOR]

Abstract SPACIROC (Spatial Photomultiplier Array Counting and Integrating ReadOut Chip) is the front-end ASIC dedicated to readout 64-channel Multi-Anode Photo-Multiplier Tube (MAPMT). In 2017, it was used for the Extreme Universe Space Observatory on a super pressure balloon (EUSO-SPB) instrument which is a pathfinder for space cosmic ray fluorescence detectors. EUSO-SPB was launched by NASA from Wanaka, NZ on the 24th of April 2017. The flight has been a success both on technological and scientific point of views. The instrument was equipped with a set of lenses to focus the UV photons on the Photo Detector Module (PDM) which was controlled by the Data Processing system. The photo detection focal surface is made of 36 MAPMTs with high voltage sub-system (HVPS). The MAPMT signals are transmitted to SPACIROC3 ASIC which performs single photon counting with low power consumption (< 1 mW/ch). This proceeding presents in detail the performances of the SPACIROC3 ASIC. [ABSTRACT FROM AUTHOR]

The ICARUS-T600 Liquid Argon (LAr) Time Projection Chamber (TPC) is presently used as the far detector of the Short Baseline Neutrino (SBN) program at Fermilab (USA) to search for a possible sterile neutrino signal with the Booster Neutrino Beam (BNB). A light detection system, based on 360 Hamamatsu R5912-MOD Photo-Multiplier Tubes (PMTs), has been realized to detect vacuum ultraviolet (VUV) photons produced after the passage of ionizing particles in LAr. High performance electronics allows recording of the PMT signals and provides a fast discrimination for the exploitation of the scintillation light for trigger purposes. This system is fundamental for the TPC operation, contributing to the trigger system and for the 3D reconstruction of events. [ABSTRACT FROM AUTHOR]

The ICARUS-T600 liquid argon (LAr) time projection chamber (TPC) detector is currently deployed as a far detector of the Short Baseline Neutrino (SBN) program at Fermilab (USA) to search for a possible LSND-like sterile neutrino signal at Δ m 2 ≈ 1 eV 2 with the Booster (BNB) and Main Injector (NuMI) Neutrino Beams [1]. A global physical event rate of ≈ 0. 6 Hz , including the genuine neutrino interactions in LAr, beam halos and cosmic interactions inside the proton pulse time windows, is expected, roughly corresponding to ≈ 4 PB of data for the total 6. 6 × 1 0 20 protons on target exposure if the full ICARUS-T600 detector is read-out (≈ 200 MB event size). The designed trigger system described here would collect the genuine neutrino interactions with a ≈ 95 % expected efficiency. [ABSTRACT FROM AUTHOR]

We discuss the performance of a readout system, Fixed Pulse Shape Efficient Readout (FIPSER), to digitize signals from detectors with a fixed pulse shape. In this study we are mainly interested in the readout of fast photon detectors like photomultipliers or Silicon photomultipliers. But the concept can be equally applied to the digitization of other detector signals. FIPSER is based on the flash analog to digital converter (FADC) concept, but has the potential to lower costs and power consumption by using an order of magnitude fewer discrete voltage levels. Performance is bolstered by combining the discretized signal with the knowledge of the underlying pulse shape. Simulated FIPSER data was reconstructed with two independent methods. One using a maximum likelihood method and the other using a modified χ 2 test. Both methods show that utilizing 12 discrete voltage levels with a sampling rate of 4 samples per full width half maximum (FWHM) of the pulse achieves an amplitude resolution that is better than the Poisson limit for photon-counting experiments. The time resolution achieved in this configuration ranges between 0.02 and 0.16 FWHM and depends on the pulse amplitude. In a situation where the waveform is composed of two consecutive pulses the pulses can be separated if they are at least 0.05–0.30 FWHM apart with an amplitude resolution that is better than 20%. [ABSTRACT FROM AUTHOR]

We present the design and the test results of the BCM1F front end ASIC designed for readout of diamond sensors used in the Beam Condition Monitoring system at the Compact Muon Solenoid (CMS) experiment built in the European Organization for Nuclear Research (CERN) in Geneva. The design comprises a fast transimpedance preamplifier with active feedback, a shaper stage and high–performance differential output buffer. The front end amplifier shows good linearity for input charges below 7 fC, signal gain of about 50 mV/fC, equivalent noise charge (ENC) around 400 e− for 2 pF and less than 700 e− for 5 pF input capacitance. The measured peaking time ( \mathrm T\mathrm {p} ) is in the range from 6.6 to 9.4 ns depending on the applied bias conditions and the input capacitance. The full–width–at–half–maximum (FWHM) of the response is kept below 10 ns, which allows for efficient beam halo detection. The return time after the detector signal overdrive is maintained below 25 ns. These two latter parameters make the presented circuit compatible with high data rate applications. [ABSTRACT FROM PUBLISHER]

Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals. [ABSTRACT FROM AUTHOR]

Abstract: The goal of this project is to develop a multi-channel TOF-PET system with a 300ps FWHM time resolution, a factor two improvement with respect to commercially available systems (Surti et al., 2007 [1]). In a TOF-PET system, the time-of-flight information can be used to improve significantly the sensitivity of the detector as shown in Karp et al. (2008) [2]. The target time resolution has been achieved in two channel systems with LYSO (Kim and Wang, 2008 [3]), the aim is to port this results into a multi-channel system. This work extends the results shown in Göttlich et al. (2010) [4], studying the stability of the detector performance in different geometries and configurations. [Copyright &y& Elsevier]

This paper discusses implementation of the Wave Union TDC, a novel scheme of FPGA TDC to improve time measurement precision using multiple measurements, along with several other topics in FPGA delay line based TDCs. FPGA specific issues such as considerations on the delay line choice in different FPGA families and encoding logic are first examined. Next, common problems for both FPGA TDCs and ASIC TDCs such as schemes of coarse time counter implementation, bin-by-bin calibration and noise issues due to single ended signals are discussed. Several resource/power saving design approaches for various processing stages are described in the document. [ABSTRACT FROM AUTHOR]

Abstract: We present a pulse generator able to generate pulses statistically similar to the ones produced by RPC cells. The device generates up to four arrays of fast and narrow random-like pulses. Polarity, maximum amplitudes, widths and pulse rate in each channel may be modified independently in order to simulate different RPC setups and environments. This portable and cost-effective pulse generator is a versatile instrument for testing FE-Electronics and different real detector features related with the signal propagation inside the detector. It has been developed in the framework of the ESTRELA 1 [1] ESTRELA (Electrically Shielded Timing RPC Ensemble for Low Angles) is part of the upgrade of the HADES experiment at GSI with the aim of constructing an RPC-based time-of-flight wall that will cover around 8m2 in order to cope with the high particle multiplicities expected for heavy nuclei collision systems such as Au+Au. project of the HADES experiment at GSI. [Copyright &y& Elsevier]

A new pixel Front-End Integrated Circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described. [ABSTRACT FROM AUTHOR]

Recently, a novel charge readout method has been developed based on 1-bit sigma delta modulation, which is able to directly achieve a Charge-to-Digital Conversion (QDC). This kind of design mainly comprises an amplifier and an FPGA instead of the conventional Front End Electronics (FEE) for radiation detectors. The amplifier is responsible for charge integration, and the FPGA is used for linear discharging. All of post-processing algorithms are implemented in the FPGA. Targeting this kind of readout method, some improvements are made to extend its application for new radiation detectors. In first improved version, a feedback resistor for baseline stabilization and a trigger threshold for removing noise signal are introduced. The feedback resistor leads to a slow exponential discharging when a charge signal is integrated on the feedback capacitor. To choose optimized parameters, an analysis of the exponential discharging effect on the linear discharging is made. In second version, an artful improvement is proposed to discard the exponential discharging. To evaluate the improved readout method, a 32-channel readout electronics prototype is developed. The performances and analysis of the circuit, such as channel linearity, dead time, are also presented. A SiPM based detector module is applied to verify this electronics prototype. The experimental results show that this new kind of charge readout is efficient and promising for other radiation detectors. [ABSTRACT FROM AUTHOR]

We present a mixed-signal CMOS front-end cell designed for semiconductor pixel detectors for X-γ ray imaging and spectroscopy. The Readout Pixel Cell (RPC) comprises an analog and a digital section to accomplish all the functionality of a spectroscopic-grade signal readout. The analog section includes a low noise charge preamplifier, a two stage shaper amplifier with digitally selectable shaping times from 1 μs to 10 μs, a baseline restorer, a high precision peak stretcher and an output amplifier. The digital section includes an amplitude discriminator with coarse and fine digital control of the threshold level, a peak discriminator, a current-mode trigger generator, a logic circuit to accomplish the pulse pile-up rejection and the RPC reset after the A/D conversion, the disable functions of the preamplifier and of the discriminators. The RPC has been designed and manufactured in 0.35 μm CMOS technology with a size of 300 μm × 300 μm. The full functionality of the RPC has been successfully tested. At room temperature, the intrinsic equivalent noise charge is 15.7 electrons r.m.s. at 3.3 jis and the minimum noise slope is 22 electrons/pF at 8 μs, the linearity error is between -1.4% and + 1.2% within 1.9 fC input signal dynamic. The RPC has separate voltage supplies (+3.3 V) and grounds for the analog and digital sections and the total power consumption is 495 μW. [ABSTRACT FROM AUTHOR]

The Near Detector for the MINOS Experiment at Fermilab is composed of alternating planes of scintillator strips and steel plates, and is read out with 64-channel, multi-anode photomultiplier tubes. The instrumentation uses a custom integrated circuit designed at Fermilab for the front end analog processing, called the QIE. The system can measure single photoelectrons to high precision with a dynamic range of 16 bits. The electronics operates in two modes. It records all events that occur during the 10 μs "fast spill" of the beam from the Fermilab Main Injector at a rate of 53 MHz, using a gate from the beamline controls to force data acquisition. The system can also acquire data from cosmic rays that pass through the detector for calibration. In this case, dynode signals from the photomultipliers are used as the trigger, causing digitization and readout of the associated channels. Zero suppression and normalization are done in the front end electronics. The system is "triggerless" in that there is no global hardware trigger. Instead, each event is tagged with a "timestamp", which is used in postprocessing to reconstruct events and discard noise hits. The system of 10,000 channels is now built and installed, and operational at Fermilab. The components of the system are described and preliminary system performance is reported. [ABSTRACT FROM AUTHOR]

We present a compact and low power integrated circuit designed to control the reset and perform pulse pile-up rejection in multi-channel spectroscopic-grade ASICs. The circuit has been implemented in a 0.35 µm CMOS technology using an area of 60 × 80 µm² and null static power consumption. These features make this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X- and gamma-ray pixel detectors. [ABSTRACT FROM AUTHOR]

Abstract: We report on the design and testing of novel mixed analog and digital front end ASICs custom made for the single photon detectors considered for the BTeV RICH system. The key features are reviewed, as well as results achieved using electronics bench tests and beam studies. [Copyright &y& Elsevier]

An amplifier has been designed for optimal use of position-sensitive thermal neutron detectors based upon the principle of resistive charge division. The important points in this optimization are: high counting rates and good spatial resolution (low noise). In this paper, we present a short theoretical analysis of the problem that led us to our design. We make an analysis of unwanted, secondary effects caused by extra resistance, the blocking capacitor and the finite input impedance of the amplifier which often occur in a practical measurement setup of this kind. [Copyright &y& Elsevier]

Abstract: The BGO-OD experiment is intended for the systematic investigation of the photo-production of mesons off the nucleon. The experiment will use bremsstrahlung photons from an e− beam incident upon a thin radiator. The photon energy will be measured via the deflection of the electrons in the magnetic field of a photon tagger. The B-FrED is a 16 channel double-threshold discriminator and shaper board designed as Front-End Electronics for the new Tagger detector of the experiment. It is a 6U-VME form factor card. The analog input stage has 1.7GHz bandwidth. The output stage provides two LVDS signals with an expected jitter of with respect to the input signal. The threshold settings are managed by a micro-controller which is remotely accessible through Ethernet. [Copyright &y& Elsevier]