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This study presents a new spur reducing architecture of phase‐locked loop‐based frequency synthesiser. In the proposed architecture, an array of switched capacitors and a delay locked loop are used to evenly transfer the charge, coming from its charge pump, to its loop filter at a fixed number of equi‐spaced time intervals. It reduces fundamental as well as higher‐order harmonics of the reference spur. The proposed architecture has been designed and fabricated using 180 nm complementary metal oxide semiconductor technology. Measured result shows about 17.64 dB reduction of the fundamental spur compared with that of the conventional architecture. [ABSTRACT FROM AUTHOR]

This paper proposes an area and power efficient frequency divider used infrequency synthesisers, which operates in 2.4 GHz IEEE 802.15.4/ZigBee frequency band. The proposed frequency divider consists of a multi-modulus pre-scaler and integrated P&S counter. In order to reduce the power consumption and area, swallow counter has been replaced by a simple digital circuit. Simulation results show 30% of area and power is reduced when compared to the previous design. All of the circuits can be designed in 0.18 µm complementary metal oxide semiconductor technology with a single 1.8 V DC voltage supply. [ABSTRACT FROM AUTHOR]

A fast adaptive frequency calibration (AFC) technique with self-calibration for fast-locking phase-locked loops is presented with frequency-selecting switches. The proposed AFC directly calculates the proper switch states of the voltage-controlled oscillator (VCO). It requires only six clock cycles of the reference oscillator regardless of the number of VCO switches to reach the final switch state in the ideal case. The proposed method counts the number of VCO cycles per reference clock period for the minimum VCO frequency (MIN) and the maximum VCO frequency (MAX) during the first four-clock periods. For the following two-clock periods, the proper states of the VCO switches are set to the calculated value fromMIN,MAXand the desired division ratio for a target frequency (EST). A frequency synthesiser with the proposed AFC was implemented on a 0.18 µm CMOS process. The AFC time decreased from 40 to 0.4 µs employing the proposed scheme such that the total lock time is 40 µs with the loop bandwidth of 40 kHz. [ABSTRACT FROM PUBLISHER]

An Σ-Δ fractional-N frequency synthesiser with small Kvco-variation wideband LC voltage controlled oscillator (LC-VCO) and current-matching charge pump (CP) for Mobile Digital television Systems is presented. To achieve small VCO-gain (Kvco) variation, a parallel switched varactor array is proposed to the conventional wideband LC-VCO with switched capacitor array, the value of the switched varactor is pre-set and both arrays are controlled by the same switching code. Perfect current matching and good stability are obtained by the improved CP with an added bias branch circuit for low reference spur. The chip was fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 0.25 µm complementary metal-oxide-semiconductor process and draws 12 mA from a 2.5 V supply voltage. The synthesiser covers a wide tuning range from 0.82 to 1.85 GHz with two integrated LC-VCOs, and each VCO achieves a Kvco variation of less than 16% with a tuning range of more than 46%. The current mismatch of CP is as low as 1.2%. The measured close-in and out-of-band phase noise are -83.5 dBc/Hz@10 kHz and -127 dBc/Hz@1 MHz, respectively, the reference spur is -76.3 dBc. [ABSTRACT FROM AUTHOR]

We propose and demonstrate an 11-bit time-to-digital converter (TDC) for all-digital phase-locked loops (ADPLLs) in digital television. The proposed TDC converts the width of the input pulse into digital output with the tap space of the outputs of a free-running ring oscillator (FRO) being the conversion resolution. The FRO is in a structure of coiled cell array and the TDC core is symmetrical in the input structure. This leads to equally spaced taps in the reference clocks and thereby a high TDC conversion linearity. The TDC is fabricated in 0.13 μm CMOS process and the chip area is 0.025 mm2. The measurement results show that the TDC has a conversion resolution of 39 ps at 1.2 V power supply and a 4.5 ns dead time in the 11-bits output case. Both the differential non-linearity (DNL) and integral non-linearity (INL) are below 0.5 LSB. The power consumption of the whole circuit is 4.2 mW. [ABSTRACT FROM AUTHOR]

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma-delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is -116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma-delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43-1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is -110 dBc/Hz@1.0 MHz. [ABSTRACT FROM AUTHOR]

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is - 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply. [ABSTRACT FROM AUTHOR]

This work presents a low power direct digital frequency synthesiser (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide lookup table ROM into two parts. The ROM size of the proposed architecture is 25% less than that of conventional lookup table DDFS. The hardware of new DDFS architecture compared to the traditional two-level table DDFS also requires less one multiplication. A synthesised 0.35 µm DDFS with an spurious free dynamic range of -80 dB, runs up to 100 MHz and consumes 81 mW at 3.3 v. The power efficiency is 0.81 mW MHz-1, which represents an enhancement of more than 38% compared to the conventional DDFS. [ABSTRACT FROM AUTHOR]

In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TDC), digitally controlled oscillator (DCO) and digital filter suitable for all-digital frequency synthesiser for IoT and IoV applications are defined. The structure of frequency synthesisers, which allows us to meet defined requirements, is presented. Its main parts are 2D Vernier TDC based on gated ring oscillators, which can achieve resolution close to 1 ps; multi core LC-tank DCO, whose tuning range is 4.3–5.4 GHz when two cores are used and phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier; digital filter made of proportional and integral gain stages and additional infinite impulse response filter stages. Such a structure allows us to achieve a synthesiser's in-band phase noise lower than −100 dBc/Hz, out-of-band phase noise equal to −134.0 dBc/Hz and allows us to set a synthesiser to type-I or type-II and change its order from first to sixth. [ABSTRACT FROM AUTHOR]