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A four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW. [ABSTRACT FROM AUTHOR]

Summary: A setting‐zero analysis method is presented to facilitate the prediction of zeros in multistage amplifiers. The main objective of this method is to simplify the analysis process of such amplifiers while improving the overall performance, and the feasibility is confirmed by various examples presented in this paper. By proposing a single‐capacitor cascode Miller compensation three‐stage amplifier using setting‐zero analysis, this paper has theoretically verified that the addition of a grounding second‐stage compensation capacitor is unnecessary. Measurement results show that this amplifier consumes a current of 38 μA at a 1.2 V supply voltage, with a 103 dB open‐loop gain. When driving a 1 nF load capacitor, this design achieves 1.88 MHz gain bandwidth and 73° phase margin, with a 3.33 V/μs average slew rate and an average 1% settling time of 0.40 μs under the unity‐gain configuration. [ABSTRACT FROM AUTHOR]

Abstract A four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW.

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance. [ABSTRACT FROM AUTHOR]

This paper presents Hybrid Cascode Compensation with Hybrid Q–Factor Control (HCCHQ), for three-stage feedback operational transconductance amplifiers (OTA) capable of handling any load capacitor ( $C_{L}$ ). The design incorporates an enhanced Miller compensation strategy, exploiting cascode-Miller compensation with hybrid pathways to effectively separate the dominant pole from non-dominant poles for bandwidth expansion. It also combines a hybrid quality factor (Q–factor) control with a local impedance attenuation (LIA) module, adjusting the Q–factor of non-dominant poles by mitigating the ringing in the time response and the frequency peaking for lighter $C_{L}$ s. The new design can accommodate unlimited capacitive loads, owing to the Miller– and load-compensated solutions for the light and heavy $C_{L}$ s, respectively. Fabricated in a 180-nm standard CMOS process, a prototype of the proposed amplifier demonstrates a quiescent current of $25~\mu $ A under a 1.8 V single supply. It boasts a compact 0.0055 mm2 area and exhibits unconditional stability when configured as a voltage buffer driving any $C_{L}$ . With a mean DC gain of 115 dB, the average unit-gain frequency (UGF) is 2.30 MHz and 0.11 MHz for 0.1 and 47 nF external capacitive loads, respectively. The mean 1% settling time is measured as $2.41~\mu $ s and $40~\mu $ s for the same capacitive loads, respectively, when a 0.4 V pulse signal is applied to the input.

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth. [ABSTRACT FROM AUTHOR]

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89 dgree, and a power dissipation of 590 μW.

This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained. Poles and zeros formulations are extracted while circuit-level implementation is suggested and simulated using 0.18 μm CMOS technology. The compensation network shares the Miller capacitor at two negative loops simultaneously leading to improving frequency response. According to the simulation results, theoretical linear calculations are in acceptable agreement. The proposed amplifier shows 115 dB, 151 MHz, and 55 as DC gain, GBW, and PM respectively while consuming 320 μW as power dissipation.

Multistage amplifiers have become appropriate choices for high‐speed electronics and data conversion. Because of the large number of high‐impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500‐pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five‐stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW. [ABSTRACT FROM AUTHOR]

Abstract： Based on dual active feedback with miller capacitor compensation (DAFMCC), a novel single pole system of capacitor-less on-chip low-dropout (LDO) voltage regulator circuit is presented. The LDO adopts a fully differential amplifier as the first gain stage, two parallel feedforward pathways can improve the transient response performance of the circuit meanwhile insert a push-pull stage at the gate of the power MOSFET which results in a symmetrical slewing behavior. The proposed LDO regulator is verified by TSMC 0.18 µm BCD process. The simulation results show that when supply voltage changes from 2 V to 4 V, the minimum dropout voltage is 200 mV, the maximum load current is 120 mA. The transient response recovery time is smaller than 0.7 µs, the phase margin is larger than 60°.

Advancements in integrated circuits technology, force designers to adopt methods and approaches with posed limitations. Nowadays, multistage amplifiers are widely in demand due to high‐gain performance while avoiding placing transistors vertically in contrast with cascode structures. In this work, a four‐stage amplifier is investigated and frequency is compensated via a compensation network that includes two Miller capacitors at the outputs of differential blocks. So, using two Miller capacitors and sharing these capacitors common in four Miller loops, provide an opportunity to achieve acceptable frequency response regarding gain‐bandwidth product and phase margin. The proposed amplifier is modeled symbolically and simulated with the HSPICE circuit simulator with the help of 0.18 μm CMOS technology. According to the simulation results, the proposed approaches show superior performance compared with previously existing methods. Additionally, the sensitivity of the proposed amplifier against load and compensation capacitors expresses a stable and relatively fixed frequency response. Such a high gain amplifier with more than 180 dB as DC gain and 88° phase margin, is in great demand for realizing modulators and data converters. [ABSTRACT FROM AUTHOR]

Nowadays cascode structures or vertical arrangements of MOSFETs can not satisfy demands regarding high gain amplifiers. As a direct result, the only promising choice turns to Multi‐stage amplifiers via cascading gain stages. The challenge here is stability issues which shows itself by different frequency compensation. All problem starts with increasing number of nodes and consequent poles. The poles degenerate phase of system and need to be controlled. In this work, a five‐stage amplifier is targeted for a new and efficient frequency compensation technique. The major contribution of proposed approach is using only two Miller capacitors with considerable small values (10 pF) compared to load capacitor (500 pF). This achieved via exploiting two differential active stages which intensify Miller effect and provide capability to share Miller capacitor at multiple loops simultaneously. The proposed amplifier with corresponding frequency compensation is described symbolically while a circuit level implementation is performed via HSPICE circuit simulator and TSMC 0.18 μm CMOS technology. Based on simulation results, the proposed amplifier expresses a DC gain of 195 dB, a gain bandwidth product of 15.2 MHz, a phase margin of 90°, and a power dissipation of 570 μW. [ABSTRACT FROM AUTHOR]

Short channel MOSFET exhibits the characteristics of wide bandwidth and low DC gain. A low DC gain causes a high gain error and a narrow output linear range in the closed loop. The DC gains can be improved by using the cascade structure, but frequency compensation is required due to the increase in the number of poles. The output nodes of each stage in a cascade Common-Source amplifier have a cascade of zero, and this zero is cancelled out by the input node of the next stage. This paper proposes a three-stage operational amplifier (op-amp) with frequency compensation using cascade zero. This op-amp was implemented in the 180 nm CMOS technology and achieved 86.96 MHz unity–gain frequency, 51.7° phase margin at 32 pF load capacitor and 99.83 dB DC gain, that is, a 36.21 dB improvement over a two-stage op-amp with the same power consumption. The op-amp consumed 7.74 mW with a supply voltage of 1.8 V. [ABSTRACT FROM AUTHOR]

The rapid advancements of CMOS integrated circuits technologies lead designers to cascade structures and avoiding cascode amplifiers. As a result, frequency compensation becomes the most important issue since multi-stage amplifiers are highly potential to instability. Here in this work, two differential stages are exploited to form frequency compensation network. These stages realize four Miller loops and share each Miller capacitor in two loops simultaneously. This intensifies Miller effect to improve frequency response due to pole-zero cancellation. The proposed three stage amplifier is modeled symbolically via a transfer function (TF) while 0.18um CMOS technology is used for circuit simulation. Good agreement between theoretical calculation and simulation results shows validity and accuracy of the TF. Also ample simulations are performed to exhibit the proposed amplifier performance against parameters mismatches. The proposed three stage amplifier expresses 105 dB as DC-gain, 4.8 MHz as Gain Band Width and 72 degree as Phase Margin. The amplifier consumes 360 uW as power consumption. This performance obviously is an improvement of Nested Miller Compensation (NMC) while Figure of Merits (FoMs) are enhunced. [ABSTRACT FROM AUTHOR]

This paper presents a novel frequency compensation scheme for the stability of low dropout regulator (LDO). The proposed compensation scheme introduces a zero in the voltage regulation loop to enlarge gain and phase margin at high‐frequencies. As a result, high open‐loop‐gain and improved load regulation performances are achieved, and a particular resistor is introduced in the compensation structure to cancel the voltage drop originating from cable resistances at the output to further improve the load regulation performance. The proposed LDO with wide input/output range and high‐power supply rejection is designed and implemented in a 180 nm CMOS process. The LDO operates with an input voltage range of 4–16 V, an output voltage range of 1.5–5 V and an output current range of 0–1000 mA. High open loop gain and high bandwidth are achieved, and the simulated performances of load regulation and line regulation are less than 32 μV/mA and less than 3 mV/V over the whole operation range, respectively. The on‐chip compensation capacitor required by the compensation module is only 1.8 pF. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth.

Resistive voltage dividers tend to have a highly non-linear transfer function as parasitic and stray capacitances exert an increasing influence with increasing frequency. The non-linear transfer function depends on the topology and resistors used and consists of a low-pass filter with an additional high-pass component in the GHz range. Due to the non-linear transfer function the measured signal differs from the original input signal. Here, we present an improved resistive voltage divider with additional compensation capacities to extend the linear bandwidth. With this new concept, the linear bandwidth is improved from 115 kHz to 88 MHz, while maintaining a DC input impedance of 10 MΩ. For high-voltage insulation and easy manufacturing, surface mounted resistors on a printed circuit board with a compensation electrode on the adjacent side are used. The performance of this resistive voltage divider is demonstrated by measuring a series of high-voltage pulses with an amplitude of 2.5 kVpeak-peak. The measured pulse rise time is about 16 ns, corresponding to an average slew-rate of 150 V/ns. Finally, the developed resistive voltage divider is successfully used to measure fast high-voltage transients required for advanced ion mobility spectrometers with integrated collision induced fragmentation. [ABSTRACT FROM AUTHOR]

Piezoelectric actuator (PEA) has been widely used in micro-systems, due to the advantages of nano-scale precision, rapid response speed, high stiffness, etc. Nevertheless, the intrinsic nonlinearities of PEA, particularly hysteresis, severely deteriorate its positioning and tracking control accuracy. In most existing control algorithms of PEA, the approximate inverse model of hysteresis is developed to compensate for motion error, which requires high modeling accuracy. To avoid the influence of complex modeling procedures and modeling errors on tracking precision, a trajectory compensation-based adaptive control method has been proposed in this paper. Firstly, a simple linear controller is used to establish the closed-loop feedback system and to guarantee the basic tracking performance of the PEA system. And then, the trajectory compensation is designed according to the frequency analysis of the closed-loop control system. Finally, nonlinear adaptive compensation is used to eliminate the residual errors of the above linear frequency domain model. Different from conventional controllers, the proposed method can achieve excellent tracking control performance without any hysteresis model of PEA. The stability and convergence of the proposed method have been theoretically proved. In addition to theoretical guarantees, the proposed method is validated experimentally and demonstrated to achieve the root-mean-square and maximum value of tracking errors to less than 8 nm and 25 nm, respectively, which has a clear accuracy advantage over other methods. [Display omitted] • This method is hysteresis-model-free and achieves solid motion control accuracy. • This method has a strong generalization capability for different control scenarios. • The results demonstrate a superior performance to classic ILC control method. [ABSTRACT FROM AUTHOR]

In this paper, a simple while effective methodology to calculate the symbolic transfer function of a multistage amplifier with frequency compensation is proposed. Three general amplifier models are introduced and analyzed, which represent basic topologies found in the literature. For these amplifier models, the symbolic transfer function is derived and specific strategies for the zero and non-dominant pole expressions are presented. The methodology is suited for hand calculations and yields accurate results while offering more intuition into the operation of the widely adopted frequency compensation solutions discussed in the literature. The effectiveness of the proposed approach is validated through various typical cases of study.

This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution. High-speed feedback pathways relying on Miller capacitors and current buffers are implemented within the amplifier scheme to push the non-dominant poles to high frequencies for small to medium load capacitors. A small resistor is also shared between the two pathways to improve the stability regardless of the load capacitor. A serial $R$ - $C$ branch is then added to extend the lower limit of load drive capability to small load capacitors. Gain margin is, for the first time in literature, analytically evaluated and included in the design phase. A prototype of the proposed amplifier is fabricated in 65-nm CMOS process with active area of 0.0017 mm2 and 1.15 pF total compensation capacitance. It can drive the load capacitor range from 200 pF to 100 nF, while drawing a quiescent current of $7.4~ \mu \text{A}$ from a 1.2-V input voltage supply. A unity-gain frequency of 1.67 MHz was measured with an average slew-rate of 1.31 V/ $\mu \text{s}$ , when the proposed amplifier is wired in unity-gain configuration to drive a 500-pF load capacitor.

In this paper, we present on-chip frequency compensation with a capacitor multiplier for a current-mode control DC-DC converter. The capacitor multiplier technique can effectively remove the crossover frequency from the origin. An equivalent capacitance is obtained by amplifying the small current in the capacitor. The value of the equivalent capacitor can be adjusted. The functional block diagram and small-signal transfer function of a buck DC-DC converter are derived for a simplified system loop for on-chip frequency compensation with a capacitor multiplier. In this paper, the derived system transfer function for frequency compensation is verified by simulation and from test results. The proposed circuit is suitable for low-cost and small-size applications. Simulation results and experimental results are presented to demonstrate the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18 μ m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper. [ABSTRACT FROM AUTHOR]

This brief provides a detailed loop gain and stability analysis of hybrid power amplifier supply modulators. Design considerations, including the relations between the voltage and current loops, the rationale of current loop compensation to ensure stability and improve bandwidth, and the impacts of current loop on the overall system stability and efficiency, are studied with combined system loop gain modeled mathematically. The theoretical analysis is proven by simulation results. Based on the study, a hybrid supply modulator has been designed and fabricated in 65-nm CMOS. In measurements, stable voltage and current closed-loop operations have been verified, with a peak efficiency of 85% when tracking a 20-MHz LTE envelope. [ABSTRACT FROM AUTHOR]

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage foldedcascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metaloxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from -0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/vHz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V/us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from -0.44 to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (FoMs) are the highest when compared to other reported FCOTAs in the literature. [ABSTRACT FROM AUTHOR]

This paper presents a systematic analytical comparison of the single‐Miller capacitor frequency compensation techniques suitable for three‐stage complementary metal–oxide–semiconductor (CMOS) operational transconductance amplifiers (OTAs). The comparison is carried out with the aid of a figure of merit that expresses a trade‐off among gain‐bandwidth product, load capacitance, and total transconductance, for equal values of the phase margin. The results found can be used before the transistor‐level design step and provide useful guidelines for the optimization of the small‐signal performance. Simulations by using a 65‐nm standard CMOS technology confirming the effectiveness of the theoretical comparison for 10 different OTA topologies are also provided. [ABSTRACT FROM AUTHOR]

Due to distribution shift, deep learning based methods for image dehazing suffer from performance degradation when applied to real-world hazy images. In this paper, this study considers a dehazing framework based on conditional diffusion models for improved generalization to real haze. First, our work finds that optimizing the training objective of diffusion models, i.e., Gaussian noise vectors, is non-trivial. The spectral bias of deep networks hinders the higher frequency modes in Gaussian vectors from being learned and hence impairs the reconstruction of image details. To tackle this issue, this study designs a network unit, named Frequency Compensation block (FCB), with a bank of filters that jointly emphasize the mid-to-high frequencies of an input signal. Our work demonstrates that diffusion models with FCB achieve significant gains in both perceptual and distortion metrics. Second, to further boost the generalization performance, this study proposed a novel data synthesis pipeline, HazeAug , to augment haze in terms of degree and diversity. Within the framework, a solid baseline for blind dehazing is set up where models are trained on synthetic hazy-clean pairs, and directly generalize to real data. Extensive evaluations on real dehazing datasets demonstrate the superior performance of the proposed dehazing diffusion model in distortion metrics. Compared to recent methods pre-trained on large-scale, high-quality image datasets, our model achieves a significant PSNR improvement of over 1 dB on challenging databases such as Dense-Haze and Nh-Haze. [ABSTRACT FROM AUTHOR]

This work presents an effective and straightforward frequency compensation scheme in CMOS three-stage amplifiers. Using a differential block in the compensation network, the proposed circuit shows independent and large first dominant pole regarding the DC gain path. The presented three-stage architecture is frequency-compensated just by a single Miller capacitor. Mathematical analysis is presented along with ample simulations that are performed using TSMC 0.18- μ m CMOS technology. According to the results, the proposed circuit shows DC gain equal to 118 dB, GBW equal to 466 MHz, PM equal to 74.3∘ and 1.2 mW as power consumption, respectively. The high values of DC gain and GBW make the proposed amplifier appropriate for more speedy operations such as high-speed modulators and data converters. [ABSTRACT FROM AUTHOR]

Multi‐stage operational amplifiers are considered as basic building blocks in modern electronics since advanced Complementary metal–oxide–semiconductor (CMOS) technology limits exploiting cascode structures due to suffering from low voltage swings and the need of high gain capability. In this regard, an improved and high‐performance three‐stage CMOS amplifier is proposed in this work. The presented structure modeled mathematically and simulated via HSPICE circuit simulator with the 0.18‐μm CMOS technology. An straightforward symbolic calculation is explained to obtain linear transfer function. According to the simulation results, the proposed circuit show 149 dB as DC gain while express 7.3 MHz and 380 μW as gain‐bandwidth product and power dissipation, respectively. Such a high‐performance amplifier has great potential to realize more complex analog and mixed mode signal systems such as modulators and data convertors. [ABSTRACT FROM AUTHOR]

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Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A high current efficiency two-stage amplifier with inner feedforward path compensation (IFPC) technique is proposed in this paper. To improve the current utilization of the whole structure, the recycling folded cascode amplifier (RFC) is adopted as the first stage, and the inner feedforward path which is used to eliminate the non-dominant pole is composed of the input stage of RFC and the tail current transistor of the second stage amplifier. By using the IFPC technique, the proposed amplifier achieves an extended gain-bandwidth (GBW) and sufficient phase margin (PM) compared to that of the two-stage amplifier using single Miller compensation (SMC). Moreover, this compensation technique avoids extra power consumption since it does not require additional circuits. The proposed two-stage IFPC amplifier was fabricated in a 0.18 μm CMOS technology and the chip area of it is about 0.076mm2. The simulated open loop AC response shows the DC gain, GBW, and PM are 130dB, 2.01MHz, and 58.3°, respectively. Measured results of transient response show when driving a 120pF load capacitance, the proposed amplifier achieves 368ns average 1% settling time, and about 1.56V/μs average slew rate (SR). Note that under the condition of 1.8V power supply, the power consumption is only 108μW, proving the proposed two-stage IFPC amplifier can achieve high current efficiency while maintaining stability.

This work presents a compact switched-capacitor power detector (PD) with frequency compensation technique in a 65-nm CMOS process. Utilizing self-biased MOSFET as switches, the PD works both at the positive and the negative cycle to increase the dynamic range (DR). The output of traditional power detectors usually change with the variations of input frequencies which make the measurement of PD more difficult. In this design, by adding a feed-forward frequency detection circuit, the load resistors of the power detector are changed according to the input frequencies. Thus, the effect of input frequency variation is minimized. The measured operation frequency of the power detector is from 3 GHz to 5 GHz with a dynamic range of 20 dB with an error of ±2 dB. The variations of the output voltage are reduced from more than 4 dB to ±0.5 dB, achieving a variation of less than ±0.25 dB/GHz. To the authors' knowledge, it is the first power detector with input frequency compensation. The core of the power detector occupies an area of 0.014mm2 and consumes 2.04mW static power.

This work presents two new CMOS designs of current mode squarer circuits using a 1.5 V supply. The four-quadrant multiplier has also been designed using proposed squarer circuits. To improve bandwidth, the resistive compensation scheme has been exploited. The input and output signals of proposed circuits are of current type and hence exhibit larger dynamic range contrary to voltage mode circuits. Various simulations have been carried out to check performance and validate theoretical analysis. It is observed that range of − 3 dB bandwidth, power consumption and linearity error of the proposed circuits I and II are 542.53 MHz and 1.13 GHz, 0.56 and 0.47 mW and 1.8 and 2%, respectively. In the state of the art, it is noticed that around 10–90% bandwidth is increased while using proposed circuits over most of the conventional circuits. All results are verified using spice tools and 0.18 µm CMOS technology parameters. [ABSTRACT FROM AUTHOR]

In this paper, a three-stage rail-to-rail class-AB amplifier for GaAs/GaN PA driver in radar transmitter components is achieved using a proposed frequency compensation scheme in 0.35 μm CMOS technology. Meanwhile, a negative voltage reference is proposed with low un-trimmed spread by employing level shift technique. The PA driver capable of handling load capacitance ranging from no load to 1uF only consumes 2 mA of quiescent current while delivering a peak current of 100 mA to the load with −90 dB THD. The core area occupies 2.4mm2. [ABSTRACT FROM AUTHOR]

In this article, we propose a bandgap reference (BGR) with a single bipolar junction transistor (BJT) branch and a proportional-to-absolute-temperature (PTAT)-embedded amplifier. Having fewer BJT and passive components, the proposed BGR uses less power and area compared to the conventional BGR that uses multiple BJTs and resistors. As the proposed BGR achieves temperature compensation by employing a feedback loop that has two gain stages, frequency compensation is required. We propose frequency compensation scheme where a compensation capacitor is connected between the BGR output and a current mirror node in the PTAT-embedded amplifier. By using this scheme, location of a mirror pole associated with the current mirror node can be optimized to achieve both improved stability and low power consumption. Fabricated in 0.18- $\mu \text{m}$ CMOS, the proposed BGR achieves temperature coefficient of 26.3 ppm/°C over −40 °C–140 °C; voltage accuracy ($\sigma /\mu $) of 0.33%; and power supply rejection (PSR) of −52 dB, −44 dB at 100 Hz, 1 MHz respectively; while occupying 0.0082 mm2 and consuming 192 nW without startup circuit and trimming. [ABSTRACT FROM AUTHOR]

Recently, the current transducer based on an array of magnetic field sensors has attracted a lot of attention. For busbars of circular cross section, many studies have been conducted and many results have been obtained. However, for the rectangular cross section busbar, the skin effect causes the frequency response curve of the magnetic flux density $B$ generated by the current-carrying conductor to appear nonlinear, which brings challenges to the wideband current measurement of the rectangular busbar. This article presents a wideband current transducer based on the array of magnetic field sensors for the current measurement of the rectangular busbar. First, according to the rectangular busbar, select reasonable magnetic field detection points to arrange the sensor array. Then, the frequency response curve of the magnetic flux density $B$ at each detection point around the rectangular busbar is obtained by simulation. After that, all frequency response curves are averaged, and the proper digital filter is designed according to the averaged frequency response curve to perform frequency compensation. The compensated frequency response curve is basically flat, so the wideband current measurement of the rectangular busbar can be realized. The bandwidth and overall performance of the designed wideband current transducer are verified through experiments, and experimental results show that the designed transducer can meet the requirements of relevant standards for the class 0.5 current transducer. [ABSTRACT FROM AUTHOR]

This paper presents a simple simplification method to design a multistage amplifier. The simplification procedure is based on a defined criterion which mainly related to ignoring negligible terms. In order to verify the validity and accuracy of the exploited method, a complex four‐stage CMOS amplifier is considered. Simplified transfer function and circuit simulator output are compared. According to simulation results obtained from HSPICE circuit simulator and TSMC 0.18 μm CMOS technology, the proposed approach expresses a bitter performance by 1% error. The aim is to propose a preprocessing algorithm. This helps main algorithm to deal with simpler inputs. In this way, a preprocessing algorithm is investigated which reduces CPU time and needed memory to simplify heavy symbolical transfer functions. Since target is analog and mix mode circuit, some circuit‐based assumptions are considered. [ABSTRACT FROM AUTHOR]

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets. • This paper makes a systematic study of using the gm/ID method for initial sizing of the class of multi-stage Op Amps with Miller compensations. • We propose methods to derive constraints from design equations to make the gm/ID-based sizing more accurate and less simulation hungry. • We further propose heuristic sizing rules that are suited for application to multi-stage Op Amps for quickly working out acceptable sizing. • We have validated the effectiveness of the initial sizing method by Op Amp examples containing different number of stages. • The proposed initial sizing method can be potentially integrated in an auto-sizing tool. [ABSTRACT FROM AUTHOR]

The importance of a transimpedance amplifier in an optical transceiver is very well known. In this paper, a novel CMOS design of the bulk-driven transimpedance amplifier (BD-TIA) is given where the bridge-shunt peaking-based frequency compensation technique is exploited to improve frequency response. A pre-existing active inductor has been used for the same. The electrical characteristics and functioning of this inductor simulator make it a suitable alternative to both floating and grounded spiral inductors. In order to verify the workability of the proposed circuit, it has been simulated with TSMC CMOS 0.18 μ m process parameters. The proposed circuit is useful in low-voltage low-power VLSI applications as it uses a single supply of 0.75 V. The power consumption of BD-TIA is very low, being 0.37 mW, because a standard MOSFET has been replaced by a bulk-driven MOSFET (BDMOS), while the 3-dB bandwidth is observed to be 4.5 GHz. The mathematical investigation and small signal analysis show that the simulation results are in good agreement. [ABSTRACT FROM AUTHOR]

In this work, two frequency compensated three stage amplifiers are proposed for 20 pF and 30 pF capacitive load. Both the proposed circuits utilize class AB Flipped Voltage Follower (FVF) along with Reversed Nested Miller Compensation (RNMC) to address RHP zero issue. Further, the proposed circuits 1 and 2 employ a slew rate enhancer circuit to improve the slew rate. Additionally, both the circuits also make use of feed forward path to increase the large signal response. The simulations are performed using TSMC 0.18 µm CMOS process in Tanner tool to examine the functionality and performance of the proposed amplifiers. The proposed amplifiers exhibit GBW of 25 MHz with phase margin of 82° at 20 pF load, whereas it is 22 MHz with phase margin of 79° at 30 pF load. Moreover, DC gain is 102 dB and 110 dB for the proposed amplifier-1 and 2 respectively. Further, maximum slew rate is 10.8 V/µS at 20 pF load while it is 10.56 V/µS at 30 pF load. The maximum common mode rejection ratio and power supply rejection ratio are examined to be 87.8 dB and 87.4 dB respectively. Corner analysis has been performed to look into the process variations to verify the robustness of the proposed amplifiers. [ABSTRACT FROM AUTHOR]

This paper presents a piezoelectric energy harvesting device with anti-interference capability. The device utilizes magnetic coupling between the magnet at the tip of the piezoelectric cantilever and the alternating magnetic field surrounding power lines to efficiently harvest energy. Three piezoelectric cantilever structures are designed to optimize energy harvesting efficiency and space utilization. The impact of magnet interaction on the energy harvesting performance is investigated through theoretical analysis and experiments. The results demonstrate a decrease in the natural frequency of each piezoelectric cantilever due to magnet interaction. Frequency compensation techniques are applied to improve the overall output of the device. The anti-interference capability of the harvester is thoroughly evaluated, showing stable output even under random acceleration and the ability to withstand external interference. Additionally, the device successfully powers a wireless temperature and humidity sensor, validating its potential for self-powered wireless sensing nodes in grid monitoring systems. [Display omitted] [ABSTRACT FROM AUTHOR]

A novel active feedback frequency compensation scheme is presented in this work. Based on the proposed technique, an amplifier with two main poles in its frequency bandwidth can be easily compensated by introducing a pole-zero pair in a local feedback. The proposed method is mathematically analyzed and then based on the derived formulations, a design procedure is established. The capability of the proposed technique is examined considering a well-known two-stage amplifier, considering just a trivial modification on its input stage. To gain an analogous and fair insight, the performance of the proposed structure is compared with that is of the optimally designed miller-compensated two-stage amplifier. The post-layout simulations are accomplished with TSMC 180nm CMOS standard technology. The Spectre post-layout simulations show that the proposed structure outperforms the traditional structure in terms of power consumption and gain bandwidth product. The robustness of the design is checked with Monte Carlo simulations.