69 results on '"Frans, Yohan"'
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2. A 64 Gb/s NRZ O-Band Ring Modulator with 3.2 THz FSR for DWDM Applications
3. A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies
4. HUBUNGAN DUKUNGAN KELUARGA DAN MOTIVASI DENGAN KEPATUHAN MINUM OBAT PADA PASIEN TUBERKULOSIS DI WILAYAH KERJA PUSKESMAS CIKEMBAR KABUPATEN SUKABUMI
5. A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET
6. A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET
7. Session 8 Overview: Ultra-High-Speed Wireline
8. F6: Optical and Electrical Transceivers for 400GbE and Beyond
9. 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET
10. Xilinx Versal™ Premium
11. Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET
12. 6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET
13. A 112–134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET
14. A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET
15. ADC-based Wireline Transceiver
16. A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET
17. A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET
18. Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC)
19. An Inverter-Based Analog Front-End for a 56-Gb/s PAM-4 Wireline Transceiver in 16-nm CMOS
20. Crosstalk Associated with the Mingling of Current Returned Paths through the Vertical Bonding Structures
21. A 112-GB/S PAM4 Transmitter in 16NM FinFET
22. A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET
23. An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS
24. A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET
25. A 56 Gb/s 6 mW 300 um2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS
26. A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs
27. A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET
28. A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET
29. A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET
30. A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
31. Design techniques for 32.75Gb/s and 56Gb/s wireline transceivers in 16nm FinFET
32. A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS
33. A 0.5–16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET
34. A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET
35. A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET
36. 6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET
37. F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond
38. A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET
39. A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS
40. A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET
41. Crosstalk associated with solder ball and/or cutout-hole on the power/ground planes/nets
42. 3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET
43. A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS
44. 3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS
45. Device aware high-speed transceiver design in planar and FinFet technologies
46. Wideband flexible-reach techniques for a 0.5–16.3Gb/s fully-adaptive transceiver in 20nm CMOS
47. Optimizing the timing center for high-speed parallel buses
48. Design challenges for high performance and power efficient graphics and mobile memory interfaces
49. A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling
50. Design and characterization of a 12.8GB/s low power differential memory system for mobile applications
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