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The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level "device" side copper wiring, with line space (L/S) of = 2.5 µm, built using damascene techniques, a 55 µm glass core with through glass vias (TGVs), and multiple UBM levels finished with tin silver (SnAg) C4 bumps. The 300mm TGV wafers are processed on existing silicon wafer manufacturing equipment following established, integrated silicon process flows. Once fully processed, the glass wafers are diced, and the interposer joined to a ceramic carrier by mass reflow. Sub-assemblies are then underfilled, the top die attached, and lidding completed. The final assemblies are tested to evaluate performance of chip to chip interconnects, chip-to-package (through interposer) interconnects, and chip-to-PCB (through interposer and package) interconnects. Results of loss vs frequency measurements are compared, for the glass interposer against the existing silicon interposer results.

A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated in this paper. It is shown that nonzero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a nonzero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays. Furthermore, a technique that significantly reduces the power dissipated in the noncritical data paths is demonstrated. The application of this technique combined with nonzero clock skew scheduling to the slower data paths is also described. Speed improvements of up to 18% and power savings greater than 80% are achieved in certain functional blocks of an industrial high performance microprocessor.

A multichip module package has been designed in IBM's silicon technology. The module consists of two chips of same size and type communicating horizontally through a silicon interposer to a large ASIC chip. The chip to chip links operate at 8 Gbps with a loss of 0.5 dB/mm and reflections < 20 dB. All links are skew matched to within 2 ps. Model to hardware correlation was performed and trace loss is within 0.1 dB of modeling data. The input to the module consists of a high speed RF signal and the module was optimized for board to package transition. Outputs of the module are 15Gbps high speed links. Both input and output signals go up or down a through silicon via (TSV) in the silicon interposer as part of their electrical paths. TSV parameters do not limit the electrical performance of the module.

Ceramic packages for high performance server processors have many wiring layers and via count due to the large number of input-output (I/Os) needed in high end computers to attain performance targets. Good AC operation of the interconnect is critical to attain since long traces and vias can be very lossy in these applications. The electrical impact of manufacturing changes implemented in these modules due to mechanical, thermal, or yield issues can be difficult to discern due to the large number of structures and parameter variation in the package. In addition, most of the signals in modern processors operate at a fundamental frequency well into the gigahertz range making traditional direct current (DC) electrical measurements less meaningful to designers and process development engineers. We quantify the AC electrical impact of package manufacturing changes using a high speed microwave vector network analyzer (VNA) on the module interconnects. We measure the effect of several of these changes on various ceramic multi-chip modules (MCM) as a function of frequency. We show how these measurements have lead to a modified cross section in high performance glass ceramic (HPGC) packages used for IBM large scale server processors.

High performance glass ceramic (HPGC) packages widely used in various range of IBM server applications are characterized for high frequency performance of SerDes differential links using TDR and network analyzer measurements and their design to performance aspects are analyzed in depth. Also HPGCspsila merits and design to electrical factors are discussed in comparison with an Alumina Ceramic and an organic Flip-chip Plastic Ball Grid Array (FCPBGA) packages alongside application space as the three types of packages were built on the same footprints of chip and board IO interfaces for a test site involving different design strategies to accommodate high link density of SerDes links. While HPGC has greater advantage for reliability and high power, and FCPBGA has greater advantage for cost, both demonstrate similar performance in compromising between through transmission and noise isolation parameters. Both HPGC and FCPBGA perform better than Alumina Ceramic in those areas.

We describe a methodology to route differential pairs in vertical layers in a high performance multi-chip module ceramic package. By matching the impedance of these vertical differential pairs to their conventional counterparts and adopting a power distribution topology that effectively isolates these pairs from noise aggressors, routing was improved by 17% and simultaneous switching noise decreased by 60%. The methods described in this paper were applied successfully in the design of an IBM ceramic multi-chip module (MCM) package with good electrical performance.

On-chip power dissipation has become a fundamental design issue in high performance integrated circuits. A technique to significantly reduce the power dissipated in the non-critical data paths of an industrial circuit is demonstrated. The application of this technique with non-zero clock skew scheduling to the slower data paths is also described. Simulation results demonstrating the application of this technique to certain functional blocks of a high performance microprocessor are presented. A greater than 80% power savings is achieved in specific circuit blocks.

A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown that non-zero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a non-zero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays by replacing clock buffers from predesigned cell libraries. Timing margin improvements of up to 18% are achieved through the application of non-zero clock skew scheduling in certain functional blocks of an industrial high performance microprocessor.

Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.