F.O. Franca Rafael, N. da Silva Iseu, D. Petrović Zorica, Morbelli Silvia, Dong Pin, Haghparast-kenari Beheshteh, P. Petrović Vladimir, Daryani Ahmad, Taghi Rahimi Mohammad, Kishore Baireddy, N.L. de Morais Clarice, A.N. Azevedo Elisa, da Silva Santos Lucas, Marini Cecilia, Brahmeshwari Gavaji, Zhu Jing-Jing, de Pilla Varotti Fernando, Ran Hao, César Dias Lopes Julio, Sharif Mehdi, Simijonović Dušica, Pereira de Freitas Rossimiriam, I.O. de Sousa Larissa, C. Lima Morganna, Cui Yingtong, Yan Yong, Prasoona Gumpula, Nayeri Tooran, Sadhu Arindam, Dey Sarkar Rimpa, Fillipe Langanke de Carvalho Matheus, Claudia de Souza Pinto Ana, Pan Xin, Branković Jovica, Brondi Alves Rosemeire, Miceli Alberto, A. Bogdanović Goran, Sarvi Shahabeddin, Raffa Stefano, Wu Xue-Jun, M. Carvalho Bruno, Li Jing-Min, Li Xin-Qian, Sambuceti Gianmario, Jiang Ting-Ting, Wu Shu-Hui, Ahmadpour Ehsan, Quan Guilan, Liu Weibin, Luisa da Fonseca Amanda, Das Kunal, Bauckneht Matteo, Milovanović Vesna, Liu Yu-Ying, Ray Kanjilal Maitreyi, De Debashis, Cossu Vanessa, Novaković Slađana, Mladenović Milan, Chen Xiang, Wu Chuanbin, Isabella Donegani Maria, and Huang Ying
Aims: Embedded system plays a vital role in today’s life. Hence, our interest is in areadelay- energy efficient embedded system design in post-CMOS technology, i.e., QCA. Objectives: The research is focused on efficient area-delay-energy Configurable Logic Block (CLB) design for Field-Programmable Gate Array architecture (FPGA) with successful simulation-based on next-generation technology, Quantum-dot cellular automata. Methods: Each proposed circuit is designed on post CMOS 4 dot 2 electron technology, i.e. QCA (Quantum dot Cellular Automata), is adopted in circuit implementation due to low power dissipation, high clock frequency and high package density. QCADesigner is used to verify the functionality of every circuit. QCAPro tool is used for determining power dissipation. Results: In contrast, a new approach of using de-multiplexer replacing the decoder has been introduced that results in the reduction of the average energy dissipation by almost 57%. A NOR based D flip-flop memory architecture and multiplexer are also used in the lookup table for the configurable logic block. The proposed architecture thus reduces the overall latency. The proposed CLB consists of 6356 QCA cells covering 7.44 um2 area. Write and read latency of proposed CLB are 12 and 7.25 QCA clock, respectively. Conclusion: The present paper concludes that read and write latency reduction occurs; average energy dissipation, leakage, and switching energy dissipation are reduced in a large amount resulting in an advantage of the overall minimization of the latency for the proposed CLB in the process.