Search

CMOS sensors were successfully implemented in the STAR tracker [1]. LHC experiments have shown that efficient b tagging, reconstruction of displaced vertices and identification of disappearing tracks are necessary. An improved vertex detector is justified for the ILC. To achieve a point(spatial single layer) resolution below the one-{\mu}m range while improving other characteristics (radiation tolerance and eventually time resolution) we will need the use of 1-micron pitch pixels. Therefore, we propose a single MOS transistor that acts as an amplifying device and a detector with a buried charge-collecting gate. Device simulations both classical and quantum, have led to the proposed DoTPiX structure. With the evolution of silicon processes, well below 100 nm line feature, this pixel should be feasible. We will present this pixel detector and the present status of its development in both our institution (IRFU) and in other collaborating labs (CNRS/C2N)., Comment: A : Talk presented at the International Workshop On Linear Colliders (LCWS 2021) 15-18 March 2021.C21-03-15.1

The deep trapping gate device concept for charged particle detection was recently introduced in Saclay/IRFU. It is based on an n-MOS structure in which a buried gate, located below the n-channel, collects carriers which are generated by ionizing particles. They deposit their energy in a volume which extends in the bulk, below the buried gate. The n-channel device is based on holes in-buried gate localization. Source-drain current modulation occurs, measurable during readout. The buried gate (Deep Trapping Gate or DTG) contains deep level centers which can be introduced during process or may be made with a Quantum Well. The device can be scaled down providing a micron range resolution. The proof of principle for such a device was verified using 2D device and process simulations. Work under way focusses on the study of building blocks. In this contribution, the pixel proof of design, using existing fabrication techniques will be discussed first. The use of this pixel for photon imaging will be discussed

The concept of the deep trapping gate device was introduced fairly recently on the basis of technological and transport simulations currently used in the field of classical electron devices. The concept of a buried gate containing localized deep level centers for holes (Deep Trapping Gate or DTG) renders possible the operation of this field effect pixel detector. One alternative to Deep Level introduction is the use of a quantum box, which is a hole quantum-well and an electron barrier. In all of these cases the buried gate modulates the drain-source current. This principle was formerly evaluated with realistic simulations parameters and this shows that a measurable signal is obtained for an energy deposition of a minimum-ionizing particle within a limited silicon thickness. In this work a quantitative study of the response of such a pixel to Minimum Ionizing Particles. The influence of some parameters such as the thickness of the pixel and its lateral dimensions, on the operation of the pixel is studied here using current available simulation tools, in quantum mode when a narrow Ge layer is used as a buried gate. A bias sequence is introduced here to separate the operation of the pixel in detection and readout mode. The first frabrication technique introduced is deep impurity implantation, followed by annealing. Recent work on quantum boxes and dots opens the possibility to the use Ge boxes as a DTG.Ion implantation and alternative methods such an epitaxial growth DTG can be reasonably considered. If the related bottlenecks are overcome the pixel should be a good candidate for high luminosity particle collider inner detectors, provides that its potential radiation hardness is proven sufficient for these applications., Comment: IWORID conference 2015 paper submitted. This paper follows the preceding arxiv document "Silicon MOS Pixel Based on the Deep Trapping Gate Principle : Design and Material Science Challenges" Nicolas Fourches et. al

The deep trapping gate pixel device was described recently as an alternative to CMOS 3T pixel. The feasibilty of this device was studied with technological and transport simulations used in classical electron devices and process design. A buried gate containing localized deep level centers (Deep Trapping Gate or DTG) is the key for the operation of this field effect pixel detector. This can be made with deep levels or a quantum box. This buried gate can modulates the drain-source current, the same way the upper gate does. This principle was evaluated with realistic simulations physical parameters and this shows that the signal magnitude is sufficient for an energy deposition of a Minimum Ionizing Particle within a limited silicon thickness (a few microns). We will study here the potential techniques usable for the fabrication of the device with their drawbacks, advantages and limits. The first technique introduced is impurity implantation, followed by annealing. The problems related to the control of the defects in the DTG will be examined in the light of recent work on ion implantation. As an alternative recent work on quantum dots opens the possibility to the use Ge dots as a DTG. Ion implantation can again be used with some limitations. As an alternative to ion implantation an epitaxial DTG could be fabricated using standard techniques. The first conclusion of this study is that all the established techniques necessary for the development of the DTG pixel can reasonably be successful because the related bottlenecks may be overcome. The deep levels concentration in the DTG (above 10^18 cm-3) is higher than the concentration of radiation induced defects for integrated fluences lower than 1x10^16 cm-3.

Silicon detectors have gained in popularity since silicon became a widely used micro/nanoelectronic semiconductor material. Silicon detectors are used in particle physics as well as imaging for pixel based detecting systems. Over the past twenty years a lot of experimental efforts have been focused on the effects of ionizing and non-ionizing radiation on silicon pixels. Some of this research was done in the framework of high luminosity particle physics experiments, along with radiation hardness studies of basic semiconductors devices. In its simplest form the semiconductor pixel detectors reduce to a PIN or PN structure partially or totally depleted, or in some MOS and APD (Avalanche PhotoDiode) structures. Bulk or surface defects affect considerably transport of free carriers. We propose guidelines for pixel design, which will be tested through a few pixel structures. This design method includes into the design the properties of defects. The electrical properties reduce to parameters, which can be introduced in a standard simulation code to make predictive simulations. We include an analytical model for defect annealing derived from isochronal annealing experiments. The proposed method can be used to study pixels detectors with different geometrical structures and made with different semiconducting materials. Its purpose is to provide an alternative to tedious and extensive radiation tests on final fabricated detectors. This is necessary for the long-term reliability of detectors together with their radiation tolerance. A general method for pixel design is introduced and we will show how it can be used for the design of alternate to silicon (germanium) pixels., Comment: Conference Poster, list of authors updated