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288 results on '"Flottes, Marie-Lise"'

1. Utilizing Layout Effects for Analog Logic Locking

Author

Aljafar, Muayad J., Azais, Florence, Flottes, Marie-Lise, and Pagliarini, Samuel

Subjects
Computer Science - Cryptography and Security, Computer Science - Hardware Architecture
Abstract

While numerous obfuscation techniques are available for securing digital assets in the digital domain, there has been a notable lack of focus on protecting Intellectual Property (IP) in the analog domain. This is primarily due to the relatively smaller footprint of analog components within an Integrated Circuit (IC), with the majority of the surface dedicated to digital elements. However, despite their smaller nature, analog components are highly valuable IP and warrant effective protection. In this paper, we present a groundbreaking method for safeguarding analog IP by harnessing layout-based effects that are typically considered undesirable in IC design. Specifically, we exploit the impact of Length of Oxide Diffusion and Well Proximity Effect on transistors to fine-tune critical parameters such as transconductance (gm) and threshold voltage (Vth). These parameters remain concealed behind key inputs, akin to the logic locking approach employed in digital ICs. Our research explores the application of layout-based effects in two commercial CMOS technologies, namely a 28nm and a 65nm node. To demonstrate the efficacy of our proposed technique, we implement it for locking an Operational Transconductance Amplifier. Extensive simulations are performed, evaluating the obfuscation strength by applying a large number of key sets (over 50,000 and 300,000). The results exhibit a significant degradation in performance metrics, such as open-loop gain (up to 130dB), phase margin (up to 50 degrees), 3dB bandwidth (approximately 2.5MHz), and power consumption (around 1mW) when incorrect keys are employed. Our findings highlight the advantages of our approach as well as the associated overhead., Comment: JCEN special issue from ASHES'22

Published
2024

2. Hybrid Protection of Digital FIR Filters

Author

Aksoy, Levent, Nguyen, Quang-Linh, Almeida, Felipe, Raik, Jaan, Flottes, Marie-Lise, Dupuis, Sophie, and Pagliarini, Samuel

Subjects
Computer Science - Cryptography and Security, Electrical Engineering and Systems Science - Signal Processing
Abstract

A digital Finite Impulse Response (FIR) filter is a ubiquitous block in digital signal processing applications and its behavior is determined by its coefficients. To protect filter coefficients from an adversary, efficient obfuscation techniques have been proposed, either by hiding them behind decoys or replacing them by key bits. In this article, we initially introduce a query attack that can discover the secret key of such obfuscated FIR filters, which could not be broken by existing prominent attacks. Then, we propose a first of its kind hybrid technique, including both hardware obfuscation and logic locking using a point function for the protection of parallel direct and transposed forms of digital FIR filters. Experimental results show that the hybrid protection technique can lead to FIR filters with higher security while maintaining the hardware complexity competitive or superior to those locked by prominent logic locking methods. It is also shown that the protected multiplier blocks and FIR filters are resilient to existing attacks. The results on different forms and realizations of FIR filters show that the parallel direct form FIR filter has a promising potential for a secure design.

Published
2023

3. Leveraging Layout-based Effects for Locking Analog ICs

Author

Aljafar, Muayad J., Azais, Florence, Flottes, Marie-Lise, and Pagliarini, Samuel

Subjects
Computer Science - Cryptography and Security
Abstract

While various obfuscation methods exist in the digital domain, techniques for protecting Intellectual Property (IP) in the analog domain are mostly overlooked. Understandably, analog components have a small footprint as most of the surface of an Integrated Circuit (IC) is digital. Yet, since they are challenging to design and tune, they constitute a valuable IP that ought to be protected. This paper is the first to show a method to secure analog IP by exploiting layout-based effects that are typically seen as undesirable detractors in IC design. Specifically, we make use of the effects of Length of Oxide Diffusion and Well Proximity Effect on transistors for tuning the devices' critical parameters (e.g., gm and Vth). Such parameters are hidden behind key inputs, akin to the logic locking approach for digital ICs. The proposed technique is applied for locking an Operational Transconductance Amplifier. In order to showcase the robustness of the achieved obfuscation, the case studied circuit is simulated for a large number of key sets, i.e., >50K and >300K, and the results show a wide range of degradation in open-loop gain (up to 130dB), phase margin (up to 50 deg), 3dB bandwidth (approx. 2.5MHz), and power (approx. 1mW) of the locked circuit when incorrect keys are applied. Our results show the benefit of the technique and the incurred overheads. We also justify the non-effectiveness of reverse engineering efforts for attacking the proposed approach. More importantly, our technique employs only regular transistors and requires neither changes to the IC fabrication process nor any foundry-level coordination or trust.

Published
2022

4. High-level Intellectual Property Obfuscation via Decoy Constants

Author

Aksoy, Levent, Nguyen, Quang-Linh, Almeida, Felipe, Raik, Jaan, Flottes, Marie-Lise, Dupuis, Sophie, and Pagliarini, Samuel

Subjects
Computer Science - Cryptography and Security
Abstract

This paper presents a high-level circuit obfuscation technique to prevent the theft of intellectual property (IP) of integrated circuits. In particular, our technique protects a class of circuits that relies on constant multiplications, such as filters and neural networks, where the constants themselves are the IP to be protected. By making use of decoy constants and a key-based scheme, a reverse engineer adversary at an untrusted foundry is rendered incapable of discerning true constants from decoy constants. The time-multiplexed constant multiplication (TMCM) block of such circuits, which realizes the multiplication of an input variable by a constant at a time, is considered as our case study for obfuscation. Furthermore, two TMCM design architectures are taken into account; an implementation using a multiplier and a multiplierless shift-adds implementation. Optimization methods are also applied to reduce the hardware complexity of these architectures. The well-known satisfiability (SAT) and automatic test pattern generation (ATPG) attacks are used to determine the vulnerability of the obfuscated designs. It is observed that the proposed technique incurs small overheads in area, power, and delay that are comparable to the hardware complexity of prominent logic locking methods. Yet, the advantage of our approach is in the insight that constants -- instead of arbitrary circuit nodes -- become key-protected.

Published
2021

5. SECCS: SECure Context Saving for IoT Devices

Author

Valea, Emanuele, Da Silva, Mathieu, Natale, Giorgio, Flottes, Marie-Lise, Dupuis, Sophie, and Rouzeyre, Bruno

Subjects
Computer Science - Cryptography and Security
Abstract

Energy consumption of IoT devices is a very important issue. For this reason, many techniques have been developed to allow IoT nodes to be aware of the amount of available energy. When energy is missing, the device halts and saves its state. One of those techniques is context saving, relying on the use of Non-Volatile Memories (NVM) to store and restore the state of the device. However, this information, as far as IoT devices deal with security, might be the target of attacks, including tampering and theft of confidential data. In this paper, we propose a SECure Context Saving (SECCS) approach that provides a context saving procedure and a hardware module easy to implement inside a System on Chip (SoC). This approach provides both confidentiality and integrity to all the CPU content saved into the target NVM.

Published
2019

10. Hybrid Protection of Digital FIR Filters

Author

Aksoy, Levent, primary, Nguyen, Quang-Linh, additional, Almeida, Felipe, additional, Raik, Jaan, additional, Flottes, Marie-Lise, additional, Dupuis, Sophie, additional, and Pagliarini, Samuel, additional

Published
2023
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11. Laser-Induced Fault Effects in Security-Dedicated Circuits

Author

Beroulle, Vincent, Candelier, Philippe, De Castro, Stephan, Di Natale, Giorgio, Dutertre, Jean-Max, Flottes, Marie-Lise, Hély, David, Hubert, Guillaume, Leveugle, Regis, Lu, Feng, Maistri, Paolo, Papadimitriou, Athanasios, Rouzeyre, Bruno, Tavernier, Clement, Vanhauwaert, Pierre, Rannenberg, Kai, Editor-in-chief, Sakarovitch, Jacques, Series editor, Goedicke, Michael, Series editor, Tatnall, Arthur, Series editor, Neuhold, Erich J., Series editor, Pras, Aiko, Series editor, Tröltzsch, Fredi, Series editor, Pries-Heje, Jan, Series editor, Whitehouse, Diane, Series editor, Reis, Ricardo, Series editor, Furnell, Steven, Series editor, Furbach, Ulrich, Series editor, Winckler, Marco, Series editor, Rauterberg, Matthias, Series editor, Claesen, Luc, editor, Sanz-Pascual, Maria-Teresa, editor, and Sarmiento-Reyes, Arturo, editor

Published
2015
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13. Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture

Author

Ammoura, Lila, Flottes, Marie-Lise, Girard, Patrick, Noël, Jean-Philippe, Virazel, Arnaud, Test and dEpendability of microelectronic integrated SysTems (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF], Test, Resistive-open defect, In-Memory Computing, 8T SRAM cell
Abstract

International audience; The adoption of In-Memory Computing (IMC) architectures is one of the promising approaches to efficiently solve the Von Neumann bottleneck problem. In addition to arithmetic operations, IMC architectures aim at integrating additional logic operations directly in the memory array or/and at the periphery for saving time and power consumption. In this paper, a comprehensive model of a 128x128 bitcell array based on a 28nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive-open defects injected in the read port. A hierarchical analysis including a detailed study of each defect was performed in order to determine their impact both in memory and computing modes, both locally on the defective bitcell and globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-open defects.

Published
2023

14. Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture

Author

Ammoura, Lila, Flottes, Marie-Lise, Girard, Patrick, Noel, Jean-Philippe, Virazel, Arnaud, Test and dEpendability of microelectronic integrated SysTems (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
Test, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Resistive defect analysis, In-Memory Computing, 8T SRAM cell
Abstract

International audience; A promising new alternative to efficiently solve the Von Neumann bottleneck problem is to adopt In-Memory Computing (IMC) architectures. Beyond the arithmetic operations, IMC architectures aim at integrating additional logic operators directly in the memory array or/and at the periphery in order to provide close computing abilities. However, they are subject to manufacturing defects in the same way as conventional memories. In this paper, a comprehensive model of a 128 × 128 bitcell array based on 28 nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive defects (open and short) injected in the read port. A hierarchical analysis allowing a thorough study of each defect has been carried in order to identify their impact in both memory and computing modes, locally on the defective bitcell as well as globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-short and resistive-open defects.

Published
2023

17. A New Scan Attack on RSA in Presence of Industrial Countermeasures

Author

Da Rolt, Jean, Das, Amitabh, Di Natale, Giorgio, Flottes, Marie-Lise, Rouzeyre, Bruno, Verbauwhede, Ingrid, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Schindler, Werner, editor, and Huss, Sorin A., editor

Published
2012
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22. Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture

Author

Ammoura, Lila, Flottes, Marie-Lise, Girard, Patrick, Noel, Jean-Philippe, Virazel, Arnaud, Test and dEpendability of microelectronic integrated SysTems (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
Short defect analysis, Test, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, In-Memory Computing, 8T SRAM cell
Abstract

National audience; A promising new alternative to efficiently solve the von Neumann bottleneck problem is to adopt In-Memory Computing (IMC) architectures. Beyond the arithmetic operations, IMC architectures aim at integrating additional logic operators directly in the memory array or/and at the periphery in order to provide close computing abilities. However, they are subject to manufacturing defects in the same way as conventional memories. In this paper, a comprehensive model of a 128x128 bitcell array based on 28nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of short defects injected in the read port. A hierarchical analysis allowing a thorough study of each defect has been carried in order to identify their impact in both memory and computing modes, locally on the defective bitcell as well as globally on the array.

Published
2022

24. Laser-Induced Fault Effects in Security-Dedicated Circuits

Author

Beroulle, Vincent, primary, Candelier, Philippe, additional, De Castro, Stephan, additional, Di Natale, Giorgio, additional, Dutertre, Jean-Max, additional, Flottes, Marie-Lise, additional, Hély, David, additional, Hubert, Guillaume, additional, Leveugle, Regis, additional, Lu, Feng, additional, Maistri, Paolo, additional, Papadimitriou, Athanasios, additional, Rouzeyre, Bruno, additional, Tavernier, Clement, additional, and Vanhauwaert, Pierre, additional

Published
2015
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25. Sécurité et intégrité dans un Contexte Embarqué

Author

Lapeyre, Sébastien, Valette, Nicolas, Merandat, Marc, Flottes, Marie-Lise, Rouzeyre, Bruno, Virazel, Arnaud, INVIA, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
authentification défi-réponse, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Autotests, tests, Sécurité, cryptographie légère, Sureté, Capteurs Analogues, JTAG
Abstract

National audience; Lors du design d'un circuit intégré, il est nécessaire d'implémenter des fonctionnalités complémentaires de tests et sécuritaires pour assurer la qualité, la fiabilité et la sécurité. Nos travaux ont pour optique d'être implémentés dans des systèmes embarqués avec comme forte contrainte d'être le plus petit possible en termes de surface utilisée. Dans ce papier nous présentons une solution de test pour des capteurs analogiques à vocation sécuritaire, ainsi qu'une méthode d'authentification permettant de protéger l'accès à une infrastructure de test, le JTAG.

Published
2021

32. Erratum to: SOC Design Methodologies

Author

Robert, Michel, Rouzeyre, Bruno, Piguet, Christian, Flottes, Marie-Lise, Robert, Michel, editor, Rouzeyre, Bruno, editor, Piguet, Christian, editor, and Flottes, Marie-Lise, editor

Published
2002
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36. Encryption Techniques for Test Infrastructures

Author

Valea, Emanuele, Flottes, Marie-Lise, Di Natale, Giorgio, Rouzeyre, Bruno, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
[INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], Test data encryption, Test and Security, Stream cipher, Hardware_PERFORMANCEANDRELIABILITY, Block cipher
Abstract

National audience; Test infrastructures are widely deployed in modern Systems-on-Chip (SoC). They allow the tester to control and observe the internal state of the SoC. However, a malicious user can exploit these infrastructures in order to extract secret information stored inside the SoC. In this paper, we review and compare security countermeasures based on the encryption of test data. The present techniques ensure the confidentiality of the exchanged messages between the circuit and the tester. Moreover, they provide lightweight user authentication in order to prevent malicious users from accessing the test infrastructure.

Published
2019

37. Stream Cipher Based Encryption in IEEE Test Standards

Author

Valea, Emanuele, Flottes, Marie-Lise, Di Natale, Giorgio, Rouzeyre, Bruno, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
PACS 85.42, Stream cipher, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, JTAG, Scan encryption, ComputingMilieux_MISCELLANEOUS, Test vs security
Abstract

International audience; IEEE test standards have been developed in order to sustain the deployment of complex test infrastructures inside modern Integrated Circuits (IC). Security is a primary issue in test infrastructures. For instance, confidentiality of sensitive data flowing through the test infrastructure must be ensured. User authentication is also crucial in order to avoid secret stealing and/or device corruption. In this paper, we propose a secure JTAG implementation, based on stream cipher encryption. This countermeasure provides data confidentiality and lightweight user authentication at the cost of a little area overhead on the whole IC.

Published
2019

39. Sécurité des moyens de test des SoC

Author

Da Silva, Mathieu, Flottes, Marie-Lise, Di Natale, Giorgio, Rouzeyre, Bruno, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
[SPI]Engineering Sciences [physics], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

National audience

Published
2018

40. Stream cipher-based scan encryption in test standards

Author

Da Silva, Mathieu, Valea, Emanuele, Flottes, Marie-Lise, Di Natale, Giorgio, Rouzeyre, Bruno, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
Stream Cipher, Scan Attacks, Security, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Scan Encryption
Abstract

National audience; Scan chains offer facilities to steal secret information embedded in a circuit. For instance on a crypto-processor, collecting data related to the round register leads to reveal the secret key used for encryption. To protect against this threat while maintaining the test and debug features, countermeasures are implemented on the test interface or on the scan chain itself. Among the countermeasures, some of them are based on stream ciphers, consisting in the encryption of both controlled and observed data in the scan chain. We show in this paper that the stream cipher protection presents vulnerabilities if the keystream generated by the stream cipher is identical after a reset.

Published
2018

41. Scan chain encryption in Test Standards

Author

Da Silva, Mathieu, Di Natale, Giorgio, Flottes, Marie-Lise, Rouzeyre, Bruno, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
[SPI]Engineering Sciences [physics], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2018

42. Scan chain encryption, a countermeasure against scan attacks

Author

Da Silva, Mathieu, Di Natale, Giorgio, Flottes, Marie-Lise, Rouzeyre, Bruno, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
[SPI]Engineering Sciences [physics], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2018

43. Does stream cipher-based scan chains encryption really prevent scan attacks?

Author

Da Silva, Mathieu, Flottes, Marie-Lise, Di Natale, Giorgio, Rouzeyre, Bruno, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
Stream Cipher, Scan Attacks, Differential attack, Security, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Scan chains offer facilities to steal secret information embedded in a circuit. For instance on a crypto-processor, collecting data related to the round register leads to reveal the secret key used for encryption. To protect against this threat while maintaining the test and debug features, countermeasures are implemented on the test interface or on the scan chain itself. Among the countermeasures, some of them are based on stream ciphers, consisting in the encryption of both controlled and observed data in the scan chain. We show in this paper that the stream cipher protection presents vulnerabilities if the keystream generated by the stream cipher is identical after a reset.

Published
2018

44. Il Futuro della Cybersecurity in Italia: Ambiti Progettuali Strategici

Author

Baldoni, Roberto, De Nicola, Rocco, Prinetto, PAOLO ERNESTO, Anglano, COSIMO FILOMENO, Aniello, Leonardo, Antinori, Arije, Armando, Alessandro, Aversa, Rocco, Baldi, Marco, Barili, Antonio, Bartoletti, Massimo, Basile, Basile, Bellini, Marco, Bergadano, Francesco, Bernardeschi, Cinzia, Bertino, Elisa, Bianchi, Giuseppe, Biancotti, Claudia, Bistarelli, Stefano, BLEFARI MELAZZI, Nicola, Boetti, Milena, Bondavalli, Andrea, Bonomi, Silvia, Buccafurri, Francesco, Cambiaso, Enrico, Caputo, Barbara, Carminati, Barbara, Cataliotti, Francesco Saverio, Catarci, Tiziana, Ceccarelli, Andrea, CESA BIANCHI, NICOLO' ANTONIO, Chiaraluce, Franco, Colajanni, Michele, Conti, Marco, Conti, Mauro, Coppolino, Luigi, Costa, Gabriele, Costamagna, Valerio, Cotroneo, Domenico, Crispo, Bruno, Cucchiara, Rita, D’Antonio, Salvatore, Damiani, Ernesto, De Santis, Alfredo, Di Battista, Giuseppe, Di Martino, Beniamino, Degiovanni, Ivo Pietro, Demetrescu, Camil, Di Corinto, Arturo, DI LUNA, GIUSEPPE ANTONIO, Di Natale, Giorgio, Dini, Gianluca, Evangelisti, Marco, Falcinelli, Daniela, Figà, Gianna, Ferretti, Marco, Ficco, Massimo, Flocchini, Paola, Flottes, Marie-Lise, Focardi, Riccardo, Franchina, Luisa, Furfaro, Angelo, Girdinio, Paola, Guida, Franco, Italiano, Giuseppe F., Lain, Daniele, Laurenti, Nicola, Lioy, Antonio, Loreti, Michele, Malerba, Donato, Mancini, Luigi Vincenzo, MARCHETTI SPACCAMELA, Alberto, Marcialis, Gianluca, Margheri, Andrea, Marrella, Andrea, Martinelli, Fabio, Martinelli, Maurizio, Martino, Luigi, Massacci, Fabio, Mayer, Marco, Mecella, Massimo, Mensi, Maurizio, Merlo, Alessio, Miculan, Marino, Montanari, Luca, Morana, Marco, Mosco, Gian Domenico, Mostarda, Leonardo, Murino, Vittorio, Nardi, Daniele, Navigli, Roberto, Palazzi, Andrea, MACARONE PALMIERI, Francesco, Panetta, Ida Claudia, Passarella, Andrea, Pellegrini, Alessandro, Pelosi, Gerardo, Pellegrino, Giancarlo, Pirlo, Giuseppe, Piuri, Vincenzo, Pizzonia, Maurizio, Pogliani, Marcello, Polino, Mario, Pontil, Massimiliano, Prinetto, Paolo, Quaglia, Francesco, Quattrociocchi, Walter, Querzoni, Leonardo, Rak, Massimiliano, Ranise, Silvio, Ricci, Elisa, Rossi, Lorenzo, Rota, Paolo, Russo, Ludovico Orlando, Samarati, Pierangela, Santoro, Nicola, Santucci, Beppe, Sassone, Vladimiro, Scala, Antonio, Scotti, Fabio, Servida, Andrea, Spagnoletti, Paolo, Spalazzi, Luca, Spidalieri, Francesca, Spoto, Austo, Squarcina, Marco, Stefanelli, Stefania, Vecchio, Alessio, Venticinque, Salvatore, Villoresi, Paolo, Visaggio, Aaron, Vitaletti, Andrea, and Zanero, Stefano

Subjects
Cyber security
Published
2018

45. A Comprehensive Approach to a Trusted Test Infrastructure

Author

Merandat, Marc, primary, Reynaud, Vincent, additional, Valea, Emanuele, additional, Quevremont, Jerome, additional, Valette, Nicolas, additional, Maistri, Paolo, additional, Leveugle, Regis, additional, Flottes, Marie-Lise, additional, Dupuis, Sophie, additional, Rouzeyre, Bruno, additional, and Di Natale, Giorgio, additional

Published
2019
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48. Encryption-Based Secure JTAG

Author

Valea, Emanuele, primary, Silva, Mathieu Da, additional, Flottes, Marie-Lise, additional, Natale, Giorgio Di, additional, and Rouzeyre, Bruno, additional

Published
2019
Full Text
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50. Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS Bulk

Author

Dutertre, Jean-Max, primary, Beroulle, Vincent, additional, Candelier, Philippe, additional, De Castro, Stephan, additional, Faber, Louis-Barthelemy, additional, Flottes, Marie-Lise, additional, Gendrier, Philippe, additional, Hely, David, additional, Leveugle, Regis, additional, Maistri, Paolo, additional, Di Natale, Giorgio, additional, Papadimitriou, Athanasios, additional, and Rouzeyre, Bruno, additional

Published
2019
Full Text
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