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Indoor navigation is essential to a wide spectrum of applications in the era of mobile computing. Existing vision-based technologies suffer from both start-up costs and the absence of semantic information for navigation. We observe an opportunity to leverage pervasively deployed surveillance cameras to deal with the above drawbacks and revisit the problem of indoor navigation with a fresh perspective. In this paper, we propose \sysname, a system that enables public surveillance cameras, as indoor navigating satellites, to locate users on the floorplan, tell users with semantic information about the surrounding environment, and guide users with navigation instructions. However, enabling public cameras to navigate is non-trivial due to 3 factors: absence of real scale, disparity of camera perspective, and lack of semantic information. To overcome these challenges, \sysname leverages POI-assisted framework and adopts a novel coordinate transformation algorithm to associate public and mobile cameras, and further attaches semantic information to user location. Extensive experiments in 4 different scenarios show that \sysname achieves a localization accuracy of 0.48m and a navigation success rate of 90.5%, outperforming the state-of-the-art systems by over 30%. Benefitting from our solution, all areas with public cameras can upgrade to smart spaces with visual navigation services.

Generator-based integrated-circuit design flows are crucial for meeting the aggressive system-on-chip development timelines demanded by rapidly changing modern workloads. Generators allow chip designers to develop complex solutions to classes of problems rather than individual instances, allowing significant design changes late in the development cycle and enabling incremental improvements to existing solutions. The philosophies of welcoming changing requirements and steady, incremental development have been embraced by the software development community for some time, but have only recently been incorporated into hardware development. While this adoption of proven software development philosophies has decreased the turnaround time of systems-on-chip, productivity has been limited by hard-to-automate tasks like physical design. Each generated design instance requires a new human-generated floorplan or other changes to the physical design flow, limiting the throughput of design space exploration by the available engineering resources. Automation of physical design is therefore critical for state-of-the-art generator-based system-on-chip design.This work describes a series of generator-based integrated circuits manufactured in 28nm FD-SOI and 16nm FinFET, outlines the physical design challenges encountered in their development, and presents a physical design methodology purpose-built to solve these challenges. The integrated circuits presented include an 8192-point digital spectrometer in 28nm FD-SOI, a dual-core RISC-V vector processor with on-chip fine-grain power management in 28nm FD-SOI, a dual-lane RISC-V vector processor with a dedicated on-chip power management core in 28nm FD-SOI, an eight-core RISC-V vector machine in 16nm FinFET, and a 21-core RISC-V vector machine with a systolic array accelerator in 16nm FinFET. The eight-core chip achieves a state-of-the-art energy efficiency of 209.5 GFLOPS/W on a half-precision matrix multiplication (GEMM) kernel.The physical design methodology presented uses a framework, Hammer, to provide reusable physical design deliverables by decoupling the design-specific, tool-specific, and technology-specific aspects of back-end design along with a novel floorplan generation framework for Chisel designs. This physical design methodology has been incorporated into the Chipyard framework, an open-source RISC-V system-on-chip development platform leveraging the Chisel hardware construction language. The floorplan generation framework allows Chisel programs, which generate RTL, to specify composable floorplans without modifying the original source code. The flow solves common challenges associated with floorplanning generated RTL, such as SRAM mapping and placement, demonstrating the efficacy of floorplan generation in reducing the overhead and cycle times of generator-based design.

The parsing of floorplans has been an issue for a long time in automated document processing and with algorithmic methods until recent years. This problem has also improved output with the emergence of convolutionary neural networks (CNN). The job here is to obtain spatial and geometrical data from floorplans as accurately as possible. The aim of this project is to extract the most information from a floor plan image around instance segmentation models like Cascade Mask R-CNN. A new style of key point CNN is being implemented to supplement the segmentation to find correct corner positions. Then the resulting segmentation is combined in a post-processing stage. With a mean IoU of 72.7 percent versus 57.5 percent, the resulting segmentation scores surpass the existing baseline of the CubiCasa5k floorplan data base. Moreover, for almost every class, the mean IoU for each class is increased. Cascade Mask R-CNN has also been shown to be better suited to this role than Mask R-CNN.

Electronic Design Automation (EDA) comprises a series of computationally difficult optimization problems that require substantial specialized knowledge as well as a considerable amount of trial-and-error efforts. However, open challenges including long simulation runtime and lack of generalization continue to restrict the applications of existing EDA tools. Recently, learning-based algorithms especially reinforcement learning (RL) have been successfully applied to handle various combinatorial optimization problems by automatically acquiring knowledge from the past experience. In this paper, we formulate the floorplanning problem, the first stage of the physical design flow, as a Markov Decision Process (MDP). An end-toend learning-based floorplanning framework GoodFloorplan is proposed to explore the design space, which combines graph convolutional network (GCN) and RL. Experimental results demonstrate that, compared with state-of-the-art heuristic-based floorplanners, the proposed GoodFloorplan can provide better area and wirelength.

The tremendous growth in deep learning (DL) applications has created an exponential demand for computing power, which leads to the rise of AI-specific hardware. Targeted towards accelerating computation-intensive deep learning applications, AI hardware, including but not limited to GPGPU, TPU, ASICs, etc., have been adopted ubiquitously. As a result, domainspecific CAD tools play more and more important roles and have been deeply involved in both the design and compilation stages of modern AI hardware. Recently, ISPD 2020 contest introduced a special challenge targeting at the physical mapping of neural network workloads onto the largest commercial deep learning accelerator, CS-1 Wafer-Scale Engine (WSE). In this paper, we proposed CU.POKer, a high-performance engine fullycustomized for WSE’s DNN workload placement challenge. A provably optimal placeable kernel candidate searching scheme and a data-flow-aware placement tool are developed accordingly to ensure the state-of-the-art quality on the real industrial benchmarks. Experimental results on ISPD 2020 contest evaluation suites demonstrated the superiority of our proposed framework over not only the state-of-the-art (SOTA) placer but also the conventional heuristics used in general floorplanning.

We present an accurate and automatic bottom-up floorplan reconstruction method by leveraging geometric priors extracted from raw point clouds of indoor scenes. Compared to two state-of-the-art methods which adopt point density as priors only, our designed geometric priors integrate point density with indoor area recognition and normal information. These geometric priors are used to calculate the confidence score for each unit region as part of the external boundaries. A cost function is developed according to the confidence scores and the normals along a certain edge, as well as the edge length. By minimizing the cost function, we can automatically estimate candidate edges, and connect them edge by edge to generate rough external boundaries. After diminishing the redundant edges, we can finally solve for a fine closed-loop external boundary path via an efficient heuristic method. We validate our method on intensive real indoor scenes. Experimental results show that our method outperforms two state-of-the-art methods in terms of reconstructing accurate external floorplan boundaries.

Τα τελευταία χρόνια υπάρχει αυξημένη ερευνητική δραστηριότητα στην αυτόματη αναγνώριση στοιχείων σε εικόνες από κατόψεις κτιρίων. Η παρούσα εργασία έχει ως σκοπό την εξαγωγή πληροφορίας από μία εικόνα κάτοψης και την μετατροπή της σε έναν γράφο ο οποίος χρησιμοποιείται για τον σχεδιασμό της συντομότερης διαδρομής σε περίπτωση επείγουσας εκκένωσης ενός κτιρίου. Αρχικά, αναγνωρίζονται τα βασικά στοιχεία της εικόνας κάτοψης, όπως τοίχοι, δωμάτια και πόρτες. Αυτό επιτυγχάνεται με την χρήση του βαθιού νευρωνικού δικτύου Panoptic-Deeplab, το οποίο πραγματοποιεί πανοπτική κατάτμηση σε εικόνες και είναι διαθέσιμο στην βιβλιοθήκη κατάτμησης εικόνων Deeplab2. Το νευρωνικό δίκτυο εκπαιδεύτηκε χρησιμοποιώντας το σύνολο δεδομένων CubiCasa5K, το οποίο αποτελείται από 5000 εικόνες και περιέχει πάνω από 80 κατηγορίες στοιχείων κάτοψης. Έπειτα, χρησιμοποιώντας την πρόβλεψη για κάθε εικονοστοιχείο, δημιουργείται ένας γράφος που δείχνει πώς συνδέονται τα δωμάτια και οι πόρτες μεταξύ τους. Αναπτύχθηκε επίσης μια εφαρμογή η οποία παρουσιάζει αυτές τις πληροφορίες στον χρήστη και παρέχει δυνατότητα επεξεργασίας του γράφου. Τελικά, ορίζονται οι έξοδοι και υπολογίζεται η συντομότερη διαδρομή από κάθε κόμβο χρησιμοποιώντας τον αλγόριθμο Dijkstra, Automatic identification of various design elements in a floor plan image has gained increased attention in recent research. Current work aims to extract information from a floor plan image and transform it into a graph that is used for pathfinding in an emergency evacuation. First, the basic elements of the floor plan image, i.e., walls, rooms and doors, are identified. This is achieved using Panoptic-Deeplab, which is a state-of-the-art deep neural network for panoptic segmentation of images, and it is available in DeepLab2, an image segmentation library. The neural network was trained using CubiCasa5K, a large-scale floor plan image dataset containing 5000 samples, annotated into over 80 floor plan object categories. Then, using the prediction of each pixel, a graph is created which shows how the rooms and the doors are connected. An application was developed which presents this information in a user-friendly manner and provides graph editing capabilities. Finally, the exits are set, and the optimal path for evacuation is calculated from each node using Dijkstra's algorithm.

The increasing size of modern field programmable gate arrays (FPGAs) allows for ever more complex applications to be mapped onto them. However, long design implementation times for large designs can severely affect design productivity. A modular design methodology can improve design productivity in a divide and conqueror fashion but at the expense of degraded performance and power consumption of the resulting implementation. To reduce the dominant power dissipation component in FPGAs, the routing power, methodologies have been proposed that consider data communication between modules during module formation and placement on the FPGA. Selecting proper mapping region on target FPGAs, on the other hand, is becoming a critical process because of the heterogeneous resources and column arrangements in modern FPGAs. Selecting inappropriate FPGA regions for mapping could lead to degraded performance. Hence, we propose a methodology that uses communication-aware module placement, such that modules are mapped by selecting the best shape and region on the FPGA factoring the columnar resource arrangements. Additionally, techniques for module locking and splitting have been proposed for deterministic convergence of the algorithm and for improved module placement. This methodology exhibits nearly 19% routing power reduction with respect to commercial CAD flows without any degradation in achievable performance.

Multiple Supply Voltage (MSV) is a known design technique to deal with the power and thermal issues of Multi Processor System on Chips (MPSoCs). In this paper, an MSV driven synthesis flow is proposed in four phases for the design of application-specific MPSoCs. The first phase conducts the core-to-router allocation concerning the operating voltages of cores as well as the bandwidth/latency requirements of the data flowing between the cores. The second phase coordinates voltages of cores connected to the same router. The third phase refines the power delivery network using our proposed voltage-aware hierarchical floorplanning algorithm. Finally, router-to-router connection and path allocation are done by the use of existing methods in the last phase. For the first time, we perform the core to router allocation phase before the voltage islanding phase to find the highest number of design solutions satisfying the set of given constraints; this in turn, improves the flexibility and efficiency of our synthesis process. Exhaustive experimental evaluations have been done on real-world benchmarks. Results confirm achieving 90% more design solutions (to conduct a wiser design space exploration) and an average of 93% Energy Delay Product (EDP) improvement as compared to the existing synthesis approaches.

The positioning of laser scanners for indoor surveying is still a time and cost expensive process. This article proposes an optimization approach for computing an admissible sensor placement with the minimal number of sensor view point positions. The approach facilitates both wall and floor surveying based on a floorplan of the study object. Optimal solutions are calculated by solving an Integer Linear Program that respects manufacturer specifications incorporating constraints such as full coverage. To enable a subsequent co-registration of the scans, a flow-based constraint formulation ensuring the connectivity of the selected positions in an appropriately defined geometric intersection graph is introduced. The method has been evaluated on real-world objects and compared to heuristic methods that have frequently been used for related problems. Our solutions outperform heuristic approaches regarding both running time and the number of TLS stations. In a case study with a larger floorplan of an institute building and with different parameter settings, our method resulted in a solution with at least two stations less compared to a solution generated by an expert.

High temperature or temperature nonuniformity has become a serious threat to performance and reliability of high-performance integrated circuits (ICs). Since the temperature in a 3-D IC is mainly determined by a power distribution across tiers, this article proposes a novel method to allocate modules to tiers while exploring a better power distribution according to the hyperparameter optimization technique. In addition, we integrate the sub-3-D thermal mask into the analytical formulation to interleave high power consumption modules in contiguous tiers during distributing modules over placement regions so that it is possible to insert through-silicon vias (TSVs) around high power modules to further reduce the temperature at a later stage. Since the temperature in a tier will be changed every time the locations of TSVs in its lower tier are moved, we also propose a procedure to update the temperature map before refining locations of TSVs. Experimental results have demonstrated that the proposed methodology can effectively reduce the temperature of a 3-D IC with a slight increase in the wirelength. Moreover, its runtime is quite fast.

In this paper, we propose a novel approach that reconstructs the indoor scene in a structure-aware manner and produces two meshes with different levels of abstraction. To be precise, we start from the raw triangular mesh of indoor scene and decompose it into two parts: structure and non-structure objects. On the one hand, structure objects are defined as significant permanent parts in the indoor environment such as floors, ceilings and walls. In the proposed algorithm, structure objects are abstracted by planar primitives and assembled into a polygonal structure mesh. This step produces a compact structure-aware watertight model that decreases the complexity of original mesh by three orders of magnitude. On the other hand, non-structure objects are movable objects in the indoor environment such as furniture and interior decoration. Meshes of these objects are repaired and simplified according to their relationship with respect to structure primitives. Finally, the union of all the non-structure meshes and structure mesh comprises the scene mesh. Note that structure mesh and scene mesh preserve various levels of abstraction and can be used for different applications according to user preference. Our experiments on both LIDAR and RGBD data scanned from simple to large scale indoor scenes indicate that the proposed framework generates structure-aware results while being robust and scalable. It is also compared qualitatively and quantitatively against popular mesh approximation, floorplan generation and piecewise-planar surface reconstruction methods to demonstrate its performance.

Layout-dependent effects (LDEs) have become increasingly more important in the synthesis of analog integrated circuits. In this article, a two-phase hybrid sizing method for high-performance analog circuits is proposed. It consists of $g_{m}$ / $I_{D}$ -based device characterization, circuit modeling, sensitivity-based constraints for LDEs, mixed-integer nonlinear programming (MINLP) in the first phase, and many-objective evolutionary algorithm (many-OEA)-based sizing in the second phase. In the first phase, accurate device characterization is handled with little modeling effort thanks to the $g_{m}$ / $I_{D}$ design methodology. Then, the LDE parameters that are linked to the normalized dc current are further optimized with the aid of sensitivity analysis. Thus, a variety of electrical, geometrical, and LDE-related constraints can be conveniently integrated into modeling of the sizing problem. In the second phase, the many-OEA-based sizing refiner can further optimize the LDE parameters by using more detailed layout information via our proposed model. A new floorplan variation scheme is also applied to improve computation efficiency and enhance optimization effectiveness. The experimental results demonstrate high efficacy of our proposed methodology in LDE-aware analog sizing optimization.

Nowadays, field-programmable gate array (FPGA) devices have been widely used in various fields. However, modules of circuits to be executed on FPGAs are placed within rectangular reconfigurable regions (RRs) with current floorplanners, leading to internal fragments, and lower utilization of resources. To address this, a dynamic description model of RRs and the corresponding floorplanner named dynamic union partial reconfiguration floorplan (DUPRFloor) are proposed in this article. The RR dynamic description modeling adds an anchor within a rectangular RR to reduce internal fragments. In this way, the modeling can represent both rectangular and nonrectangular shapes. Then, to find the optimal anchor, a clipping method is devised by constraining width and height of the candidate region. Finally, the mixed-integer linear programming (MILP) is used to optimize an objective function which considers the resources utilization and communication costs to obtain a desirable floorplanning result. The proposed method has been validated by simulation on three kinds of devices. And experimental results show that reconfigurable resources can be saved as much as 19.16% compared to rectangular modeling method. The DUPRFloor is also validated on the Microelectronics Center of North Carolina standard benchmark data sets. Results show that DUPRFloor can reduce 18.65% global wire length at most with almost the same execution time compared to state-of-the-art algorithms. Our approach is tested on a FPGA implemented software-defined radio (SDR) and reduced 29.41% wasted configurable frames, and to the overall design, 2% configurable frames are saved at most.

Due to the rapid development of indoor location-based services, automatically deriving an indoor semantic floorplan becomes a highly promising technique for ubiquitous applications. To make an indoor semantic floorplan fully practical, it is essential to handle the dynamics of semantic information. Despite several methods proposed for automatic construction and semantic labeling of indoor floorplans, this problem has not been well studied and remains open. In this article, we present a system called SiFi to provide accurate and automatic self-updating service. It updates semantics with instant videos acquired by mobile devices in indoor scenes. First, a crowdsourced-based task model is designed to attract users to contribute semantic-rich videos. Second, we use the maximum likelihood estimation method to solve the text inferring problem as the sequential relationship of texts provides additional geometrical constraints. Finally, we formulate the semantic update as an inference problem to accurately label semantics at correct locations on the indoor floorplans. Extensive experiments have been conducted across 9 weeks in a shopping mall with more than 250 stores. Experimental results show that SiFi achieves 84.5% accuracy of semantic update.

Silicon photonics is the leading candidate technology for high-speed and low-energy-consumption networks. Thermal and process variations are the two main challenges of achieving high-reliability photonic networks. Thermal variation is due to the heat issues created by application, floorplan, and environment, while process variation is caused by fabrication variability in the deposition, masking, exposition, etching, and doping. Tuning techniques are then required to overcome the impact of the variations and efficiently stabilize the performance of silicon photonic networks. We extend our previous optical switch integration model, BOSIM, to support the variation and thermal analyses. Based on device properties, we propose indirect feedback tuning (IFT) to simultaneously alleviate thermal and process variations. IFT can improve the BER of silicon photonic networks to 10−9 under different variation situations. Compared to state-of-the-art techniques, IFT can achieve an up to $1.52 \times 10^{8}$ times bit-error-rate improvement and 4.11X better heater energy efficiency. Indirect feedback does not require high-speed optical signal detection, and thus, the circuit design of IFT saves up to 61.4% of the power and 51.2% of the area compared to state-of-the-art designs.

Vectorized reconstruction from indoor point cloud has attracted increasing attention in recent years due to its high regularity and low memory consumption. Compared with aerial mapping of outdoor urban environments, indoor point cloud generated by LiDAR scanning or image-based 3D reconstruction usually contain more clutter and missing areas, which greatly increase the difficulty of vectorized reconstruction. In this paper, we propose an effective multistep pipeline to reconstruct vectorized models from indoor point cloud without the Manhattan or Atlanta world assumptions. The core idea behind our method is the combination of a sequence of 2D segment or cell assembly problems that are defined as global optimizations while reducing the reconstruction complexity and enhancing the robustness to different scenes. The proposed method includes a semantic segmentation stage and a reconstruction stage. First, we segment the permanent structures of indoor scenes, including ceilings, floors, walls and cylinders, from the input data, and then, we reconstruct these structures in sequence. The floorplan is first generated by detecting wall planes and selecting optimal subsets of projected wall segments with Integer Linear Programming (ILP), followed by constructing a 2D arrangement and recovering the ceiling and floor structures by Markov Random Filed (MRF) labeling on the arrangement. Finally, the wall structures are modeled by lifting each edge of the arrangement to a proper height by means of another global optimization. Merging the respective results yields the final model. The experimental results show that the proposed method could obtain accurate and compact vectorized models on both precise LiDAR data and defect-laden MVS data compared with other state-of-the-art approaches.

Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields. Machine learning tools are used to greatly accelerate chip layout design, by posing chip floorplanning as a reinforcement learning problem and using neural networks to generate high-performance chip layouts.

A rectangular floorplan (RFP) is a partition of a rectangle R into rectangles R 1 , R 2 , … , R n such that no four of them meet at a point. Rectangular floorplans find their applications in VLSI circuits floorplanning and architectural floorplanning. Let G represent the graph of a rectangular floorplan RFP 1 ( n ) and H be a subgraph of G , where n denotes the number of rectangles in RFP 1 ( n ) . It is well known that every subgraph of G may not admit an RFP, i.e., G does not have a hereditary property. Hence, in this paper, we first derive a necessary and sufficient condition for H to admit a rectangular floorplan RFP 2 ( n ) . Further, if H admits an RFP, we present a linear time transformation algorithm for deriving RFP 2 ( n ) from RFP 1 ( n ) .