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Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses., To be presented 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018); Torino, Italy; October 2018

This paper reports the use of Laser-induced Forward Transfer (LIFT) technology for printing of multilayer flexible circuitries and the fabrication of micro-bumps for flip-chip bonding of packaged LEDs and bare die microcomponents. Bonding of passive and functional surface mount devices (SMD) on low-temperature polyethylene terephthalate (PET) foils have been demonstrated using two selective bonding techniques. Firstly, using a high intensity near-infrared (NIR) lamp, a bare die NFC chip was bonded on micro-bumps formed with LIFT printed isotropic conductive adhesive (ICA) within less than a minute. Secondly, using a high intensity Xenon lamp, passive components and packaged LEDs were bonded within 5 seconds on microbumps formed with conventional Sn-Ag-Cu (SAC) lead-free alloys. In the both cases, due to selective light absorption, a limited temperature increase was observed in the PET substrates allowing successful bonding of components onto the delicate polyethylene foil substrates using conventional interconnect materials. © 2018 IEEE.

In this case study, we investigated the minimum line width and spacing for roll-to-roll (R2R) screen printed silver interconnections on polyethylene terephthalate (PET). This initial pilot investigation involved rotary screen printing 16 high density I/0 patterns while alternating pitch (150, 175, 200, and 250 µm) and nominal screen linewidth (50, 75, 100, 150 µm). Based on those results, we chose the Asahi silver nanoparticle ink and StorkS305 screen to compare three printed chip bonding test patterns utilizing a nominal line width of 75 µm (average printed line width was 115 µm), and a pitch of 150, 175 or 200 µm. Flip chip bonding of daisy chain bare dies was used to compare the effect of gold stud bumping and the choice of anisotropic conductive adhesive (ACA). Even though gold stud bumps ensured reliable connections, the choice of the ACA for unbumped chips proved uncertain, which has provoked ongoing and future investigations.The results of this study shed significant and valuable light on high throughput R2R fabricated hybrid systems and necessary steps to be considered for future high density rotary screen printed hybrid electronic applications.

In this work, low thermal-mass LEDs (LTM-LEDs) were developed and demonstrated in flip-chip configuration, studying both experimentally and theoretically the enhanced electrical and optical characteristics and the limits. LTM-LED chips in 25 × 25 μm2, 50 × 50 μm2, 100 × 100 μm2 and 200 × 200 μm2 mesa sizes were fabricated and comparatively investigated. Here it was revealed that both the electrical and optical properties are improved by the decreasing chip size due to the reduced thermal mass. With a smaller chip size (from 200 μm to 50 μm), the device generally presents higher current density against the bias and higher power density against the current density. However, the 25 × 25 μm2 device behaves differently, limited by the fabrication margin limit of 10 μm. The underneath mechanisms of these observations are uncovered, and furthermore, based on the device model, it is proven that for a specific flip-chip fabrication process, the ideal size for LTM-LEDs with optimal power density performance can be identified. ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version

An application-oriented integration concept for a half-bridge switch assembly has been developed based on the latest generation 70- ?m-thin insulated gate bipolar transistors and diodes, which are rated at 600 V/200 A. This paper addresses the design and reliability of the assembly, with a fully bondwireless approach using cylindrical copper bumps. Advanced numerical structural simulation techniques are also applied to assess the influence of interconnect characteristics (material, size, and shape) and try to determine an optimum solution for reducing the stress and creep strain development in the solder joint. Preliminary experimental tests of the power module are also carried out at different switching frequency and loads to prove the validity of the proposed solution in terms of electromagnetic performance.

Purpose - Out-of-plane displacement (warpage) is one of the major thermomechanical reliability concerns for board-level electronic packaging. The warpage and residual stresses can cause unreliability in the performance of electronic chip. An accurate estimation of the distortion and the residual stresses will help in selecting right combination of material for soldering and to determine the better assembly procedure of the chip. The purpose of this paper is to create a 3D nonlinear finite element model to predict the warpage, bending stresses, shear and peel stresses in a flip-chip on board (FCOB). Design/methodology/approach - A 3D finite element procedure has been developed considering the material nonlinearity during solidification for a FCOB assembly. Finite element results have been compared with the experimental values. Findings - The present finite element method gives better approximation of residual warpage and stresses compared to analytical models available in the literature. Originality/value - The 3D finite element approach considering the elasto-plastic and temperature-dependent material properties has not been attempted by any authors. Experiments have been conducted for the comparison of finite element values. The finite element results compare better than the methods available in the literature. Hence a better method for estimating the deformation and residual stresses in flip-chip assembly has been suggested. � Emerald Group Publishing Limited.

This paper presents the first volumetric images obtained using a 2D CMUT array with through-wafer via interconnects. An 8×16-element portion of a 32×64-element array flip-chip bonded onto a glass fanout chip was used in the experiments. This study experimentally demonstrates that 2D CMUT arrays can be fabricated with high yield using silicon micromachining processes, individual electrical connections can be provided using through-wafer interconnects, and the flip-chip bonding technique can be used to integrate the dense 2D arrays with electronic circuits for practical imaging applications. Publisher's Version

Manuscript received December 17, 2002; accepted May 30, 2003. This work was supported by the United States Office of Naval Research and CBYON, Inc. Recently, capacitive micromachined ultrasonic transducers (CMUTs) have emerged as a candidate to overcome the difficulties in the realization of 2-D arrays for real-time 3-D imaging. In this paper, we present the first volumetric images obtained using a 2-D CMUT array. We have fabricated a 128 x 128-element 2-D CMUT array with through-wafer via interconnects and a 420-mum element pitch. As an experimental prototype, a 32 x 64-element portion of the 128 X 128-element array was diced and flip-chip bonded onto a glass fanout chip. This chip provides individual leads from a central 16 X 16-element portion of the array to surrounding bondpads. An 8 x 16-element poition of the array was used in the experiments along with a 128-channel data acquisition system. For imaging phantoms, we used a 2.37-mm diameter steel sphere located 10 mm from the array center and two 12-mm-thick Plexiglas plates located 20 mm and 60 mm from the array. A 4 X 4 group of elements in the middle of the 8 X 16-element array was used in transmit, and the remaining elements were used to receive the echo signals. The echo signal obtained from the spherical target presented a frequency spectrum centered at 4.37 MHz with a 100% fractional bandwidth, whereas the frequency spectrum for the echo signal from the parallel plate phantom was centered at 3.44 MHz with a 91% fractional bandwidth. The images were reconstructed by using RF beamforming and synthetic phased array approaches and visualized by surface rendering and multiplanar slicing techniques. The image of the spherical target has been used to approximate the point spread function of the system and is compared with theoretical expectations. This study experimentally demonstrates that 2-D CMUT arrays can be fabricated with high yield using silicon IC-fabrication processes, individual electrical connections can be provided using through-wafer vias, and flip-chip bonding can be used to integrate these dense 2-D arrays with electronic circuits for practical 3-D imaging applications. United States Office of Naval Research Publisher's Version Q2 WOS:000187162500021 PubMed ID: 14682642

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.

The suppression of the critical current in YBCO Josephson junctions by the Earth's magnetic field strongly affects the operation of SQUIDs outside magnetic shielding. Commonly, one observes a modulation of the SQUID flux-voltage transfer function amplitude, V/sub sq-pp/, with a period of /spl Delta/B/sub 0-v/ leading to an increased white flux noise level or unstable SQUID operation. Here, we report on the investigation of /spl Delta/B/sub 0-v/ of rf-SQUID sensors based on step edge junctions (SEJ) operated in a flip chip configuration with coplanar resonators with integrated flux concentrators. To investigate the origin of the suppression of V/sub sq-pp/, we opened the SQUID loop of some samples and measured the magnetic field dependence of the critical current I/sub c/(B) directly and compared it to V/sub sq-pp/(B). It is shown that a junction width in the submicrometer scale is required for operation of the sensors in the Earth's magnetic field.

We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator. A chip holder with a via hole is used to coat the photoresist for indium bump lift-off. The 1000 μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500 μm, which ensures the integrity of the indium bump array. 64 × 64 indium arrays with 20 μm-high, 30 μm-diameter bumps are successfully formed on a 5 × 6.5 mm2 CMOS chip. © 2011 Chinese Institute of Electronics.