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Modern Internet of Things (IoT) devices are becoming increasingly complex, often incorporating a range of different components (sensors/processing/memory/logic) fabricated using a variety of process technologies. To integrate these disparate elements in a low-cost, small and power-efficient way, research has looked to '3D integration' where several tiers are stacked and interconnected vertically within a single chip. Most research into 3D integration assumes the use of Through Silicon Vias (TSVs) to interconnect stacked tiers; however, TSVs are presently expensive to manufacture and only available in leading-edge process nodes, making them poorly suited to cost-sensitive IoT applications. In this thesis, wireless Inductive Coupling Links (ICLs) are investigated as an alternative to TSVs for vertical communication (and power delivery) within a 3D-IC. The motivation for focusing on wireless links is primarily cost-driven, as ICLs do not require 3D-specific fabrication processes and can facilitate simple pick-and-place assembly using only adhesive. Specifically, this work explores the design challenges associated with such ICLs, aiming to establish a standard interface that can be used for IoT-style 3D stacking applications. The key novel contributions include: (i) A low-energy ICL transceiver that uses timedomain encoding to reduce the number of transmit pulses, and hence overall energy, by over 13% when compared to existing solutions. (ii) A CAD tool for automated ICL inductor optimisation that significantly reduces the design time (by over 6 orders-of-magnitude) when compared with finite element tools, whilst maintaining an average accuracy within 7.8%. (iii) A near-field wireless clock link for many-tier clock synchronisation that achieves low-skew clock distribution across a wide range of frequencies (results show less than 61ps of clock skew across five tiers when operating between 50MHz and 2.3GHz). (iv) A hybrid ICL transceiver for concurrent wireless data and power transmission. The proposed transceiver can achieve wireless power transfer of up-to 2.0mW/link whilst simultaneously transferring 1.4Gbps of data using a BPSK scheme. These four contributions are also validated through two 3D-stacked silicon test-chip demonstrators, the first fabricated in 0.35 µm CMOS technology (showcasing the low-energy ICL transceiver), and the second fabricated in 65nm CMOS technology (showcasing wireless data, power and clock transmission as part of a 3D stacked Arm Cortex M0 SoC). Overall, this work represents an exciting step towards a new era in VLSI where IC designers can 'pick-and-mix' the functional circuit blocks and technologies within a given chip (in the form of separate semiconductor dies) and stack them together in a low-cost way using ICLs.