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Through a single optical interface, a $250\ \mu m$ pitch two-dimensional $2\times 8$ -channel optical transceiver is integrated on a lithographically patterned silicon interposer, offering 200 Gb/s data input and output duplex within an area of $6\ mm\times 6\ mm$ .

In this paper, based on a wet etched silicon interposer, we propose a 2.5D assembly of two dimensional optical transceivers for 400 Gbps parallel optical interconnections. In this opto-electronic packaging, two dimensional optical matrix is formed as 250 μm in both the x -and y-directions by exploiting commercial opto-electronic arrays, and a compact optical interface is used to couple the light channels with fiber ribbons. Each quadrant of the optical matrix is connected with its CMOS IC part via impedance matched co-planner wave guides. The shortest traces between optics and CMOS ICs can be 300 μm, benefiting from flip-chip technology. The process flow of silicon interposer fabrication is illustrated. With flip-chip bonding, 25 Gbps 2D 16-channel receiver is assembled on the silicon interposer, and the sub-module, including the optical interface, is scaled down to 4 mm by 6 mm. In addition, the performance of this assembled module is fully characterized. Uniform and clear eye patterns are captured for all of the channels. Receiver sensitivities are also tested for all channels at 25.78 Gbps, 2 31-1 PRBS, with the variation less than 1.5 dB at error free operation.

We demonstrate a wafer-scale process for making compact 3D stacked 10×10 Gbps transmitter chips. Error-free operation is obtained for 0 and 500 meter transmission in OM4-Plus fiber with a maximum 1.4 dB Rx sensitivity penalty.