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Nowadays, silicon-based fin field-effect transistor (FinFET) devices have become the top choice for integrated circuit designers because they can handle the majority of application scenarios. In this article, the authors propose applying deep learning models to predict the electrical characteristics of devices using their structural parameters, aiming to solve the problems of complexity, time consumption, and convergence difficulty in traditional simulations. The authors first determine the electrical characteristics of simulations on FinFET devices using technology computer-aided design (TCAD). Different deep learning models were constructed in this study to predict various electrical parameters and characteristics of integrated circuit devices based on different datasets and prediction tasks, and high levels of accuracy were achieved. For instance, the average normalized mean square error of the predicted electrical parameters of FinFET devices based on TCAD simulation was less than 1.4 × 10−5, while the average relative errors of the predicted DC and AC characteristics of FinFET devices based on Berkeley short-channel insulated gate FET model (BSIM) simulation were 7.12 × 10−3 and 4.8 × 10−3, respectively. These results demonstrate that the proposed deep learning models can effectively predict the electrical parameters and characteristics of integrated circuit devices, providing strong support for device design and optimization. [ABSTRACT FROM AUTHOR]

In this study, we have proposed the utilization of machine learning techniques to predict the I–V characteristics and transconductance curve of a multichannel junctionless FinFET design. Various machine learning models were employed to predict the current–voltage (I–V) and transconductance (gm) curve by training the models with data generated from Technology Computer Aided Design (TCAD) simulations for the 3D multichannel junctionless FinFET. Specifically, three different machine learning models were constructed using the random forest (RF), linear regression (LR), and decision tree regression (DTR) algorithms. These models aimed to uncover hidden relationships and establish correlations between different physical parameters. This approach offers valuable insights into extracting several short channel effects parameters, such as threshold voltage (Vth), on-state current (Ion), off-state current (Ioff), and subthreshold swing, from the trained dataset. The results indicate that both the random forest and decision tree regression models achieved a similar level of accuracy in predicting the IDS–VGS and gm curves when compared to the TCAD simulations for the proposed device structure. The RF, LR, and DTR models were evaluated using metrics such as root mean squared error (RMSE) and error rate. The RF-ML and DTR-ML models exhibited 99% accuracy with an error rate below 1%, even when trained with only 20% of the dataset (i.e., 255 training samples). This work primarily aims to demonstrate the integration of machine learning techniques with device simulation tools to advance technology for new device development. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 12-transistor SRAM cell capable of operating at near-threshold voltage in FinFET technology. This cell employs Schmitt trigger-based inverters and feedback cut write assist technique to improve performance properties. The simulations have been done through HSPICE using 10 nm FinFET technology at a supply voltage of 0.45 V and a temperature of 25°C under 5000 Monte Carlo tests. The proposed cell improves the read static noise margin by at least 1.01 times. The write static noise margin is also increased by at least 1.07. The proposed single-ended cell leads to a reduction of $ {\alpha _{BL}} $ αBL by 50% and offers low dynamic write power. The leakage power is also reduced by 1.03 times due to the use of single bitline in the cell structure, stack transistors in the write path and elimination of leakage in the read path. [ABSTRACT FROM AUTHOR]

In this paper, a deep learning-based device modeling framework for design-technology co-optimization (DTCO) is proposed. A ResNet surrogate model is utilized as an alternative to traditional compact models, demonstrating high accuracy in both single-task (I–V or C–V) and multi-task (I–V and C–V) device modeling. Moreover, transfer learning is applied to the ResNet model, using the BSIM-CMG compact model for a 12 nm FinFET SPICE model as the pre-trained source. Through this approach, superior modeling accuracy and faster training speed are achieved compared to a ResNet surrogate model initialized with random weights, thereby meeting the rapid and efficient demands of the DTCO process. The effectiveness of the ResNet surrogate model in circuit simulation for 12 nm FinFET devices is demonstrated. [ABSTRACT FROM AUTHOR]

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively. [ABSTRACT FROM AUTHOR]

Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transistor (SE10T) SRAM cell with high stabilities. It utilises a stacked pull-down structure for hold/read stability improvement and leakage power reduction, a feedback-cutting mechanism for writability enhancement, and single-ended read/write structures for dynamic power reduction. Also, using a single-transistor reading path with eliminated read bitline leakage enhances ON-to-OFF currents (ION/IOFF) ratio. The proposed design is compared with the conventional 6T, Schmitt-trigger 10T (ST10T), differential writing 10T (DW10T), data-independent read port 10T (DIRP10T), transmission gate read-decoupled 9T (TGRD9T), and feedback-cutting 11T (FC11T) SRAM cells based on 7-nm Fin-shaped Field-Effect Transistor (FinFET) technology at VDD = 0.4 V. The proposed design shows at least 1.04×/1.01×/1.12×/1.25×/1.15× improvement in read stability/writability/read delay/leakage power/dynamic power. Moreover, it shows at least 1.22× improvement in ION/IOFF ratio and offers the lowest minimum operating voltage (0.292 V). However, it offers a 1.02× lower hold stability than that of ST10T, a 1.18×/1.14×/1.13× higher write delay compared to 6T/ST10T/DW10T, and a 1.56×/1.07×/1.05× higher layout area occupation in comparison with 6T/TGRD9T/DIRP10T. Therefore, the proposed SRAM cell can be an optimum candidate for usage in smartwatches. [ABSTRACT FROM AUTHOR]

This paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology. FinFET technology is a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology to avoid the problems caused by the decrease in transistor size as the technology evolves. In addition to the manufacturing process being similar to CMOS technology, FinFET technology offers many advantages, such as reduced short channel effects, higher drain current, reduced static leakage current, faster switching time, lower supply voltage, lower power consumption, and higher efficiency. The VDBA active circuit block, which has high input impedance and low output impedance, is preferred for high-frequency and high-bandwidth applications. It is advantageous to design active filter circuits using VDBA because of its superior features, such as lower power consumption, higher bandwidth, wider range linearity, and the ability to implement the proposed circuits without external resistors. In this study, FinFET-based VDBA and filter application are simulated with the Spice simulation programme using 32 nm PTM technology parameters. Simulation results using 32 nm FinFET technology are compared with those using 0.18 µm TSMC technology. It is concluded that 32 nm FinFET technology reduces power consumption by 98.8 % and increases bandwidth by 145 times. The successful results show that FinFET technology is superior to CMOS technology in analogue circuit design. FinFET-based VDBA circuits and filters will be more advantageous in the design of signal processing and biomedical applications.

A novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique. [ABSTRACT FROM AUTHOR]

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7 nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation σ / μ (%) for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation σ / μ (%) for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry's production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies. [ABSTRACT FROM AUTHOR]

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS2 layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS2, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT's advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit. [ABSTRACT FROM AUTHOR]

This paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology. FinFET technology is a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology to avoid the problems caused by the decrease in transistor size as the technology evolves. In addition to the manufacturing process being similar to CMOS technology, FinFET technology offers many advantages, such as reduced short channel effects, higher drain current, reduced static leakage current, faster switching time, lower supply voltage, lower power consumption, and higher efficiency. The VDBA active circuit block, which has high input impedance and low output impedance, is preferred for high-frequency and highbandwidth applications. It is advantageous to design active filter circuits using VDBA because of its superior features, such as lower power consumption, higher bandwidth, wider range linearity, and the ability to implement the proposed circuits without external resistors. In this study, FinFET-based VDBA and filter application are simulated with the Spice simulation programme using 32 nm PTM technology parameters. Simulation results using 32 nm FinFET technology are compared with those using 0.18 μm TSMC technology. It is concluded that 32 nm FinFET technology reduces power consumption by 98.8 % and increases bandwidth by 145 times. The successful results show that FinFET technology is superior to CMOS technology in analogue circuit design. FinFET-based VDBA circuits and filters will be more advantageous in the design of signal processing and biomedical applications. [ABSTRACT FROM AUTHOR]

Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a "self-tanked" fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time. [ABSTRACT FROM AUTHOR]

The innovation of 3D FinFETs using top‐down silicon nanofins represents a significant advancement toward scaling down microchip process nodes to the cutting‐edge 3‐nm level. While bottom‐up semiconductor nanofins also hold promise as building blocks for FinFETs, their controlled growth remains challenging. Drawing inspiration from the guided roots along brick gaps, this study shows that the aligned atomic terraces on an annealed miscut LaAlO3 surface can trigger an exceptional graphoepitaxial effect, encouraging the bottom‐up vapor‐phase growth of self‐aligned nanostructures such as CdS, CdSe, ZnSe, and ZnTe. Subsequently, the resultant CdS nanofins, characterized by narrow widths of ≈20 nm and large height‐to‐width ratios exceeding 16, can be seamlessly assembled into arrayed FinFETs on the insulating LaAlO3 substrate, obviating the need for post‐growth alignment steps. Unlike most nanostructure‐based planar transistors, which often operate in depletion mode characterized by negative thresholds, these FinFETs operate in enhancement mode with positive thresholds (≈5 V), ≈10−14‐A standby currents, and ≈108 on/off current ratios. The achieved ratio surpasses the record for planar enhancement‐mode CdS transistors by 4 orders of magnitude, primarily due to the enhanced electrostatic control over the nanofins. Overall, the graphoepitaxially side‐by‐side nanofins show tremendous potential to expand the repertoire of FinFETs based on non‐silicon semiconductors. [ABSTRACT FROM AUTHOR]

SRAMs, the go-to choice for system-on-chips nowadays, suffer from high power consumption and unstable behavior in nanoscale CMOS technology. Consequently, we observe the emergence of troublesome short-channel effects (SCEs), necessitating the utilization of innovative nano-devices. Combining its attractive features, including reduced SCEs and leakage, the fin-shaped field-effect transistor (FinFET) shines as a skillful replacement for CMOS, skillfully tackling those injurious problems. This paper presents a near-threshold single-bitline 9T (SB9T) SRAM cell, with a primary focus on enhancing stability and energy efficiency. The SB9T SRAM cell integrates a read-assist scheme and a feedback-cutting technique to enhance read stability and writability. By conducting simulations utilizing a 7-nm FinFET technology and operating at a voltage of 0.5 V, the SB9T SRAM cell demonstrates remarkable performance advantages when compared to existing designs. Specifically, in comparison to the conventional 6T cell, the SB9T SRAM cell achieves an improvement of 1.86 × in read stability and 2.41 × in writability. Additionally, the SB9T SRAM cell minimizes power dissipation from leakage by at least 8.73% and enhances write energy efficiency by a minimum of 4.84%. It should be noted that although the SB9T SRAM cell consumes 1.03 × more read energy than the conventional 8T cell, it still surpasses alternative designs by reducing read energy consumption by at least 4.86%. [ABSTRACT FROM AUTHOR]

The increased short-channel effects in the ultra-nanoscale regime limit the operation of complementary metal oxide semiconductor (CMOS) technology. To combat the issues in the ultra-nanoscale regime, fin-shaped field effect transistor (FinFET) technology is the best choice because of its numerous advantages over CMOS technology. FinFET enhances the further scaling of the devices and control over the channel. Therefore, this research paper presents the implementation of a low leakage 4:2 compressor in FinFET technology. A compressor is a general block, especially used in multiplier units and hence in digital signal processing (DSP) systems. The design of the low power compressor improves the overall efficiency of the DSP systems. An extensive study of the proposed low power 4:2 compressor at 7 nm technology node is done in the paper. Mentor Graphics tools are used for the circuit simulations and analyzes. The key parameters, such as leakage power, delay, power delay product (PDP), and the process voltage temperature (PVT) variations, are estimated for the performance evaluation. The proposed 4:2 compressor saves 87.33% of leakage power and is 75.90% more energy efficient compared to its conventional counterpart. [ABSTRACT FROM AUTHOR]

The recent shift in the VLSI industry from conventional MOSFET to FinFET for designing contemporary chip-multiprocessor (CMP) has noticeably improved hardware platforms' computing capabilities, but at the cost of several thermal issues. Unlike the conventional MOSFET, FinFET devices experience a significant increase in circuit speed at a higher temperature, called temperature effect inversion (TEI), but higher temperature can also curtail the circuit lifetime due to self-heating effects (SHEs). These fundamental thermal properties of FinFET introduced a new challenge for scheduling time-critical tasks on FinFET-based multicores that how to exploit TEI towards improving performance while combating SHEs. In this work, TREAFET, a temperature-aware real-time scheduler, attempts to exploit the TEI feature of FinFET-based multicores in a time-critical computing paradigm. At first, the overall progress of individual tasks is monitored, tasks are allocated to the cores, and finally, a schedule is prepared. By considering the thermal profiles of the individual tasks and the current thermal status of the cores, hot tasks are assigned to the cold cores and vice-versa. Finally, the performance and temperature are balanced on-the-fly by incorporating a prudential voltage scaling towards exploiting TEI while guaranteeing the deadline and thermal safety. Moreover, TREAFET stimulates the average runtime frequency by employing an opportunistic energy-adaptive voltage spiking mechanism, in which energy saving during memory stalls at the cores is traded off during the time slice having the spiked voltage. Simulation results claim TREAFET maintains a safe and stable thermal status (peak temperature below 80 °C) and improves frequency up to 17% over the assigned value, which ensures legitimate time-critical performance for a variety of workloads while surpassing a state-of-the-art technique. The stimulated frequency in TREAFET also finishes the tasks early, thus providing opportunities to save energy by power gating the cores, and achieves a 24% energy delay product (EDP) gain on average. [ABSTRACT FROM AUTHOR]

Non-invasive side-channel attacks (SCAs) based on leakage power analysis (LPA) have received more attention recently, since leakage current has gradually become more dominant with further scaled technologies. For SRAM cells, LPA exploits the correlation between data in memory cells and their corresponding leakage power. This paper proposes a novel SRAM design in 7 nm node for countering LPA attacks, based on a single-ended PMOS-reading 9T (nine-transistor) cell design. The leakage current imbalance, delay, stability, and robustness of SRAM cells are examined for the proposed memory cell architecture with layout designs, and results are compared against other SRAM cell designs. Simulation results and failure of LPA attacks in case studies confirm the enhanced resilient behavior for the new SRAM cell design. [ABSTRACT FROM AUTHOR]

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In this paper, the junctionless Fin Field Effect Transistor (FinFET) and nanosheet Field Effect Transistor (NSFET) with a gate length of 12 nm are implemented using the Sentaurus Technology Computer-Aided Design (TCAD) tool. To compare the junctionless FinFET and NSFET, simulations are done at constant threshold voltage. The NSFET outperformed FinFET in terms of current driving capabilities, Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), and intrinsic voltage gain (AV). Further, the device design guidelines are presented for FinFET and NSFET in terms of geometrical parameters. The simulation indicates that downscaling the gate length from 16 to 8 nm leads to an increase in SS and DIBL by 21 and 68.49 % in FinFET whereas 19 and 70.14 % in nanosheet FET. The height variation of FinFET seems to make the least impact on short channel effects (SCEs) while scaling the thickness of NSFET from 9 to 5 nm improves the DIBL and SS by 61.9 % and 15.54 % respectively. In the case of scaling the width of FinFET from 10 to 5 nm, DIBL and SS increase by 55.4 % and 14 % whereas scaling of nanosheet width from 24 to 12 nm gives 19.44 % and 1.37 % improvement in DIBL and SS, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes High-k SOI GaN FinFET which is a potential candidate for more efficient and high-performance electronic devices attributable to high carrier mobility and high breakdown voltage of GaN. Further, optimization of fin aspect ratio of High-k SOI GaN FinFET is done, keeping conducting channel area constant for enhanced linear and intermodulation distortion performance. The better linearity and intermodulation distortion parameters are essential for optimized and efficient performance of the device in RF/wireless applications. This paper presents three different configurations for High-k SOI GaN FinFET that are C1, C2 and C3 with fin aspect ratio of 1.67, 2.4, 3.75 respectively, having the same conducting channel area to optimize the linear and intermodulation distortion performance for RF/wireless applications. The investigation has been focused on the linearity and intermodulation distortion performance through exploration of 1-dB compression point, Voltage Intercept Points (VIP2 & VIP3), IIP3, IMD3, second & third Harmonic Distortion (HD2, HD3), etc. for all the three configurations. The results conclude that decrease in fin aspect ratio reduces the distortion and improves the linearity of the device for RF applications. Cut-off frequency (fT) and maximum oscillation frequency (fmax) are also calculated for C1, C2 and C3. C1 configuration has highest fT and fmax which makes it suitable for RF applications. By these findings, it would be helpful to design 3-D devices that can be used in wireless communication system, electric vehicles, Internet of Things (IoT) devices and power electronics. [ABSTRACT FROM AUTHOR]

With feature size scaling down, the effect of single event transient (SET) on the reliability of circuits is necessary to be considered. The bipolar amplification effect plays a key role in the charge collection of SET of nano-meter FinFET devices. It is important taking into account the bipolar amplification to calculate deposited charge, which is always obtained by a linear model dependency on linear energy transfer (LET) and silicon film thickness. Based on radiation-induced generation rate model and genetic arithmetic, an accurate analytical for the deposited charge of SET in FinFET is proposed. The effects of LET, volume of particle hit, characteristic radius and decay time of Gaussian function on the deposited charge are analyzed by the proposed model. The dependence of the device structure on the deposited charge is also discussed by the model. The results indicate that the presented model agrees with TCAD well. Compared with TCAD, the proposed model has an average relative error 0.002% while the linear model has an average relative error 50.5% for LET ranging from 3 to 110 MeV·cm2/mg. Due to large sensitive volume of the particle hit in source and drain areas, the deposited charge has two maxima in source and drain areas and a minimum round the gate-drain junction of fin. The deposited charge increases with the characteristic radius and decay time decrease and the relative error between TCAD and the proposed model represent a reduction trend. [ABSTRACT FROM AUTHOR]

In the current nanoscale regime, fin field effect transistor (FinFET) technology overcomes the limitations of metal oxide semiconductor field effect transistor (MOSFET) technology. Robust and low-power static random access memory (SRAM) design is a demanding task for memory designers, especially in the nanoscale regime. Therefore, this paper proposes a 10 transistor (10T)-based SRAM cell design using low-power FinFET technology. The proposed approach not only reduces the leakage current, but also improves cell stability in different states. The proposed SRAM cell is simulated and analyzed at a 10 nm technology node using a multi-gate predictive technology model (PTM) for the transistors with a power supply of 0.7 V. The comparison analysis is also presented with the existing designs. The read and write static noise margins, and SRAM electrical quantity matrix (SEQM) of the proposed SRAM cell are improved by 3.54×, 1.71× and 26.41×, respectively, compared with the conventional 6T (C6T) design. The reliability investigations and comparison of the proposed SRAM cell have been carried out using Monte Carlo simulations with ± 1 0 % deviations in the process parameters. The reliability analysis shows that the proposed SRAM cell is less sensitive to process variations. [ABSTRACT FROM AUTHOR]

Purpose: In radiology, several medical imaging modalities were used. In recent Biomedical systems, integrated circuits were used in the form of Application Specific Integrated Circuits (ASICs) to perform FFT. The raw data obtained from the acquiring equipment are reconstructed to image using Fast Fourier Transform (FFT). The contribution in the paper is to design an FFT integrated unit for converting the Magnetic Resonance (MR) signal into frequency spectrum of each phase encoding. Materials and Methods: The image created is been transformed from the spatial projection using inverse Fourier transform. The k-space FFT information were back projected to obtain the MRI image. This paper presents an integrated circuit implementation of FFT processing elements used in Magnetic Resonance Imaging (MRI) reconstruction and ultrasonic imaging. The circuits designed in this work is to be used in the back-projection unit of MRI reconstruction. The complex periodic signal received from the receiver coils in MRI or piezoelectric disc in ultrasound and detector array in CT are analyzed using Fourier transform. The proposed single-path delay feedback (SDF) Decimation In Frequency (DIF) 4096-point FFT for image reconstruction was implemented in 65nm FPGA kit and programmed using VHDL in Quartus tool. Results: This block becomes the part of the reconstruction unit of MRI image. The proposed design reduces the execution of instruction per cycle and the fixed point arithmetic provides low roundoff error. Conclusions: Since in MRI reconstruction the frequency encoding and phase encoding is combined to develop the images the proposed FFT will be useful. In Future application specific integrated circuits will be designed for the entire MRI back projection and reconstruction unit. [ABSTRACT FROM AUTHOR]

In this paper we present an extended analysis of thsse impact of SiGe p-epi source/drain engineering on sub-20 nm gate length p-FinFETs performance for the N7 technology node. Different Ge concentrations and profiles (graded versus non-graded) are evaluated making use of properly calibrated drift-diffusion TCAD simulations. Calibration of simulations is based on advanced metrology and on Monte-Carlo simulations such that the resulting simulated ID-VG (in LIN and SAT regimes) matches the one measured on device. The calibrated TCAD simulator is then used to understand the limited performances of the device and to propose new source/drain epi architectures with graded and increased Ge content. A new p-FinFET design is fabricated and tested, confirming a boost in ON-current and a reduction of the parasitic resistance. Prospective TCAD work is also presented suggesting possible future improvements on p-epi source/drain and on local interconnect contacts. [ABSTRACT FROM AUTHOR]

The effective potential approach was successfully incorporated as a quantum correction to a Monte Carlo device simulator of n-FinFETs to take into account the electron quantum confinement. The electron line density calculated by the effective potential approach agrees very well with the one calculated by a 2D Schrödinger–Poisson solver. Next, the results for the drain current as a function of the gate and drain voltage obtained by the semiclassical and by the quantum-corrected Monte Carlo device simulator were compared. The quantum-corrected Monte Carlo device simulator properly models volume inversion, which reduces the impact of surface roughness scattering, thus improving the electron drift velocity. Additionally, the quantum correction allows the modeling of the reduction of electron density in the n-FinFETs channel due to the quantum-mechanical size quantization effect. This, in turn, leads to a reduction of the drain current. [ABSTRACT FROM AUTHOR]

The principal design concern in today's very large-scale integration (VLSI) industry is power dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation places a bottleneck in scaling down the dimensions and supply voltage of metal oxide semiconductor field effect transistor (MOSFET). Short channel effects (SCEs) put a limit on MOSFET scaling. At the lower technology nodes, the control of the gate over the channel is lost in MOSFET. Fin-shaped field effect transistor (FinFETs) uses multiple gates to gain much electrostatic control over the channel. FinFET not only improves the drive current but also reduces the subthreshold leakage. This paper proposes a novel power-efficient technique for the nanoscale regime. The simulation results are derived using Mentor Graphics at a 16 nm node. The power is reduced by 91.45% and 89.01% in the proposed MOSFET and FinFET-based inverter, respectively. A chain of 5-inverters is designed as a benchmark circuit to check the performance comparisons. In the proposed MOSFET and FinFET-based benchmark circuit, there is a power delay product (PDP) reduction of 80.28%, and 99.87%, respectively. The effect of process voltage and temperature (PVT) variations for the robustness of the technique is also discussed. The proposed technique provides the power-efficient and robustness operation against the variations as compared to the other methods. [ABSTRACT FROM AUTHOR]

Hybrid room-temperature (RT) silicon single-electron – field effect transistors (SET-FETs) provide a means to switch between ‘classical’, high current FET, and low-power SET operation, using a gate voltage. While operating as a SET, charge on a silicon quantum dot (QD) within the current channel, can be controlled at the one-electron level using the Coulomb blockade effect. This paper investigates nanofabrication methods for sub-10 nm ‘fin’ channel hybrid RT SET-FETs, and their influence on the energy band diagram, and formation of tunnel barriers and QDs, along the channel. Devices are fabricated in heavily n-doped SOI material using electron beam lithography, with thermal oxidation to reduce the as-defined fin width. Effective channel dimensions, following oxidation and excluding Si/SiO2 interface dopant deactivation, are ∼2.4 nm × 32 nm × 20 nm. Dopant disorder, fin width variation at the nanometre scale, and quantum confinement effects are considered as mechanisms for the formation of tunnel barriers and QDs, with dopant disorder the most likely reason. Arrhenius plots of Ids vs. 1/T allow extraction of a potential barrier energy ∼0.2 eV along the fin channel. For 180devices fabricated on four chips, 37% show RT SET-FET operation, ∼3 times higher than the corresponding yield observed in previous work on point-contact silicon SETs.

In the present study, a new low-power and high-speed comparator circuit is designed in 65 nm fin field-effect transistor (FinFET) technology. Moreover, by properly using the capabilities of FinFET technology, the number of transistors is reduced, and subsequently, a smaller area is occupied. Replacing MOSFET transistors with FinFETs reduces the delay and power consumption of the circuit, so the overall performance is improved. The first innovation of the proposed design is that to reduce the size and power consumption, two transistors were removed and the back gates of two transistors were cross-coupled. The second innovation is the connection of back gates to other suitable points of the circuit that increase the speed of comparison. In this study, a supply voltage of 0.8 V is applied to the circuit to show that the proposed modifications with FinFET reduce the delay to 272 ps and power consumption to 6.7 µW.

Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.

RF array performance of stacked nanosheets, stacked nanowires, FinFETs, and TreeFETs are optimized using double-sided gate contact, contact over active-gate, and proposed hybrid layouts. For the double-sided gate contact, gate resistance increases with the increasing active region width to decrease the maximum oscillation frequency. The gate vias on the active region of contact over active-gate can reduce gate resistance by providing vertical paths for small-signal gate current. Combining the advantages of double-sided gate contact and contact over active-gate, the hybrid can further reduce the gate resistance to improve the maximum oscillation frequency. FinFETs/TreeFETs with the vertical sections of the channel (fin/interbridge) stop the lateral small-signal gate current path to increase gate resistance and thus decrease the maximum oscillation frequency as compared to nanosheets and nanowires. Nanowires adopting the hybrid layout and gate length of 18nm can achieve the highest maximum oscillation frequency of 590GHz due to the lowest gate resistance, the highest electron concentration, and the best gate control.

The performance of semiconductors has greatly improved due to the miniaturization of the transistor. To shrink the size of a transistor, the channel length must be decreased. Short-channel effects become noticeable as the gate length is reduced. Short-channel effects are observable at dimensions below 7 nm as a consequence of the shorter gate length. However, nanosheet structures have been proposed to replace FinFET and nanowire transistors at the 7 nm and 3 nm technological nodes. The purpose of this research is to construct an artificial neuron based on nanosheet transistors and evaluate its spiking behaviour and power consumption. We are building a regular Axon Hillock and our proposed neuron model using GPDK 45 nm and nanosheet transistor 20 nm technology. The simulation results clearly show that the nanosheet transistor consumes less power than the GPDK 45 nm transistors. Furthermore, we verified the validity of our suggested neuron model by performing Monte Carlo simulation, PVT analysis, AC response, noise response and layout. Additionally, the proposed neuron was tested with a variety of input currents, including pulse current, ramp current, sinusoidal current, and arbitrary current, and their associated spike patterns were recorded. According to our research, nanosheet-based Axon Hillock consumes 156 fW, and our proposed neuron consumes 1.9 pW of power.