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Abstract Phase Change Memory (PCM) is an emerging technology exploiting the rapid and reversible phase transition of certain chalcogenides to realize nanoscale memory elements. PCM devices are being explored as non-volatile storage-class memory and as computing elements for in-memory and neuromorphic computing. It is well-known that PCM exhibits several characteristics of a memristive device. In this work, based on the essential physical attributes of PCM devices, we exploit the concept of Dynamic Route Map (DRM) to capture the complex physics underlying these devices to describe them as memristive devices defined by a state—dependent Ohm’s law. The efficacy of the DRM has been proven by comparing numerical results with experimental data obtained on PCM devices.

Stanford memristor model is a widely used model that accurately characterizes real non-volatile metal-oxide resistive random access memory (RRAM) devices with bipolar switching characteristics. The paper studies for the first time the dynamics and bifurcations in a class of nonlinear oscillators with real non-volatile memristor devices obeying Stanford model. This is in contrast with papers in the literature considering oscillators with ideal, abstract, or artificial memristor models, that are unable to describe physical memristors implemented in nanotechnology. One main new idea in the paper is to use the memristor as a programmable nonlinear resistor. Namely, two principal modes of operation are considered. 1) Analogue transient phase: the oscillator is designed so that in the transient oscillations the voltage on the memristor is below threshold, hence the main memristor state variable, i.e., the gap of the insulating material, is almost constant and the memristor behaves as a static nonlinear resistor. 2) Programming phase: the nonlinear characteristic of the memristor, which depends on the gap, can be changed via the application of voltages above threshold. The paper studies nonlinear oscillations in the transient phase for a fixed gap as well as the bifurcations phenomena displayed when the gap is varied. The paper also discusses the differences between the approach in the paper and those to design other memristor oscillators with non-volatile memristors.

Multistability phenomena and complex nonlinear dynamics in memristor oscillators pave the way to obtain efficient solutions to optimization problems by means of novel computational architectures based on the interconnection of single–device oscillators. It is well-known that topological properties of interconnections permit to control synchronization and spatio–temporal patterns in oscillatory networks. When the interconnections can change in time with a given probability to connect two oscillators, the whole network acts as a complex network with blinking couplings. The work of has shown that a particular class of blinking complex networks are able to completely synchronize in a faster fashion with respect to other coupling strategies. This work focuses on the specific class of blinking complex networks made of Memristor–based Oscillatory Circuits (MOCs). By exploiting the recent Flux–Charge Analysis Method, we make clear that synchronization phenomena in blinking networks of memristor oscillators having stochastic couplings, i.e., Blinking Memristor Oscillatory Networks (BMONs), correspond to global periodic oscillations on invariant manifolds and the effect of a blinking link is to shift the nonlinear dynamics through the infinite (invariant) manifolds. Numerical simulations performed on MOCs prove that synchronization phenomena can be controlled just by changing the coupling amongst them.

Among the recent innovative technologies, memristor (memory-resistor) has attracted researchers attention as a fundamental computation element. It has been experimentally shown that memristive elements can emulate synaptic dynamics and are even capable of supporting spike timing dependent plasticity (STDP), an important adaptation rule that is gaining particular interest because of its simplicity and biological plausibility. The overall goal of this work is to provide a novel (theoretical) analog computing platform based on memristor devices and recurrent neural networks that exploits the memristor device physics to implement two variations of the backpropagation algorithm: recurrent backpropagation and equilibrium propagation. In the first learning technique, the use of memristor–based synaptic weights permits to propagate the error signals in the network by means of the nonlinear dynamics via an analog side network. This makes the processing non-digital and different from the current procedures. However, the necessity of a side analog network for the propagation of error derivatives makes this technique still highly biologically implausible. In order to solve this limitation, it is therefore proposed an alternative solution to the use of a side network by introducing a learning technique used for energy-based models: equilibrium propagation. Experimental results show that both approaches significantly outperform conventional architectures used for pattern reconstruction. Furthermore, due to the high suitability for VLSI implementation of the equilibrium propagation learning rule, additional results on the classification of the MNIST dataset are here reported.

This paper suggests an approach to generate pseudo-random sequences based on the discrete-time model of the simple memristive chaotic system. We show that implementing Euler’s and Runge–Kutta’s methods for the simulation solutions gives the possibility of obtaining chaotic sequences that maintain general properties of the original chaotic system. A preliminary criterion based on the binary sequence balance estimation is proposed and applied to separate any binary representation of the chaotic time sequences into random and non-random parts. This gives us the possibility to delete obviously non-random sequences prior to the post-processing. The investigations were performed for arithmetic with both fixed and floating points. In both cases, the obtained sequences successfully passed the NIST SP 800-22 statistical tests. The utilization of the unidirectional asymmetric coupling of chaotic systems without full synchronization between them was suggested to increase the performance of the chaotic pseudo-random number generator (CPRNG) and avoid identical sequences on different outputs of the coupled systems. The proposed CPRNG was also implemented and tested on FPGA using Euler’s method and fixed-point arithmetic for possible usage in different applications. The FPGA implementation of CPRNG supports a generation speed up to 1.2 Gbits/s for a clock frequency of 50 MHz. In addition, we presented an example of the application of CPRNG to symmetric image encryption, but nevertheless, one is suitable for the encryption of any binary source.