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The blood-brain-barrier (BBB) prevents that harmful substances in the blood enter the brain, and barrier disruption has been associated with a variety of central-nervous-system diseases. In vitro BBB models enable to recapitulate the BBB behavior in a controlled environment to investigate how the barrier reacts to stress events and external insults. Here, we present a human-cell-based BBB platform with integrated, transparent electrodes to monitor barrier tightness in real time at high spatiotemporal resolution. The BBB model includes human cerebral endothelial cells and primary human pericytes and astrocytes in a three-dimensional arrangement within a pump-free, open microfluidic platform. With our platform, we demonstrate that oxygen-glucose deprivation (OGD), which mimics the characteristics of an ischemic insult, induces a rapid remodeling of the cellular actin structures and subsequent morphological changes in the endothelial cells. High-resolution live imaging showed the formation of large actin stress-fiber bundles in the endothelial layer during OGD application, which ultimately led to cell shrinkage and barrier breakage. Simultaneous electrical measurements showed a rapid decrease of the barrier electrical resistance before the appearance of the stress fibers, which indicates that the barrier function is compromised already before the appearance of drastic morphological changes. The results demonstrate that our BBB platform recapitulates the main barrier functions in vitro and can be used to investigate the rapid reorganization of the BBB upon application of external stimuli.

This letter presents a mostly digital analog-to-digital converter implemented with voltage-controlled oscillators that can directly interface a capacitive MEMS microphone. The ADC is based on two ring oscillators and a coarse-fine counting circuitry. Coarse and fine counters are synchronized using a novel data scrambling technique to mitigate metastability and timing errors. This method enables a very low power consumption in the digital post-processing circuit. The proposed ADC, prototyped in 130-nm CMOS, achieves 73.8 dB-A of signal-to-noise and distortion ratio (SNDR) peak and 97 dB of dynamic range (DR) in a 20-kHz BW, while consuming 240 $\mu \text{W}$ from the 1.5-V/1.2-V power supplies. In a reduced power mode (8 kHz BW) with relaxed oscillation parameters, it reaches 66.4 dB-A of SNDR peak and 93 dB of DR with a power consumption of only 77 $\mu \text{W}$ .

This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma–delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the input signal frequency and the integrators gain. Unlike standard techniques, we do not rely on the feedback pulse properties, which enables a broader application of our technique to band-pass or VCO-based $\Sigma \Delta $ modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation.

This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma-delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the input signal frequency and the integrators gain. Unlike standard techniques, we do not rely on the feedback pulse properties, which enables a broader application of our technique to band-pass or VCO-based sigma-delta modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation.

This paper presents a compact-area, low-power, highly digital analog-to-digital converter (ADC) for audio applications. The proposed converter is implemented using only oscillators and digital circuitry, without operational amplifiers nor other highly linear circuits. The ADC consists of two twin second-order $\Sigma \Delta $ modulators, which can work both individually or in a pseudodifferential configuration. The proposed system has been implemented in a 0.13- $\mu \text{m}$ standard CMOS technology. The single-ended configuration occupies an active area of 0.02 mm2, is powered at 1.8 V with a current consumption of 155 $\mu \text{A}$ , and achieves an A-weighted dynamic range (DR) of 98 dB-A. The pseudodifferential configuration achieves 103 dB-A of A-weighted DR at the expense of doubling the area and power consumption.

Artículo de acceso abierto (OA), confirmado con el editor. En la plataforma consta como OA, pero el fichero del artículo tiene, erróneamente, copyright de IEEE. In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order Delta Sigma modulators. A first advantage of our approach is that it unveils systematic error components not described by the equivalence with a conventional Delta Sigma modulator. A second advantage is that, by a proper selection of the pulses generated by the PFM, we can theoretically construct an open loop VCO-ADC with an arbitrary noise shaping order. Unfortunately, with the exception of the first-order noise shaping case, the required pulse waveforms cannot easily be implemented on the circuit level. However, we describe circuit techniques to achieve a good approximation of the required pulse waveforms, which can easily be implemented by practical circuits. Finally, our approach enables a straightforward description of multistage Delta Sigma modulator architectures, which is an alternative and practically feasible way to realize a VCO-ADC with extended noise shaping. This work was supported in part by the UC3M Research Program of Carlos III University, Madrid, Spain, and in part by the CICYT Project TEC2014-56879-R, Spain. The work of P. Rombouts was supported by the Fund for Scientific Research Flanders (FWO-Vlaanderen), Belgium

This brief describes the architecture and implementation of a novel voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC). Instead of a ring oscillator, the VCO is built with a pulse frequency modulation architecture where an analog feedback loop ensures both oscillation and linearity of the voltage-to-frequency conversion. A multibit first-order noise-shaped output is achieved by sampling a digital delay line that acts as a part of the oscillator and as a multibit quantizer. A prototype has been implemented in a 40-nm CMOS process. Although most of the circuit elements are taken from a standard digital library, a transconductor is required as the input stage. To ensure proper linearity, a bulk-driven transconductor has been designed. The ADC measurements reach 53 dB of SNDR at 1 GHz sampling frequency in a 20-MHz bandwidth with a pseudo-differential architecture. Powered at 1.1 V, the power consumption is 3.5 mW. The active area is 0.08 mm 2 . The resulting figure-of-merit equals 242 fJ/step. This work was supported by the CICYT Projects, Spain, under Grant TEC2014-56879-R and Grant TEC2017-82653-R. This brief was recommended by Associate Editor S. Mirabbasi.

A new multistage 1-1 ΔΣ analogue-to-digital converter (ADC) architecture implemented only with voltage-controlled oscillators (VCOs) is introduced. A sturdy multistage noise-shaping (SMASH) configuration is used to avoid the need of either calibration circuitry or noise-cancellation filters. The digital nature of the VCO's output simplifies the implementation of the interconnection paths between stages, making unnecessary neither the use of multibit digital-to-analogue converters nor analogue subtraction elements. The basic operation of the architecture is shown at system level and the sensitivity to VCO's frequency mismatch is analysed. The proposed architecture has been validated through behavioural simulations. This work was supported by the CICYT project TEC2014-56879-R, Spain.

A theoretical approach to the problem of replicating continuous-time systems with frequency modulated oscillators is proposed. It has been shown that continuous time filters and especially, the loop filter of a sigma-delta modulator, can be implemented with VCOs and digital circuitry. The analysis of these architectures is usually based on the integral relationship between frequency and phase in an oscillator. However, the spectrum of a modulated oscillator contains components at the harmonics of the oscillation frequency that cannot be easily described using the phase-frequency relationship. We propose a model in which a VCO is considered a signal encoder instead of an integrator. This model is applied then to the design of a band pass-sigma delta modulator.

Capacitive or resistive sensors can be included in the feedback network of an oscillator to implement a data acquisition system. A higher sampling rate, compared with standard oversampled converters, is required to maintain a sufficient SNR in this case. In this paper, we propose an architecture based on a LC-CMOS oscillator and a digital interface that can be completely integrated on chip and satisfies low clock specifications of standard microphone capacitive interfaces. The complete system outputs one-bit bitstream at 15.53MHz and achieves SNR of 55.38dB for −26dBfs input tone.