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In this work, threshold voltage instability of normally off p-GaN high electron mobility transistors has been investigated by monitoring the gate current density during a device on-state. The origin of gate current variations under stress has been ascribed to charge trapping occurring at different interfaces in the metal/p-GaN/AlGaN/GaN system. In particular, depending on the stress bias level, electrons (VG < 6 V) or holes (VG > 6 V) are trapped, causing a positive or negative threshold voltage shift ΔVTH, respectively. By monitoring the gate current variations at different temperatures, activation energies associated with the electrons and holes trapping could be determined and correlated with the presence of nitrogen (electron traps) or gallium (hole traps) vacancies. Moreover, the electrical measurements suggested the generation of a new electron-trap upon long-time bias stress, associated with the creation of crystallographic dislocation-like defects extending across different interfaces (p-GaN/AlGaN/GaN) of the gate stack.

In this article, threshold-voltage VTH instabilities under positive gate voltage stress VGStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast VG ramp was applied in this study. PBTI transients performed at different VGStress and several temperatures highlight the influence of two trap populations, one being related to Al2O3 gate oxide defects and the other one to CN acceptors in GaN lattice. Both trap populations are located close to the Al2O3/GaN interface and lead to VTH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8–0.9 eV related to CN traps and an energy range between 0.7 and 1.5 eV ascribed to Al2O3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies.

Gallium nitride (GaN) and its AlGaN/GaN heterostructures grown on large area Si substrates are promising systems to fabricate power devices inside the existing Si CMOS lines. For this purpose, however, Au-free metallizations are required to avoid cross contaminations. In this paper, the mechanisms of current transport in Au-free metallization on AlGaN/GaN heterostructures are studied, with a focus on non-recessed Ti/Al/Ti Ohmic contacts. In particular, an Ohmic behavior of Ti/Al/Ti stacks was observed after an annealing at moderate temperature (600°C). The values of the specific contact resistance ρc decreased from 1.6×104 Ω.cm2 to 7×105 Ω.cm2 with increasing the annealing time from 60 to 180s. The temperature dependence of ρc indicated that the current flow is ruled by a thermionic field emission (TFE) mechanism, with barrier height values of 0.58 eV and 0.52 eV, respectively. Finally, preliminary results on the forward and reverse bias characterization of Au-free tungsten carbide (WC) Schottky contacts are presented. This contact exhibited a barrier height value of 0.82 eV.

In this paper, we investigate the influence of Poole–Frenkel effect (PFE) on the dynamic R ON transients in C-doped p-GaN HEMTs. To this aim, we perform a characterization of the dynamic R ON transients acquired during OFF-state stress (i.e. V GS,STR = 0 V < V T, V DS,STR = 25–125 V) and we interpret the results with the aid of numerical simulations. We find that dynamic R ON transients at room temperature accelerate with V DS,STR 1/2, which is signature of PFE, as further confirmed by the simultaneous decrease of the activation energy (E A) extracted from the Arrhenius plot of the dynamic R ON transients at V DS,STR = 50 V and T = 30 °C–110 °C. Results obtained by means of calibrated numerical simulations reproduce the exponential dependence of transients time constants (τ) on V DS,STR 1/2 and consequent E A reduction only when including the PFE-enhancement model of hole emission from dominant acceptor traps in the buffer related to C doping. This result is consistent with the ‘hole-redistribution’ model that considers hole emission from acceptor traps (rather than electron capture) as the mechanism underlying dynamic R ON increase during OFF-state stress.

Gallium Nitride, in the form of epitaxial HEMTs (High Electron Mobility Transistor), is now almost universally acknowledged as the replacement for silicon bipolar and power LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices as the primary active element for linear power amplification in RF (Radio Frequency), microwave, and mmW (Millimeter Wave) base station applications. This is particularly true for GaN-on-SiC (Silicon Carbide) discrete HEMT devices and MMIC's (Monolithic Microwave Integrated Circuits) which enable the state-of-the-art high frequency performance and bandwidth required for sub-6 GHz frequency bands covering both 4G and 5G systems as well as able to be extended into Ku-Band and Ka-Band applications. The challenge for GaN-on-Silicon technology is to take advantage of these industry accepted GaN-on-SiC results and leapfrog not only the high frequency/high power performance but also drive GaN into a new cost paradigm, enabling the opening of 5G applications currently beyond the price point of silicon carbide based systems.

SILICON CARBIDE (SiC) material has attracted substantial attention during the last few years as a promising candidate for making power devices for high-temperature operation and under harsh environments. In spite of the considerable progress in device performance, reliability may be a limiting factor for the introduction of SiC MOSFETs in commercial power devices. One of the major reliability concerns is the instability of the threshold voltage in MOSFETs and, similarly, of the flat-band voltage in capacitors under normal operation conditions. This instability is attributed to trapping of channel electrons in interface and bulk oxide traps. The main goal of this work is to investigate how the trapped charges at SiO2/SiC interface influence the C/V curve. In particular, by means of 2-D numerical simulations (SILVACO tools), we could isolate the two different contributions from p-type and n-type doped regions of our MOSFET and we considered both donor and acceptor traps contributions. Then, we compared the simulation results with experimental C/V curves. A good agreement between TCAD simulations and experimental measurements was obtained. So, device simulations can provide a better understanding of such defects at SiO2/SiC interface and we give an insight into the influence of traps, produced during device processing or caused by radiation environment, on the output characteristics of the device.

The fully recessed gate GaN-on-Si MOS-channel HEMTs (MOSc-HEMT) with Back-Barrier (BB) structure gives rise to unexpected threshold voltage (V TH ) behaviors such as V TH increase with decreasing gate length (L G ) (V TH roll-up) and discrepancies between V TH values extracted from I D (V G ) (V TH_IV ) and from C GC (V G ) (V TH_CV ) characteristics. Using TCAD simulations and experimental measurements, we demonstrate that conduction band confinement, especially at gate corners, is responsible for these peculiar V TH behaviors. This band confinement is strengthened by the fully recessed gate configuration coupled with the proximity of a back-barrier.

In this brief, we investigate the bidirectional threshold voltage drift ( $\Delta {V}_{T}$ ) following negative-bias temperature instability (NBTI) stress in carbon-doped fully recessed AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs). Several stress conditions were applied at different: 1) gate biases ( ${V}_{GS,STR}$ ); 2) stress times ( ${t}_{STR}$ ); and 3) temperatures ( ${T}$ ). Both negative and positive $\Delta {V}_{T}$ (thermally activated with different activation energies, ${E}_{A}$ ) were observed depending on the magnitude of ${V}_{GS,STR}$ . In accordance with the literature, observed $\Delta {V}_{T} V ( ${E}_{A}~\approx ~0.5$ eV) under moderate stress is attributed to the emission of electrons from oxide and interface traps. Instead, $\Delta {V}_{T} >0$ V ( ${E}_{A}~\approx ~0.9$ eV) under high stress is attributed to the increased negatively ionized acceptor trap density in the buffer associated with carbon doping.

Dynamic ${R}_{\mathrm{\scriptscriptstyle {ON}}}$ dispersion due to buffer traps is a well-known issue of GaN power high electron mobility transistors (HEMTs), critically impacting their performance and stability. Several works show that the dynamic ${R}_{\mathrm{\scriptscriptstyle {ON}}}$ reaches a maximum for some OFF-state drain–source voltage ( ${V}_{\text{DS},{\mathrm{\scriptscriptstyle OFF}}}$ ) value typically in the range of several hundred volts and then partially recovers to smaller values. In this work, we propose a quantitative explanation for this behavior, attributing it to the charging/discharging dynamics of carbon (C)-related buffer traps. We characterize the dynamic ${R}_{\mathrm{\scriptscriptstyle {ON}}}$ in packaged p-GaN gate AlGaN/GaN HEMTs with a custom measurement setup. We find that in these devices, the relative ${R}_{\mathrm{\scriptscriptstyle {ON}}}$ increase reaches a maximum of 60% for ${V}_{\text {DS}, {\mathrm{\scriptscriptstyle {OFF}}}} \approx 100$ –200 V, partially recovering to about 30% as ${V}_{\text {DS}, {\mathrm{\scriptscriptstyle {OFF}}}}$ is raised to 500 V. We ascribe this behavior to the partial neutralization of C-related acceptor traps in the buffer due to trapping of holes produced by a high-field generation mechanism. This explanation is supported by calibrated 2-D numerical simulations, that successfully reproduce the experimentally observed ${R}_{\mathrm{\scriptscriptstyle {ON}}}$ reduction only when including a hole generation mechanism.

In this study, we investigate the difference between I D (V G ) and C(V G ) pBTI shifts on GaN-on-Si E-mode MOS-channel HEMTs, under various gate voltage stresses (V GStress ) and temperatures (T). A new experimental setup using ultra-fast and simultaneous I D (V G ) and C(V G ) measurements enables to monitor the threshold voltage V TH drift through two metrics, $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ . Experimental pBTI results depict a difference between $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ , such as $\mathrm{\Delta}\mathrm{V}_{\text{THI}} . TCAD simulations support that ID(V G ) shift ( $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ ) is related to charge trapping in Al 2 O 3 gate oxide defects at the gate corners regions while C(V G ) shift ( $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ ) is mainly ascribed to the gate bottom, due to the presence of a back-barrier layer in the epitaxy. These previous results enable to deduce that the Al 2 O 3 defects density is more important at the gate corners than at the gate bottom.

In this paper, threshold voltage V TH instabilities under positive gate voltage stress (V GStress ) are thoroughly investigated on GaN-on-Si Enhancement-mode MOS-channel HEMTs. An analysis of pBTI transients performed at several V GStress and temperatures (T) reveals two trap populations close to the Al 2 O 3 /GaN interface namely (1) C N acceptors in the GaN substrate, and (2) defects in the Al 2 O 3 gate oxide. Both trap populations lead to V TH instabilities via different underlying mechanisms as evidenced by TCAD simulations. At V GStress TH drifts are ascribed to C N traps ionization localized at 0.8-0.9eV above the valence band (E v ). At higher VGstress, electron trapping also occurs in Al 2 O 3 defects leading to stronger V TH degradation. DC & AC pBTI transients have been modeled using Capture Emission Time (CET) map approach, which allowed the identification of both trap populations. Temperature-dependent CET maps extraction reveals a strong activation of C N traps with temperature, and confirms Arrhenius analysis consistency. This study provides a deep understanding of BTI reliability in GaN-HEMT technologies.

This paper aims to investigate the interface traps density (Dit) extraction on MOS gate stacks processed on GaN-on-Si substrates. CGV (Capacitance-Conductance) measurements under different frequencies (f = 1kHz-1MHz) and temperatures (T = 20K-500K) on various Al 2 O 3 /UID-GaN MOS capacitors were carried out. Thorough analysis under dark and UV light compared to TCAD/analytical modeling reveal a strong distributed series resistance under the gate related to the high resistivity of UID-GaN layer. This effect leads to an overestimation of the actual Dit value extracted at high frequencies (> 10kHz). Choosing an adequate doping under the gate (n-type) cancels the series resistance effect and unlocks a reliable extraction through {T/f} dependent CGV measurements.

ST, following its historical leadership position in Smart Power Technologies, is introducing the new STi2GaN Product Family for both 100V and 650V Voltage clusters: System in package with Si controller and Monolithic approach integrating the power stage with driver and protections will produce two main product clusters that, combined with proper packaging, will allow best ever application performances including a significant improvement for high efficiency and low emission rates. Using the example of a new monolithic H-Bridge designed for automotive 48V-12V DC/DC converter, this paper illustrates how STi2GaN technology aids the design of high-density power converter.

In this paper, near interface traps (NITs) in lateral 4H-SiC MOSFETs were investigated employing temperature dependent transient gate capacitance measurements (C-t). TheC-tmeasurements as a function of temperature indicated that the effective NITs discharge time is temperature independent and electrons from NITs are emitted toward the semiconductor via-tunnelling and/or trap-to-trap tunnelling. The NITs discharge time was modelled taking into account also the interface state density in a distributed circuit and it allowed to locate traps within a distance of about 1.3nm from the SiO2/4H-SiC interface.

We present a temperature-dependence electrical characterization of the oxide/semiconductor interface in MOS capacitors with a SiO2layer deposited on 4H-SiC using dichlorosilane and nitrogen-based vapor precursors. The post deposition annealing process in N2O allowed to achieve an interface state density Dit 9.0×1011cm-2eV-1below the conduction band edge. At room temperature, an electron barrier height (conduction band offset) of 2.8 eV was measured using the standard Fowler-Nordheim tunneling model. The electron conduction through the SiO2insulating layer was evaluated by studying the experimental temperature dependence of the gate current. In particular, the Fowler-Nordheim electron barrier height showed a negative temperature coefficient (dφB/dT= - 0.98 meV/°C), which is very close to the expected value for an ideal SiO2/4H-SiC system. This result, obtained for deposited SiO2layers, is an improvement compared to the values of the temperature coefficient of the Fowler-Nordheim electron barrier height reported for thermally grown SiO2. In fact, the smaller dependence ofφBon the temperature observed in this work represents a clear advantage of our deposited SiO2for the operation of MOSFET devices at high temperatures.

Owing to the high carrier density and high electron mobility of the two dimensional electron gas (2DEG), high electron mobility transistors (HEMTs) based on gallium nitride (GaN) are suitable devices for high power and high frequency applications. Clearly, the presence of the 2DEG at the interface of AlGaN/GaN heterostructures makes HEMTs intrinsically normally-on devices. However, for power electronics applications, normally-off operation is desired for safety reasons and to simplify the driver circuitry. In this context, although several approaches to obtain normally-off transistors have been reported in the literature, normally-off GaN-based HEMTs with a p-GaN gate is among the most promising and the only commercially available today. This paper reviews the most relevant technological issues for normally-off HEMTs with a p-GaN gate. First the operation principle and the impact of the heterostructure parameters are discussed. Then, the possible effects of the dry etching process of p-GaN are shortly mentioned. Thereafter, the role of the metal/p-GaN interface and the impact of the thermal processes on the electrical characteristics are widely discussed. Finally, recent alternative approaches proposed to avoid the use of the p-GaN dry etching are presented.

The evaluation and investigation of electrical parameters drifts during device operation is one of the mandatory task that has to be performed in order to improve GaN-power devices stability. In this work the authors would like to present a novel characterization method that allows the simultaneous monitoring of both RON and VTH during the switch-mode operation. By applying the proposed measurement method with different operating parameters it has been possible to provide a preliminary interpretation of the physical mechanisms leading to the observed RON increase and VTH positive shift. In particular, the observed RON increase, which is thermally activated with a 0.83 eV activation energy, has been ascribed to the presence of Carbon-related traps within the device buffer layer. On the other hand, the positive VTH shift has instead been related to interface defects at the dielectric/III–N interface and/or to bulk traps in the gate dielectric.

Among the wide band gap (WBG) semiconductors, silicon carbide (4H-SiC) and gallium nitride (GaN) are nowadays recognized as outstanding materials for the future of power electronics. In fact, owing to their excellent properties, they can guarantee a better energy efficiency in power conversion systems with respect to Silicon. Today, although several SiC and GaN devices have already reached the market, there are still many technological issues to be faced in order to fully exploit the enormous potential of these materials. In this context, this paper aims to review some emerging trends in the processing of WBG semiconductor devices (e.g., diodes, MOSFETs, HEMTs,...). The focus will be put on some selected "hot topics", like the channel mobility in SiC MOSFETs, the Ohmic contacts to SiC devices, and the approaches for normally-off GaN HEMTs. Finally, a summary of the open issues and a short outlook on the future perspectives of SiC ultra-high-voltage devices and vertical GaN devices will be given. (C) 2017 Elsevier B.V. All rights reserved.

This work reports on the physical and electrical characterization of the oxide/semiconductor interface in MOS capacitors with the SiO2 layer deposited by a high temperature process from dichlorosilane and nitrogen-based vapor precursors and subjected to a post deposition annealing process in N2O. Low interface state density (Dit ≈ 9.0×1011cm-2eV-1) was found at 0.2 eV from EC, which is comparable to the values typically obtained in other lower temperature deposited oxides (e.g., TEOS). A barrier height of 2.8 eV was derived from the Fowler-Nordheim plot, very close to the ideal value expected for SiO2/4H-SiC interface. Basing on these preliminary results, the integration in MOSFETs devices can be envisaged.

The electronic properties of the graphene (Gr) Schottky junction with an Al0.22Ga0.78N/GaN heterostructure on silicon have been investigated, both by experiment and with use of ab initio DFT calculations. A peculiarly high n-type doping (1.1 x 10(13) cm(-2)), observed for Gr in contact with AlGaN, was explained by the combined effect of Fermi level pinning by AlGaN surface states and charge transfer. Spatially uniform current injection across the Gr/AlGaN/GaN heterojunction was revealed by nanoscale resolution conductive atomic force microscopy (CAFM) analyses. Furthermore, a Gr/AlGaN/GaN Schottky diode with excellent rectifying behavior has been demonstrated and used as the key building block for a hot electron transistor (HET) with a 10 nm Al2O3 base-collector barrier. Thanks to the highly efficient hot electron injection from the AlGaN/GaN emitter, this transistor exhibits high on-state current density (J(C,ON) approximate to 1 A/cm(2)), high on-state over off-state current density ratio (J(C,ON)/J(C,OFF) approximate to 10(6)), and a common-base current gain alpha approximate to 0.15, solely limited by the high Al2O3 base-collector barrier. The excellent performances of the Gr/AlGaN/GaN Schottky junction represent an important step toward the development of a HET technology compatible with the state-of-the-art GaN high electron mobility transistors.

In this paper, we explore the influence of the fully recessed gate length on threshold voltage instabilities. The study has been performed by the use of ultra-fast pBTI measurements on GaN-on-Si E-mode MOSc-HEMTs, as well as TCAD simulations. It reveals that gate length reduction tends to decrease the pBTI degradation. Transient analyses (degradation/relexation) reveal same dynamics whatever the gate length while the value of the initial V TH directly influences BTI. TCAD simulations highlight that the full recess gate configuration creates a short-channel effect responsible for this peculiar Vth degradation.

In this paper, we investigate the influence of negative gate stress on threshold voltage V TH instabilities in GaN-on-Si devices. This study has been carried out by using ultra-fast Measurement-Stress-Measurement (MSM) procedure on GaN-on-Si E-mode MOSc-HEMTs (Enhancement-mode MOS-channel HEMTs) for different gate lengths L G . NBTI transients at different temperatures and complementary ToF-SIMS analysis reveal the influence of two trap populations involved on V TH instabilities, both of them are related to the C N acceptor traps. The first one is close to the interface between GaN and Al 2 O 3 gate oxide due to N-vacancies induced by the dry etching process, the second one is likely to be related to GaN:C layer. NBTI transients also exhibit a dependence with L G , which is consistent with the E-field distribution of the gate region obtained by TCAD simulations at different gate stress voltages, and confirm the proximity of a C N trap population to the gate oxide.

In this paper, the electrical behavior of a Ni/Au Schottky barrier on free standing GaN has been studied employing a variety of techniques and correlated with the material and interface quality. The temperature dependence of the ideality factor (n) and of the Schottky barrier height (ΦB) revealed a spatial inhomogeneity of the barrier. This behavior has been described by means of the Tung's model on inhomogeneous Schottky barriers. The origin of the barrier inhomogeneity can be likely associated to the surface quality of the GaN epilayer or to microstructure of the Ni/GaN interface.

The evaluation and investigation of electrical parameters drifts during device operation is one of the mandatory task that has to be performed in order to improve GaN-power devices stability. In this work the authors would like to present novel results concerning the analysis of VTH and RON drifts in E-mode GaN HEMT observed during their switch-mode operation. Two different mechanisms are observed for the induced positive VTH shift. The first one is related to electron injection from the 2DEG into dielectric/semiconductor traps beneath the gate region of the device, while a second one linked to electron injection from the gate terminal induces a VTH shift linked to a localized negative trapping mechanism in the drain-edge of the gate terminal. The observed RON increase is instead linked to a hole-emission process taking place in the gate-drain access region within the device carbon-doped buffer layers. The negative charge build-up related to the ionized acceptor traps leads to the 2DEG depletion and consequent RON increase.

In this review article, a comprehensive study of the mechanisms of Ohmic contact formation on GaN-based materials is presented. After a brief introduction on the physics of Ohmic contacts, a resume of the most important results obtained in literature is reported for each of the systems taken in consideration ( n -type GaN, p -type GaN and AlGaN/GaN heterostructures). The optimal metallization schemes and processing conditions to obtain low resistance Ohmic contacts are presented, discussing the role of the single metals composing the stack and the modification induced by the thermal annealing, either on the metal layers or at the interface with GaN. Physical insights on the mechanism of Ohmic contact formation have been gained by correlating the temperature dependence of the electrical parameters with a morphological/structural analysis of the interface. In the case of the AlGaN/GaN systems, the influence of the heterostructure parameters on the Ohmic contacts has been taken into account adapting the classical thermionic field emission model to the presence of the two dimensional electron gas (2DEG). Finally, the state of the art of “Au-free” metallization to AlGaN/GaN heterostructures is also presented, being this latter a relevant topic for the integration of GaN technology on large scale Silicon devices fabs.

The role of carbon-related traps in GaN-based ungated high-electron mobility transistor structures has been investigated both experimentally and by means of numerical simulations. A clear quantitative correlation between the experimental data and numerical simulations has been obtained. The observed current decrease in the tested structure during backgating measurements has been explained simply by means of a thermally activated hole-emission process with $E_{A} = 0.9$ eV, corresponding to the distance of the acceptor-like hole-trap level from the GaN valence band. Moreover, it has been demonstrated by means of electrical measurements and numerical simulations that only a low percentage of the nominal carbon doping levels induces the observed current reduction when negative substrate bias is applied to the tested structure.

This paper reports on the behavior of Al/Ti/p-GaN interfaces as gate contacts for p-GaN/AlGaN/GaN normally off high electron mobility transistor (HEMTs), highlighting the impact of the thermal budget on the metal gate on the device characteristics. In fact, while the devices subjected to an annealing at 800 °C show a considerable high leakage current, those with nonannealed Al/Ti gate contacts exhibit a normally off behavior, with a pinch-off voltage $V_{\mathrm {po}}= +1.1$ V and an on/off current ratio of $3 \times 10^{8}$ . Temperature-dependent electrical measurements on back-to-back Schottky diodes allowed to determine a Schottky barrier height $\Phi _{B}$ of 2.08 and 1.60 eV, for the nonannealed and 800 °C annealed gate contacts, respectively. Hence, the increase in the leakage current observed upon annealing at 800 °C was attributed to the lowering of the Schottky barrier height $\Phi _{B}$ of the metal gate. The interfacial structural characterization explained the barrier lowering induced by the annealing. This scenario was discussed through the simulated band diagram of the heterostructures, considering the experimental values of $\Phi _{B}$ . These results provide useful information for the device makers to optimize the fabrication flow of normally off HEMTs with p-GaN gate.