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Improvement of current drive in n- and p-type silicon junctionless metal-oxide-semiconductor-field-effect-transistors (MOSFETs) using strain is demonstrated. Junctionless transistors have heavily doped channels with doping concentrations in excess of 10(19) cm(-3) and feature bulk conduction, as opposed to surface channel conduction. The extracted piezoresistance coefficients are in good agreement with the piezoresistive theory and the published coefficients for bulk silicon even for 10 nm thick silicon nanowires as narrow as 20 nm. These experimental results demonstrate the possibility of enhancing mobility in heavily doped silicon junctionless MOSFETs using strain technology. (C) 2010 American Institute of Physics. [doi:10.1063/1.3474608]

In this paper we investigate the effects of intravalley acoustic phonon scattering on the quantum transport and on the electrical characteristics of multigate silicon nanowire metal-oxide-semiconductor field-effect transistors. We show that acoustic phonons cause a shift and broadening of the local DOS in the nanowire, which modifies the electrical characteristics of the device. The influence of scattering on off-state and on-state currents is investigated for different values of channel length. In the ballistic transport regime, source-to-drain tunneling current is predominant, whereas in the presence of acoustic phonons, diffusion becomes the dominant current transport mechanism. A three-dimensional quantum mechanical device simulator based on the nonequilibrium Green's function formalism in uncoupled-mode space has been developed to extract device parameters in the presence of electron-phonon interactions. Electron-phonon scattering is accounted for by adopting the self-consistent Born approximation and using the deformation potential theory. (C) 2010 American Institute of Physics. (doi: 10.1063/1.3457848)

In this paper, we simulate quantum transport in trigate silicon-on-insulator (SOI) nanowire field-effect transistors using 3-D numerical simulations. The formation of 1-D subbands in SOI nanowire, which results in the oscillation of the current and transconductance characteristic at low temperatures, has been studied in detail. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased, thereby enabling the experimental evaluation of the subband energy spacing in nanowire structures (subband spectroscopy).

This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and ON–OFF current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.

This paper investigates the influence of substrate bias of junctionless (JL) and Inversion-Mode (IM) MuGFETs such as a variation of threshold voltage. The JL MuGFET has a similar response to positive substrate bias as an IM MuGFET. However, narrow JL MuGFETs are far more sensitive to negative substrate bias than IM MuGFET.

Using three-dimensional quantum simulations we investigate the effluence of intravalley acoustic phonon scattering on the mobility in ultra scaled trigate silicon nanowire transistors. The electron transport is modeled using the Non-Equilibrium Green’s Function formalism and the elastic phonon scattering has been included using deformation potential theory and self- consistent Born approximation. Device parameters variations on ballistic and diffusive operation of the nanowire are studied extensively for the [100] channel direction. We also show that the elastic phonon scattering dramatically degrades the mobility, compared to the ballistic case.

This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.

In this paper, we present 3D quantum simulations based on Non-Equilibrium Green’s Function (NEGF) formalism using the Comsol Multiphysics™ software and on the implementation of a new Fast Coupled Mode-Space (FCMS) approach. The FCMS algorithm allows one to simulate transport in nanostructures presenting discontinuities, as the normal Coupled Mode-Space (CMS) algorithm does, but with the speed of a Fast Uncoupled-Mode Space (FUMS) algorithm (a faster algorithm that cannot handle discontinuities). We then use this new algorithm to explore the effect of local constrictions on the performance of nanowire MultiGate Field-Effect Transistors (MuGFETs). We show that cross-section variations in a nanowire result in the formation of energy barriers that can be used to improve the on/off current ratio and switching characteristics of transistors: (1) A small constriction resulting in a barrier of the order of a 0.1 eV can be used as an effective means to improve the subthreshold slope and minimize the on/off current ratio degradation resulting from SD tunneling in ultra scaled transistor, and (2) We also report a new variable barrier transistor (VBT) device concept that is able to achieve sub-kT /q subthreshold slope without using impact ionization or band-to-band tunneling. Intra-band tunneling through constriction barriers is used instead. The device is, therefore, fully symmetrical and can operate at very low supply voltages. A subthreshold slope as low as 56.5 mV/decade is reported at T = 300 K. The VBT reported here breaks the 60 mV/dec barrier over more than five decades of subthreshold current, which is the widest current range reported so far.

This paper describes the simulation of the electrical characteristics of a new transistor concept called the ‘‘Junctionless Multigate Field-Effect Transistor (MuGFET)”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversion-mode devices with PN junctions at the source and drain. The simulation results indicate that the junctionless MuGFET is a very promising candidate for future decananometer MOSFET applications.

An unusual bump in the gate capacitance characteristics of Si nanoscale MuGFETs is presented and explained here through 3D NEGF quantum simulations. As higher order subbands are populated when the gate voltage is increased, the channel moves closer to the surface. This increases the slope in the Id-Vg and creates the bump in the Cg(Vg) curve as the centroid of the charge moves closer to the Si/SiO2 interface and the capacitance is increased.

We present here 3D quantum simulations based on Non-Equilibrium Green’s Function (NEGF) formalism using the Comsol Multiphysics™ software and on the implementation of a new Fast Coupled Mode-Space (FCMS) approach. The FCMS algorithm allows one to simulate transport in nanostructures presenting discontinuities, as the normal Coupled Mode-Space (CMS) algorithm does, but with the speed of a Fast Uncoupled-Mode Space (FUMS) algorithm (a faster algorithm that cannot handle discontinuities). Using our simulator, we also show that energy barriers resulting from cross-section variations at the gate edge of a nanowire can be optimized to improve the on/off current ratio. A subthreshold slope steeper than the kT/q.log(10) limit of classical transistors together with symmetrical source drain operation is demonstrated for the first time using this new Variable barrier tunnel transistor (VBT) concept.

In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.

We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.