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Objective. Comprehensive integrated circuit (IC) verification plays a crucial role in preventing costly errors and delays in product development cycle. It includes testing interaction and compatibility of different system elements, such as central processing unit, memory and various peripheral devices. Validating IC’s compliance to the functional requirements list may take up to 70% of the design process duration. This proportion grows with complexity and size of the device under development. Consequently, the essential tasks that integrated circuit developers face are research and development of methods for cutting design complexity and reducing implementation time.Method. Conducted research regarding usage of genetic algorithm for error discovery, which could lead to a failure in the end product.Result. Collected data regarding the amounts of victims and target errors for each fault of types stuck-at-0 and stuck-at-1 for circuits from ISCAS’85 and ISCAS’89 benchmarks. It has been discovered that the proposed method is more effective in comparison to random vector generation to an extent of target errors amount for every benchmark.Conclusions. Accumulated results allow for the algorithm usage during IC design in order to reduce time consumption for circuitry validation and improve on test kits quality.

Nowadays, System on Chip (SOC) based devices such as smartphones, tablets, cameras, and others are commonly used. The cost of these devices is determined by the expenses associated with their manufacturing and testing. In modern manufacturing technology, SOC-based devices have more cores embedded within them. However, testing these numerous cores thoroughly can be quite expensive and can sometimes cost more than the manufacturing itself. To make these devices more affordable for people from economically weaker backgrounds, it is necessary to come up with an efficient testing strategy that can help reduce the costs. In this study, we introduce a new method of testing the SOC incompletely instead of testing it thoroughly. This method involves compromising on the test quality, which may result in errors in the output. Incomplete testing is performed only for those cores of the SOC that can tolerate such errors. For example, incomplete testing is performed for the cores that are responsible for multimedia applications such as image or video display, where a slight compromise in the quality can be tolerated by human eyes. This incomplete testing helps to reduce the Test Power Consumption (TP), Test Access Time (TAT), and Test Data Volume (TDV) while compromising with the Fault Coverage (FC). [ABSTRACT FROM AUTHOR]

This paper presents a novel flexible concurrent testing scheme for non-feedback and feedback bridging faults in integrated circuits. All the existing concurrent testing schemes for non-feedback and feedback bridging faults available in the literature are designed with very straightforward manner and these schemes do not provide any idea regarding flexibility in design of the tester circuit. However, providing flexibility in design of the tester circuit is one of the important criteria to be included in concurrent testing of modern integrated circuits. To the best of my knowledge, the proposed scheme will be treated as first concurrent testing scheme that provides flexibility in design of the tester circuit for both non-feedback and feedback bridging faults. This work aims to provide flexibility in tester circuit design by dropping some of wires that are tapped from Circuit Under Test (CUT) to the tester circuit. Dropping some of tap wires from CUT to the tester circuit reduces load on CUT and this helps in reducing the area overhead of the tester circuit. Thus, flexibility in concurrent testing is achieved by dropping some of tap wires during design of tester circuit. Further, dropping some of tap wires (flexibility) in tester circuit design provides a trades-off analysis between area overhead, fault coverage and fault detection latency. The proposed scheme is verified using different ISCAS89 benchmark circuits and results illustrate that flexibility in design of tester circuit is achieved through dropping some of tap wires from CUT to the tester circuit. Further, it reduces area overhead greatly with minimal compromise in fault coverage. [ABSTRACT FROM AUTHOR]

In this paper, a testing technique based on supply current verifying is presented, for fault detection of analog circuits containing CMOS operational amplifiers. This testing technique is employed and developed to maximize the fault coverage of the circuit under test (CUT) using transient and frequency responses of the supply current. This testing method is based on the over-sighting of the quiescent supply current (Iddq) of the CMOS operational amplifier operating in its quiescent mode and the supply current of the CMOS operational amplifier used as a Sallen-Key band pass filter in the AC and transient operating domains. The faults investigated in our study are of bridging and open circuit types that occur at the CMOS transistor level. The Pspice software was used for the CUT simulation by applying Monte-Carlo analysis in faulty and fault free conditions. Test parameters are extracted and selected to be used as input features of our classifier. [ABSTRACT FROM AUTHOR]

Test data volume reduction and power consumption during testing time outlines are two main problems for Very Large Scale Integration (VLSI) gadgets. Most the code-based arrangements have been utilized to diminish test data volume, although the most notable way that test data volume is high. The switching action that happens between the test carriers leads would expand power consumption. This work presents a compression/decompression methodology for limiting the amount of test data that should be kept on a tester and conveyed to each center in a System on a Chip (SOC) during a test utilizing the Adaptive Multiscale Transformation Run Length Code (AMT-RLC). The data transmission capacity between the tester and the SOC is a block when testing modern SOCs with a few centers to check how long the test can run. The proposed work keeps the tester in the SOC and the test vectors in a compacted memory structure. A modest quantity of On-chip equipment is needed to release different test vectors. Due to its variouscharacteristics that decrease the test data volume, the Adaptive Multiscale Transformation Run Length Code is picked for a center test vector framework. These attributes ensure that the code words overhead is decoded (and applied to the center's output exhibit grouping commitment) utilizing an exact cell cluster that occupies less space. The suggested strategy may provide test data compression with much-reduced Area overhead for the decoder and low power consumption, according to the results. The abstract shall be running continuously (not structured) and shall not include reference citations. Abbreviations should be defined in full the first time they appear. Abbreviations could be then used, quoted in-between parentheses. [ABSTRACT FROM AUTHOR]

In this paper, a method for maximum fault coverage with minimum power dissipation, during the testing of analog and digital circuits of mixed-signal System-on-Chip (SOC) simultaneously using Genetic Algorithm, (GA) is proposed. Mixed-signal SOC consists mainly of an analog block, a digital block and a DAC/ADC (Digital to Analog Converter/Analog to Digital Converter). Due to the presence of analog and digital circuits in mixed-signal SOCs, the testing procedure is difficult from that of only analog or digital circuit testing. Here stuck at 0/1 faults are considered for digital circuits, and stuck open/short faults are considered for analog circuits. In analog testing fault modeling, fault injection and fault simulation are done. The outputs of the analog block and some independent digital signals are given to the digital block. The GA-based approach is used for power-aware ordering of test patterns considering pattern dependency on previous patterns at the input of digital block as input patterns. The effect of noise on analog test signals has also been investigated here with the area analysis of the circuit. An average of 92.43% fault coverage and 13.56% maximum power saving is achieved when this methodology is applied to ITC 97 (Analog block) and ISCAS 85 (Digital block) benchmark circuits, respectively. A trade-off between fault coverage and power dissipation has been presented. [ABSTRACT FROM AUTHOR]

This work presents a low cost automatic test generation tool for structural analog testing. With the spice netlist and technology models of the circuit to be tested, a fault list is generated, considering a defect modeling provided by the user. The tool interacts with a spice simulator, simulating the fault-free and faulty circuits. The test development considers DC, AC (single tone) and transient (step) stimuli applied at the primary circuit inputs, computing the obtained fault coverage when taking different circuit nodes as observation points. The final test set determination relies on a fault dictionary that helps maximizing the fault coverage, at the same time as minimizing the test application. Since different circuit nodes are observed during the fault simulation campaign, this tool also helps the test developers and designers on defining Design-for-Testability strategies to increase fault detection by covering the undetected faults identified. The feasibility of the proposed method and the applicability of the tool are demonstrated with two case-studies, consisting in fully-differential integrated filters designed on a commercial 180 nm process. Results show that fault coverages near to 95% are obtained in both case-studies while requiring small test sequences with simple parametric measurements. [ABSTRACT FROM AUTHOR]

Wireless sensor networks (WSN) deploy many nodes over an extended area for traffic surveillance, environmental monitoring, healthcare, tracking wildlife, and military sensing. Nodes of the WSN have a limited amount of energy. Each sensor node collects information from the surrounding area and forwards it onto the cluster head, which then sends it on to the base station (BS). WSNs extend the lifetime of the network through clustering techniques. Choosing nodes with the greatest residual energy as cluster heads is based on the idea that energy consumption is periodically distributed between nodes. The sink node gathers information from its environment that is then transmitted to the base station. The clustering protocol uses a considerably amount of energy for data collection and transmission, with additional energy used for listening to the nodes. It also contributes to channel sensing and avoiding collisions alongside energy transmission. Most clustering techniques do not consider cluster fails, because of which detection through cluster heads or the BS is not possible. Terminated nodes and sub-cluster heads thus continue to transmit information to the failed sub-cluster head, which leads to higher energy consumption. In light of this, we propose a technique to choose cluster heads while reducing the use of CSMA/CA through fault tolerance to determine the failure of the cluster heads by consuming little energy. This work here contributes to increasing the life of the WSN and conserving its energy by more than a half-sensor node per round. [ABSTRACT FROM AUTHOR]

The LFSRs have been employed as test pattern generator in BIST for decades; however an emerging problem with design constraints leads a lot of improvements in this field. This paper presents a memory efficient FSM encoding-based method to generate test patterns for a given primitive polynomial LFSR TPG. Here test patterns generated from LFSR is divided into groups and follows encoding to transform into multiple test patterns. These newly generated encoded test patterns further divided into transitional and non-transitional blocks which control the bit transitions over encoded values. This weighted driven bit transition also prevents certain bit transitions that reduce the dynamic power as well during testing process. Here highly optimized LFSR test pattern generation is accomplished with high performance TPG design. Extra clocking is also applied to control LFSR output test pattern for improved randomization characteristics of test patterns and pseudorandom measures. The generated random patterns from LFSR are applied to CUT for improved fault coverage using shift and scan method. [ABSTRACT FROM AUTHOR]

The paper develops an efficient mechanism with a view to healing bridging faults in synchronous sequential circuits. The scheme inserts faults randomly into the system at the signal levels, encompasses ways to intrigue the state of the signals and carries it with steps to rig out the true values at the primary output lines. The attempts espouse the ability of the methodology to explore the occurrence of a variety of single and multiple bridging faults and arrive at the true output. The approach enables to detect the occurrence of wired-OR and wired AND bridging faults in the combinational part of the serial binary adder as the CUT and heal both the inter and intra-gate faults through the use of the proposed methodology. It allows claiming a lower area overhead and computationally a sharp increase in the fault coverage area over the existing Triple Modular Redundancy (TMR) technique. The Field Programmable Gate Arrays (FPGA) based Spartan architecture operates through Very High-Speed Integrated Circuit Hardware Description Language (VHDL) to synthesize the Modelsim code for validating the simulation exercises. The claim incites to increase the reliability of the synchronous sequential circuits and espouse a place for the use of the strategy in the digital world.

Traditional literature on analog testing deals with the propagation of faults to the output ports of a circuit. Often the percentage of detected faults remains low because suitable stimuli cannot be found for propagating certain faults to the outputs. Existing technology supports monitoring internal nets of a circuit, thereby improving fault detection by observing their effect on internal nets. However, this approach is feasible only if the number of internal nets probed by the built-in test structure is limited. This paper presents a structured approach that identifies a small well-chosen subset of internal nets which, when probed, can increase the coverage of analog faults. Further, it describes a formal methodology to identify distinct sub-circuits in a given design, that could be independently probed for detection of faults. Thus, for a given fault universe, the complexity of simulations can be reduced significantly by simulating only the sub-circuits rather than the entire design. We utilize the speed of DC analysis, some common features of analog signals, and partitioning of the transistor netlist using a Channel Connected Graph to accomplish this outcome. We report significant improvement in fault coverage on several circuits including some Analog/Mixed-Signal benchmarks. [ABSTRACT FROM AUTHOR]

Deterministic test generation methods are time consuming and, this has led to emergence of simulation-based approaches. The basis of simulation-based methods is to propose a number of test vectors, evaluate the efficiency of the proposed vectors, and accept or reject them. In these methods, the efficiency of each test vector is traditionally evaluated based on fault coverage of that vector. In this paper an alternative criterion based on probabilistic simulation approaches is proposed that can be calculated much faster than fault coverage. Statistical evaluations confirm a strong correlation between the proposed measure and fault coverage. The proposed measure can be used in simulation-based and meta-heuristic test generation methods to achieve speedup. In order to indicate efficiency of the proposed probabilistic measure, two test generation methods that utilize this measure are suggested and exploited to generate test for ISCAS85 benchmark circuits. These test generation methods are called PMI_PRUNE and PMI_GA. Our results demonstrate that PMI_PRUNE can achieve up to 21.2x, while the maximum speedup in PMI_GA is 5.0x. The average speedup in PMI_PRUNE and PMI_GA is about 9.6x, and 2.7x respectively. [ABSTRACT FROM AUTHOR]

Nowadays, the behaviour of many systems can be properly described by taking into account time constraints, and this motivates the adaptation of existing Finite State Machine (FSM)- based test derivation methods to timed models. In this paper, we propose a method for deriving conformance tests with the guaranteed fault coverage for a complete possibly nondeterministic FSM with a single clock; such Timed FSMs (TFSMs) are widely used when describing the behaviour of software and digital devices. The fault domain contains every complete TFSM with the known upper bounds on the number of states and finite boundary of input time guards. The proposed method is carried out by using an appropriate FSM abstraction of the given TFSM; the test is derived against an FSM abstraction and contains timed input sequences. Shorter test suites can be derived for a restricted fault domain, for instance, for the case when the smallest duration of an input time guard is larger than two. Moreover, the obtained test suites can be reduced, while preserving the completeness, when all input time guards of the specification and an implementation are right closed (or all intervals are left closed). Experiments are conducted to study the length of test suites constructed by different methods.

This paper presents a modified global energy production computation formula that replaces the traditional Performance Ratio (PR) with a novel Solar Reliability Factor (SRF) for mobile solar tracking systems. The SRF parameter describes the reliability and availability of a dual-axis solar tracker, which powers a smart home automation system entirely by using clean energy. By applying the SRF in the global energy production formula of solar tracking systems, we can predict the energy generation in real time, allowing proper energy management of the entire smart home automation system. Regarding static deployed Photovoltaic (PV) systems, the PR factor is preserved to compute the power generation of these devices accurately. Experimental results show that the energy production computation constantly fluctuates over several days due to the SRF parameter variation, showing a 26.11% reduction when the dual-axis solar tracker’s availability is affected by system errors and maximum power generation when the solar tracking device is operating in optimal conditions.

Testing is an essential process to validate the truthful functionality of logic circuits, devices, and systems. It accounts a large overhead in terms of additional hardware, time, and manpower which dramatically enhance overall cost of manufacturing. The efficacy of multiple control Fredkin (MCF) gates towards both online and offline testing paradigms is demonstrated here by exploiting their parity preserving and conservative properties. The authors introduce (i) a method of testing MCF circuits for the detection of bit‐flip faults online; (ii) deterministic approaches for the identification of stuck‐at, bridging, missing gate, and cross‐point faults; and (iii) three test sets of size 2, n, and 2(n−2) for the detection of these faults off‐line. Experiments are performed on a set of benchmarking circuits to demonstrate the effectiveness of the proposed methods in terms of test overhead and fault coverage. Online testable circuits are formulated on account of 0.5% of overhead in terms of considered cost metrics and an average reduction up to 61% is calculated with respect to existing work in the area. The test sets show completeness for the detection of all considered fault models. Fault simulations for both the presented testing methodologies are carried out which shows 100% coverage. [ABSTRACT FROM AUTHOR]

Software-based self-test (SBST) is being widely used in both manufacturing and in-the-field testing of processor-based devices and systems-on-chips. Unfortunately, the stuck-at fault model is increasingly inadequate to match the new and different types of defects in the most recent semiconductor technologies, while the explicit and separate targeting of every fault model in SBST is cumbersome due to the high complexity of the test-generation process, the lack of automation tools, and the high CPU-intensity of the fault-simulation process. Moreover, defects in advanced semiconductor technologies are not always covered by the most commonly used fault-models, and the probability of defect-escapes increases even more. To overcome these shortcomings, we propose the first fault-independent method for generating SBST procedures. The proposed method is almost fully automated, it offers high coverage of non-modeled faults by means of a novel SBST-oriented probabilistic metric, and it is very fast as it omits the time-consuming test-generation/fault-simulation processes. Extensive experiments on the OpenRISC OR1200 processor show the advantages of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a mathematical approach for determining the reliability of solar tracking systems based on three fault coverage-aware metrics which use system error data from hardware, software as well as in-circuit testing (ICT) techniques, to calculate a solar test factor (STF). Using Euler’s named constant, the solar reliability factor (SRF) is computed to define the robustness and availability of modern, high-performance solar tracking systems. The experimental cases which were run in the Mathcad software suite and the Python programming environment show that the fault coverage-aware metrics greatly change the test and reliability factor curve of solar tracking systems, achieving significantly reduced calculation steps and computation time.

In the present era of complex systems like avionics, industrial processes, electronic circuits, etc., on-the-fly or on-line fault detection is becoming necessary to provide uninterrupted services. Measurement limitation based fault detection schemes are applied to a wide range of systems because sensors cannot be deployed in all the locations from which measurements are required. This paper focuses towards On-Line Testing (OLT) of faults in digital electronic circuits under measurement limitation using the theory of discrete event systems. Most of the techniques presented in the literature on OLT of digital circuits have emphasized on keeping the scheme non-intrusive, low area overhead, high fault coverage, low detection latency etc. However, minimizing tap points (i.e., measurement limitation) of the circuit under test (CUT) by the on-line tester was not considered. Minimizing tap points reduces load on the CUT and this reduces the area overhead of the tester. However, reduction in tap points compromises fault coverage and detection latency. This work studies the effect of minimizing tap points on fault coverage, detection latency and area overhead. Results on ISCAS89 benchmark circuits illustrate that measurement limitation have minimal impact on fault coverage and detection latency but reduces the area overhead of the tester. Further, it was also found that for a given detection latency and fault coverage, area overhead of the proposed scheme is lower compared to other similar schemes reported in the literature.