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Operation of the 1-transistor, 1-capacitor dynamic random access memory cell that allows for two-bit operation, double the typical storage capacity, is explored. By using a metal-ferroelectric-semiconductor field-effect transistor, a second bit is captured in the ferroelectric layer polarisation resulting from negative and positive polarisation states. As a result, new modes of operation are created giving non-volatile, long-term storage as well as decreased power consumption and radiation hardening. A typical write and read operating cycle is outlined in-depth and used to verify operation indicating four distinct states representing the two bits. The resulting empirical data gives a comprehensive presentation of the read cycle of the memory cell. Methods for determining the polarisation state of the transistor are also explored and used to determine the average value for measured channel resistance using three types of transistors, each having different channel width and length.

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

The ferroelectric transistor (FeFET) provides unique characteristics of memory circuits due to its hysteresis effects. This paper examines the design considerations of a 1T-1C dynamic random-access memory (DRAM) cell using a ferroelectric transistor. The research investigates the effects of the FeFET on the DRAM cell while modifying design parameters which are controlled by the circuit designer. Parameters include channel width and length and write-word-line (WWL) voltage. Experimental data will be taken for different circuit configurations. Comparisons will be made to similar circuits that utilize only metal-oxide-semiconductor field effect transistors (MOSFETs).

Dynamic random-access memory (DRAM) cells offer advantages over static random-access memory (SRAM) cells due to their reduced size and relaxed constraints on device sizing ratios. In this paper, the usage of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) in a three-transistor dynamic random-access memory (DRAM) cell is examined, in order to determine the effects caused by its hysteresis properties. Combinations of metal-oxide-semiconductor field effect transistors (MOSFETs) and MFSFETs are explored, along with implementations consisting only of MFSFETs. The effects seen in these circuit configurations will be compared to configurations using only MOSFETs. Experimental data will be presented, showing the effect of varying parameters of the devices and circuit, such as channel length and width, input voltage waveforms, load devices, and capacitance. Particularly, attention will be given to the application of waveforms containing negative voltages to the gates of the transistors.

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

In this paper, empirical data describing the channel resistance and polarization of several metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) is presented. Various channel length and width transistors were used to describe the channel resistance under various biasing conditions and in both positive and negative polarization states. The presented results and analysis provide insight into the switching speed between polarization states as well as the timing and retention constraints for a given set of device dimensions. This is of particular value when considering circuit designs that utilize MFSFETs, especially digital memory circuits.

The temperature effects on a ferroelectric non-volatile memory latch were measured. The device is based on a design from Radiant Technologies Inc. utilizing a discrete ferroelectric capacitor. The effects measured include functionality, I-V characteristics and retention. The range of temperatures for which the device was tested is –107°F to +302°F. The results are compared with measurements made at room temperature for the device. Retention measurements of the device at elevated temperatures allow predictions of retention performance under normal operating conditions. Potential applications of this device in harsh environments which include aerospace, industrial and automotive are presented.

The implementation of a non-volatile latch circuit developed with a metal–ferroelectric–semiconductor field-effect transistor is presented. The circuit contains two inverter stages in order to create and rectify the desired waveform. The hysteresis properties of the ferroelectric transistor allow it to retain a polarisation state after an applied voltage at the gate is removed. This circuit has reduced power requirements because a constant power supply is not needed at all times; instead, a voltage is only needed at the gate of the ferroelectric transistor when storing a value, and the other components only need a power supply when reading the stored value from the circuit. The circuit is less complex than similar non-volatile latches because only a single ferroelectric transistor is used and fewer overall transistors may be used. It also has the advantage of being radiation-hardened for space applications.

In this paper, Part II of the authors’ paper [1] , the physically-derived nonquasi-static model presented in [1] is applied to the ferroelectric common-source and common-gate amplifiers. The model is based on the method of partitioned channel and ferroelectric layers and is valid in accumulation, depletion, and all three cases of inversion: weak, moderate, and strong. The equations of this model are based on the standard MOSFET equations that have been adapted to include the ferroelectric properties. The model code is written in MATLAB and outputs voltage plots with respect to time. The accuracy and effectiveness of the model are verified by two test cases, where the modeled results are compared to empirically-derived oscilloscope plots.

A physically-derived nonquasi-static model describing the behavior of the ferroelectric common-drain amplifier is presented. The model is based on the method of partitioned channel and ferroelectric layers and is valid in accumulation, depletion, and the three inversion cases: weak, moderate, and strong. The equations of this model are based on the standard MOSFET equations that have been modified to reflect the ferroelectric properties. The model code is written in MATLAB and outputs voltage plots with respect to time. The accuracy and effectiveness of the model are verified by a few test cases, where the modeled results are compared to empirically-derived oscilloscope plots.

Data is presented in this paper that was obtained using a metal-ferroelectric-semiconductor field effect transistor (MFSFET) in a common-drain amplifier configuration. The empirical data shown has been collected using larger drain voltages than previously seen, which helps to further understand and characterize the interesting operation of this amplifier circuit. The effects of varying different parameters such as load resistance, poling voltage, and input voltages of the amplifier circuit are examined. Differences between the MFSFET and MOSFET common-drain amplifier configurations are explored in-depth.

This paper presents a new mathematical model created for the common-drain amplifier using metal-ferroelectric-semiconductor field effect transistors (MFSFET). The model developed in this paper is based upon empirical data collected through experimentation with the common-drain amplifier while using a MFSFET. Several parameters are considered when calculating the output voltage, such as varying gate capacitance, input voltage, quiescent point, and power supply voltages. A comparison between collected and modeled data is presented as verification of the model's performance when applied to the common-drain configuration.

We present a detailed and accurate physics based method for modeling flash memory programming characteristics when the substrate contains different percentages of Germanium. Typical memory cells are programmed by moving electrons from the substrate to the floating gate. We determine this electron movement by considering the contributions attributed to the Nonquasi-Static gate current and tunneling currents while keeping the Germanium percentage as an independent variable. The simulations accuracy is further increased by using Nonquasi-Static methods to determine the drain and source currents as well as the device capacitance values. The goal of this paper is to highlight the physical parameters of the memory cell that are affected by Germanium and show the improvements that can be achieved by using Silicon-Germanium (SiGe) substrate material versus Silicon only. Several papers have been published on MOSFET's with SiGe substrates but none have been published on the use of SiGe substrates to improve flash memory programming.

We present a detailed and accurate physics based transient simulation for modeling flash memory programming characteristics using nonquasi-static and tunneling equations versus the typical Lucky-Electron Model. The result is a set of simple expressions that were originally developed for a MOSFET and adapted for use in floating gate memory. Of greater importance is the extensive use of physical parameters as opposed to the scale factors and probabilities used in other models. This technique allows floating gate memory designers to determine the nominal programming characteristics of single-level and multi-level memory cells prior to the fabrication process. This technique also allows designers to determine the effects of fabrication tolerances on the performance of the memory cell. The accuracy of this model was validated through comparison with experimental data and simulation results presented in several publications.

I-V characteristics for FeFET different than that of MOSFET Ferroelectric layer features hysteresis trend whereas MOSFET behaves same for both increasing and decreasing VGS FeFET I-V characteristics doesn't show dependence on VDS A Transistor with different channel length and width as well as various resistance and input voltages give different results As resistance values increased, the magnitude of the drain current decreased.

In this paper we present a data retention analysis of a non-volatile ferroelectric memory device. A ferroelectric capacitance coupled with a sense capacitance in a Sawyer tower is used as the memory component of the device. The cumulative direction of all the dipoles in the ferroelectric capacitance material corresponds to its memory. The positive and negative remnant polarization charge states of the capacitor when an electric field is applied to it are denoted as either data ‘0’ or data ‘1’[1]. In addition to retention the voltage and current characteristics of the circuit were measured. Measurements of the ferroelectric capacitor's polarization taken at different delay time intervals are also presented.

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

This paper investigates the Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell erase cycle. A nonquasi-static (NQS) MOSFET model was developed and implemented in software. The model equations were incrementally solved at each time step. During an erase cycle, a negative pulse is applied to the gate which causes Fowler-Nordheim tunneling between the floating gate and channel. The SONOS floating gate voltage, tunneling current, and threshold voltage were characterized during this erase cycle. Comparisons were made between the model predictions and experimental data for the threshold voltage.

We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

NASA is planning on going beyond Low Earth orbit with manned exploration missions. The radiation environment for most Low Earth orbit missions is harsher than at the Earth's surface but much less harsh than deep space. Development of new electronics is needed to meet the requirements of high performance, radiation tolerance, and reliability. The need for both Volatile and Non-volatile memory has been identified. Emerging Non-volatile memory technologies (FRAM, C-RAM,M-RAM, R-RAM, Radiation Tolerant FLASH, SONOS, etc.) need to be investigated for use in Space missions. An opportunity arose to fly a small memory experiment on a high inclination satellite (FASTSAT). An off-the-shelf 512K Ramtron FRAM was chosen to be tested in the experiment.

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

The National Aeronautics and Space Administration (NASA) is developing high-tolerance, radiation-hardened electronics for missions in and beyond Low Earth orbit. Ferroelectric-based electronics are highly viable candidates for these electronics because of their inherent radiation-hardened property. Since standard memory devices are prone to damage caused by radiation, ferroelectric memory may provide the needed radiation-tolerance. To test the effectiveness of ferroelectric random access memory (FRAM) in Low Earth orbit, a 512 K Ramtron FRAM will be flown on a Low Earth orbit satellite that will be launched by NASA. This paper discusses the advantages of ferroelectric electronics and outlines the Low Earth orbit ferroelectric memory test experiment.

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization.

This paper presents empirical data that was collected through experiments using a FeFET in the established common-source amplifier circuit. The unique behavior of the FeFET lends itself to interesting and useful operation in this widely used common-source amplifier. The paper examines the effect of using a ferroelectric transistor for the amplifier. It also examines the effects of varying load resistance, biasing, and input voltages on the output signal and gives several examples of the output of the amplifier for a given input. The difference between a commonsource amplifier using a ferroelectric transistor and that using a MOSFET is addressed.

This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

This paper presents a mathematical model characterizing the behavior of a common-source amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the common-source amplifier is the most widely used amplifier in MOS technology, understanding and modeling the behavior of the FeFET-based common-source amplifier will help in the integration of FeFETs into many circuits.

We present a detailed and accurate physics-based transient simulation for modeling Flash memory erase characteristics when the substrate contains different percentages of germanium (Ge). Typical cells are erased by moving electrons from the floating gate to the drain, source, or substrate. This paper addresses substrate erase modeling using a simulation based on the solution to Poisson's equation with Ge percentage as an independent variable. The goal of this paper is to demonstrate the derivation of an accurate erase simulation and show the improvements that can be achieved by using silicon-germanium (SiGe) substrate material versus silicon (Si) only. Several papers have been published on MOSFETs with SiGe substrates, but none has been published on the use of SiGe substrates in Flash memory.

This paper presents a mathematical model characterizing the behavior of a common-drain amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the amplifier is the basis of many circuit configurations, a mathematical model that describes the behavior of a FeFET-based amplifier will help in the integration of FeFETs into many other circuits.

The use of ferroelectric field-effect transistors (FeFETs) to create simple amplifiers is not completely understood and has not been extensively studied. This paper summarizes the results of behavioral characterization of a FeFET-based analog amplifier. The characterization incorporates several variables that affect the amplifier's output, including frequency, load resistance, and gate-to-source voltage. More specifically, the relationship between the frequency of the input signal and each of the peak output voltage, phase shift of the output signal, and voltage gain is examined. Also analyzed is the effect of load resistance on each of these three output parameters. These relationships are noted in actual oscilloscope outputs.

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also posses unique characteristics that made them have interesting and useful properties in analog circuits. Because ferroelectric transistors posses the properties of hysteresis and nonlinearity, an analog amplifier containing an FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of a simple analog amplifier using both a traditional FET and a ferroelectric FET. The characterization includes voltage transfer, gain, frequency response, and operating modes. Because of the hysteresis effects the FeFET amplifier has two distinct operating modes, each with significantly different properties. These two regions have very different gain characteristics and are nonlinear. This has the effect of being able to program the FeFET to have two different voltage transfer/current characteristics with a single device. This can a...

Ferroelectric devices provide many benefits over standard Metal-Oxide Semiconductor (MOS) devices. There is considerable interest in the aerospace industry in the reliability and radiation hardening effects that the ferroelectric memory devices provide. The modeling of a Ferroelectric Static Random Access Memory (FeSRAM) cell is to be investigated. The SRAM memory cell under investigation is a standard four transistor cell with the MOS Field-Effect Transistors (MOSFETs) replaced with Ferroelectric Field Effect Transistors (FeFETs). The SRAM FeFETs were simulated by using a previously developed model. Comparisons were made between the FeSRAM and a standard MOSFET SRAM.

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness from 200 nanometers to 1 nanometer.

Previous research investigated the modeling of a NAND gate constructed of n-channel Metal-Ferroelectric-Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate.

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. This paper addresses substrate erasing using a negative gate bias voltage based on the approximate solution to Poisson's equation. Substrate erasing using a negative gate bias voltage is one of the more prevalent ways to erase flash memory in currently available consumer products. Many papers have been published on this topic but rarely present detailed derivations and none using this exact set of equations to model this erasing process.

The modeling of a NAND gate constructed of Metal-Ferroelectric-Semiconductor Field Effect Transistors (MFSFETs) has been investigated. Initially, an inverter circuit was modeled using a n-channel MFSFET with positive polarization for a standard CMOS inverter n-channel transistor and a n-channel MFSFET with negative polarization for the standard CMOS inverter p-channel transistor. The MFSFETs were simulated by using a previously developed MFSFET model which utilized a partitioned ferroelectric layer. Then a 2-input NAND gate was modeled similar to the inverter gate. The data shows that it is feasible to construct a NAND gate with MFSFET transistors.

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

A model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. The model is based on an existing model that incorporates partitioning of the ferroelectric layer to calculate the polarization within the ferroelectric material. The model incorporates several new aspects that are useful to the user. It takes into account the effect of a non-saturating gate voltage only partially polarizing the ferroelectric material based on the existing remnant polarization. The model also incorporates the decay of the remnant polarization based on the time history of the FFET. A gate pulse of a specific voltage; will not put the ferroelectric material into a single amount of polarization for that voltage, but instead vary with previous state of the material and the time since the last change to the gate voltage. The model also utilizes data from FFETs made from different types of ferroelectric materials to allow the user just to input the material being used and not recreate the entire model. The model also allows the user to input the quality of the ferroelectric material being used. The ferroelectric material quality can go from a theoretical perfect material with little loss and no decay to a less than perfect material with remnant losses and decay. This model is designed to be used by people who need to predict the external characteristics of a FFET before the time and expense of design and fabrication. It also allows the parametric evaluation of quality of the ferroelectric film on the overall performance of the transistor.

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

A combination empirical/theoretical n-channel metal-ferroelectric-semiconductor field-effect transistor (MFSFET) model is developed. The model is based on a partition concept where the MFSFET ferroelectric material is segmented, allowing each individual segment to maintain an independent polarization solution as a function of applied electric field history. Modifications are made to pertinent classical metal-oxide-semiconductor field-effect transistor device equations to include the presence of ferroelectric dipole polarization charge. The model's usage of ferroelectric polarization is numerical in nature, allowing both analytic and non-analytic ferroelectric polarization models to be used. Simulation results showing the effects of the ferroelectric model parameters on MFSFET drain current are presented, including active and remnant saturated hysteresis and retention.

An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

A data capture system was developed to measure drain current as a function of gate-to-source voltage and drain-to-source voltage for Metal-Ferroelectric-Semiconductor Field-Effect Transistors (MFSFETs). Data from active hysteresis, remanent hysteresis, and retention tests were collected. The system consisted of an IBM-compatible PC equipped with an analog data acquisition system and a General Purpose Interface Bus (GPIB) controller, a voltage pulse generator, a custom MFSFET evaluation circuit, dual power supplies, and several custom software modules. Software modules were written to collect drain current data from all of the MFSFETs simultaneously, while controlling drain voltage, pulse width, and gate voltage pulse waveform sequencing remotely. System capabilities were: drain voltage from 0 to 10 volts, gate voltage from − 16 to + 16 volts, and pulse width from 1 μsec to 0.999 sec. The system allowed a high degree of flexibility and customization with regard to system inputs and facilitated com...

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.