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This paper discusses the hardware and control system design of the asymmetric cascade multilevel inverter. The asymmetric cascaded multilevel inverter structure is adopted to minimize bridges, gate drive circuits and DC power source number. Therefore, the proposed structure is able to generate higher voltage at higher speed with low switching losses and high efficiency. Selective Harmonic Elimination (SHE) based on Newton-Raphson (N-R) algorithm is developed to calculate a switching angle for a range of modulation index to control asymmetric cascade multilevel inverter. Simulation results prove that Newton-Raphson technique is more effective than genetic algorithm (G-A) and equal calculated switching angles method (ECSA). A comparison between the algorithm performance for 9-level asymmetric cascade H-bridge inverter control was evaluated and experimentally tested on FPGA-based prototypes.

In this article, Newton–Raphson optimization-based selective harmonic elimination pulse width modulation is investigated for open-loop control of flying capacitor multilevel inverter. Proposed control strategy has allowed giving up current and voltage measurement instrumentations and sensors used in case of closed loop–based control. Proposed control strategy generates accurate switching angles, capable to balance flying capacitor voltage and eliminate lower order harmonics considering load power factor variation. Algorithm performances are verified by simulation and experiments, and obtained results prove that proposed technique does effectively eliminate specific harmonics and balance capacitor voltages while getting inverter output voltage with desired number of levels.

In this paper, SHE based on Newton–Raphson algorithm is used for open-loop control of flying capacitor multilevel inverter. Without measuring current and capacitor voltages, as well as not using any controller and voltage feedback, proposed control strategy generates accurate switching angles, capable of balancing flying capacitor voltage and eliminates lower order harmonics while considering load power factor variation. Efficiency and robustness of proposed algorithm are verified by simulation and experiments. Results show that proposed method does effectively eliminate specific low-order harmonics, and inverter output voltage is resulted in low total harmonic distortion with desired number of levels and balanced capacitor voltages.

Newton-Raphson-based flying capacitor multilevel inverter modeling is investigated for capacitor voltage balancing. Without using voltage feedback, Newton-Raphson method determines the best switchi...

In this paper, a serial/parallel cascaded H-bridge (CHB) multilevel inverter is presented. The topology has the advantage of reduced number of switching devices, DC-sources and gate driver circuits. Consequently, cost and complexity are greatly minimised, providing the same number of output voltage levels even more compared to conventional structures and other topologies given in some recent literatures in which authors have proposed new topologies with reduced circuit devices count (RDC). The main contribution of this work is the ability to choose a set of harmonic order to be eliminated; in other similar works, PWM technique is only capable to minimise total harmonic distortion (THD) without eliminating selected harmonic which require a complex output filter. The feasibility and effectiveness of the proposed topology is evaluated with intensive simulation study and experimentally tested on a prototype using a field-programmable gate array (FPGA) to implement N-R algorithm for inverter selective harmonic elimination (SHE) control.

In this paper a new topology of cascaded H-bridge (CHB) multilevel inverter employing less number of switches, is presented.

This paper deals with the control design of an asymmetrical cascaded multilevel inverter. This structure therefore provides the capability to produce higher voltages at higher speeds with low switching frequency which has inherent low switching losses and high converter efficiency. Selective harmonic elimination(SHE) for asymmetrical multilevel CHB inverter control is proposed. The technique utilized in the estimation of switching angles involves Firefly Algorithm (FFA). Compared to Newton Raphson algorithm (NR), FFA is more robust and entails less computation time. Simulation results prove the effectiveness of FFA technique compared to NR algorithm. The proposed method does effectively eliminate a number of specific low order harmonics, and the output voltage is resulted in low total harmonic distortion. FFA and NR algorithm for asymmetrical cascaded H-bridge nine level inverter control are experimentally tested on a prototype using FPGA.