Search

The undoped 4-stacked Ge0.9Sn0.1 nanosheets sandwiched by double Ge0.95Sn0.05 caps without parasitic Ge channels underneath are realized by a radical-based highly selective isotropic dry etching. Highly inter-channel uniformity of the stacked GeSn nanosheets is realized by thin Ge0.9Sn0.1 (5 nm) channels and thick Ge0.95Sn0.05 caps to achieve high $\mathrm{I}_{\mathrm{\scriptscriptstyle ON}}$ . The caps are the barriers to separate the holes from the dielectrics/cap interface to reduce the surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( $ cm $^{-{3}}$ ) and heavily doped ( $\sim {2} \times {10}^{{21}}$ cm $^{-{3}}$ ) Ge at S/D can suppress the impurity scattering to increase the channel mobility and can reduce the S/D resistance, respectively. The high ${I}_{{\mathrm{\scriptscriptstyle ON}}} = {73}\,\,\mu \text{A}$ per stack (86 $\mu \text{A}/\mu \text{m}$ , normalized by the total perimeter of nanosheets) at ${V}_{\text {OV}} = {V}_{\text {DS}} = - {0.5}$ V is achieved for the device with the sheet width of 80 nm and the Lg of 80 nm. The quantum mechanical simulation shows that there is heavy hole population at the two ends of nanosheets.

The low contact resistivity with the median value of $3.1\times 10^{-{9}}\,\,\Omega \cdot \text {cm}^{{2}}$ (the lowest value of $1.1\times 10^{-{9}}\,\,\Omega \cdot \text {cm}^{{2}}$ ) is achieved by Ti metal contact to in-situ B-doped GeSn with B segregation at Ti/GeSn:B interface. The newly developed two-sheet-resistance model is used to extract the contact resistivity, considering the different sheet resistance of GeSn:B in the gap regions and under the metal layers. Sn incorporation into Ge lowers the Schottky barrier height of holes, and the heavy B doping at the Ti/GeSn:B interface reduces the hole tunneling distance. Fully compressively strained GeSn:B epitaxial layer with the bulk active [B] of $1.9\times 10^{{20}}$ cm−3 and [Sn] of 4.7% on the Ge-buffered Si substrate is successfully grown by chemical vapor deposition. The effects of B2H6 precursor on growth rate and [Sn] are investigated. Low contact resistivity is obtained using conventional B-doping in GeSn grown at a temperature as low as 305 °C and submitted to a post epitaxy thermal budget of 400 °C for 30 s.

The distinct photoresponse of the floating channels and the parasitic channels can be a signature to check the existence of the parasitic channel. The photoresponse of the sole parasitic channel mainly shows the photocurrent ( ${I}_{\text {ph}}$ ), while the photoresponse of the sole floating channels without parasitic channel shows the negative threshold voltage shift ( $\Delta {V}_{\text {T}}$ ) for nFET. The device with both the floating channels and the parasitic channel shows both photocurrent and negative threshold voltage shift under exposure.

An optical non-destructive method to check the existence of the parasitic Ge0.94Si0.06 channel underneath vertically stacked Ge0.91 Sn0.09 channels by infrared illumination is investigated. The 1310-nm and 1550-nm infrared light excite the electron-hole pairs in both the stacked floating channels and parasitic channel. On the other hand, the 2000-nm infrared light generates photo-excited carriers in the floating GeSn channels, but not in the parasitic GeSi channel since the photon energy is lower than the bandgap of Ge0.94 Si0.06. The main infrared responses of the floating channels and parasitic channel are the threshold voltage shift and the photocurrent, respectively. In addition, the distinct photoresponses of the stacked channels and parasitic channel are further confirmed by transistors without floating channels. The mechanisms behind the infrared responses are proposed. The existence of the parasitic channel can be detected by the infrared response for the advanced technology nodes, where the presence of the parasitic channel is not desired for performance enhancement and power reduction.

The undoped 4-stacked Ge 0.9 Sn 0.1 nanosheets sandwiched by double Ge 0.95 Sn 0.05 caps without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. High inter-channel uniformity of the stacked GeSn nanosheets is achieved to enhance ION by thin Ge 0.9 Sn 0.1 (5nm) channels. The carriers are separated from dielectrics by the caps to reduce the impurity and surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( ON =73μA per stack (910μA/μm per channel footprint) at V OV =V DS =-0.5V is achieved among GeSn 3D FETs for the sheet width/Lg of 80nm/80nm. The I ON per channel footprint can be improved to 1070μA/μm with the sheet width scaled to 57nm due to the large carrier population at the two ends of nanosheets. The double caps as barriers for the holes in the Ge 0.9 Sn 0.1 nanosheets decrease the low frequency noise by reducing trapping/detrapping between the GeSn nanosheets and the gate dielectrics.

To detect the existence of the parasitic channel of GAAFET for the advanced technology nodes, a non-destructively optical method is investigated. With the infrared illumination at the wavelength of 1310 nm, 1550 nm, and 2000 nm, the main infrared responses of the stacked Ge 0.91 Sn 0.09 channels and the parasitic Ge 0.94 Si 0.06 channel are ΔV T and I ph , respectively. In addition, the photoresponses between the floating channels with the parasitic channel underneath and the transistors with the sole parasitic channel distinct from each other were observed. By distinguishing the optical responses under infrared illumination, the existence of the parasitic channel can be checked non-destructively.

The undoped stacked GeSn channels without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. Heavily doped Ge sacrificial layers can reduce S/D resistance and the undoped GeSn channels can increase the channel mobility. SS=89m V /dec and $\mathrm{I}_{\mathrm{O}\mathrm{N}}=42\mu 1$ per stack ( $10.5\mu A$ . per sheet) at $\mathrm{V}_{\mathrm{OV}}\mathrm{V}_{\mathrm{DS}}=-0.5\mathrm{V}$ are achieved for the undoped 4-stacked 12nm-thick nanosheets with 120nm gate length and the width larger than 50nm. The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H202 wet etching. Both dry etching and undoped channel are essential to obtain stacked wide nanosheets with high performance.

The record low contact resistivity $(\rho_{\mathrm{c}})$ of Ti contact to Ge:B $(8.1\mathrm{x}10^{-10}\Omega-\mathrm{cm}^{2})$ is achieved by in-situ doped CVD using the high-order Ge precursor $(\mathrm{Ge}_{2}\mathrm{H}_{6})$ . The best achievable $[\mathrm{B}]_{\mathrm{act}}$ . of $7\mathrm{x}10^{20}\mathrm{cm}^{-3}$ and extended epitaxial process window are obtained using $\mathrm{Ge}_{2}\mathrm{H}_{6}$ . By optimizing the [B] and [Sn], 2% Sn addition into Ge epitaxy reaches the lowest $\mathrm{p}_{\mathrm{c}}$ of $4.1\mathrm{x}10^{-10} \Omega-\mathrm{cm}^{2}$ . Further Sn addition (4.7% and 13.2%) increases $\rho_{\mathrm{c}}$ due to reduced [B], and degrades the thermal stability. The record low resistivity $(2\mathrm{x}10^{-4}\Omega-\mathrm{cm})$ among epitaxial p-type Ge and GeSn is also demonstrated. Optimized metal etching processes ( $\mathrm{Cl}_{2}+\mathrm{BCl}_{3}$ for metal on $\mathrm{GeSn}:\mathrm{B}$ , while $\mathrm{C}1_{2}$ for metal on Ge:B) are necessary to minimize etching of GeSn:B and Ge:B, and to fabricate the test structure. A two-sheet-resistance model is used to correctly extract the $\rho_{\mathrm{c}}$ . B segregation $(> 1\mathrm{x}10^{21}\mathrm{cm}^{-3})$ at the metal/semiconductor interface enables the record low $\rho_{\mathrm{c}}$ .

Fully compressively strained GeSn quantum-well channels sandwiched by Ge sacrificial layers on 200-mm silicon-on-insulator (SOI) wafers are grown using chemical vapor deposition. The transmission electron microscopy images indicate that dislocations are confined near the relaxed Ge buffer/SOI interface, resulting in low defect densities in the stacked GeSn channels. The top Ge cap is essential to ensure that the top GeSn channel matches the other two channels during the Ge etching. Channel release is obtained by etching of the Ge sacrificial layers with optimum ultrasonic-assisted H2O2. The low thermal budget gate-stack (400 °C) and S/D parasitic resistance reduction are achieved. The first stacked 3-Ge0.93Sn0.07-channel p-gate-all-around FET with ${L} _{\text {CH}}= 60$ nm has a record high ${I}_{ \mathrm{\scriptscriptstyle ON}}=1975~\mu \text{A}/\mu \text{m}$ (per channel width) at ${V}_{\text {OV}}={V}_{\text {DS}}=-1$ V, among all GeSn pFETs. The junctionless device structure is used to simplify the process.

Although the Sn content in GeSn can reach 10% using chemical vapor deposition, the reduction of Sn content by in-situ boron doping and solid phase doping by chemical vapor deposition are observed. The Sn loss increases with the increasing boron concentration in GeSn:B alloys, while there is no Sn reduction at the similar phosphorus doping level in GeSn:P. Based on the first principle calculations, the energy for boron to place Sn in GeSn is lower than that for boron to place Ge, indicating that boron atoms prefer to occupy Sn sites. The Sn loss is more serious for boron-implanted GeSn with thermal annealing at 400 °C than in-situ boron-doped GeSn even with 500 °C thermal annealing.

Although the melting laser annealing can activate the heavily phosphorus-doped epitaxial Ge on silicon-on-insulator by chemical vapor deposition, the dopant segregation occurs after the rapid thermal process at 550 °C for 3 min even with SiO2 capping. However, the active dopant concentration can be recovered after the second laser annealing to melt Ge again due to higher P solubility in the liquid Ge than the solid Ge. The temperature distribution and the melt depth of epi-Ge is mainly determined by the laser fluence. Selective laser annealing is used to simultaneously reach low dopant concentration in the channel regions for good gate controllability, and high concentration in the source and drain regions with low parasitic resistance for the transistors. As a result, the low specific contact resistivity of $1.2\ \times \,\,10^{-8}\,\,\Omega $ cm2 using the Ni–Ge/n+Ge, the 21% current enhancement of the Ge + Si nFET as compared to the device without the selectively second laser annealing and the Ni–Ge contact, and the similar subthreshold slope after the selectively second laser annealing are achieved. The Si channel underneath the Ge channel also contributes about 38% of the total current.

Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus- doped Ge sacrificial layers over unintentionally doped Ge 0.98 Si 0.02 to form two stacked Ge 0.98 Si 0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. The parasitic Ge/Si channel underneath the Ge 0.98 Si 0.02 channels is completely removed by optimized etching. The infrared response of the parasitic channel is a non-destructive method to further confirm the removal of the parasitic channel. VT can be tuned by PMA, and ION can be enhanced by short L G . Record ION of 48 μA at V OV =V DS =0.5V and record Q (G m,max/ SS SAT ) of 8.3 at V DS =0.5V with L G = 40 nm are achieved among Ge nFETs. The results are comparable to Si nFETs.

Record [Sn]=12% and record compressive strain of 3.3% among GeSn 3D transistors to enhance the ION are demonstrated by CVD epitaxy. For the first time, in-situ Ge 0.95 Sn 0.05 caps are grown on stacked Ge0.ssSn0.12 channels to improve interface quality and separate carriers from the interface to achieve high mobility. L G is scaled down to 40nm to further boost the ION. Low channel doping and high S/D doping ([B] peak ~1E21cm-3) can suppress the impurity scattering in the channels and reduce the contact resistivity for the S/D, respectively, to reveal the intrinsic merit of the high mobility of GeSn. The stacked 3 Ge 0.88 Sn 0.12 nanosheets achieve record ION of 58µA at V OV =V DS = -0.5V and record G m,max of 172µS at V DS = -0.5V among GeSn pFETs, and the performance is comparable to mature Si FinFETs, stacked Si channels, and stacked Ge channels. The caps as barriers on the Ge0.ssSn0.12 channels decrease the low frequency noise by reducing trapping/detrapping between the GeSn channels and the gate dielectrics.

The record low contact resistivity $(\rho_{\text{c}})$ of $4.4\text{x}10^{-10}\Omega-\text{cm}^{2}$ is achieved in Ti metal contact to in-situ B-doped $\text{GeSn}$ using B $(> 1\text{x}10^{21}\text{cm}^{-3})$ and Sn $(> 12\%)$ segregations at the Ti/GeSn:B interface. Sn incorporation into Ge lowers the Schottky barrier height of holes. Increasing B doping at the $\text{Ti}/\text{GeSn}:\text{B}$ interface reduces the hole tunneling distance. Thanks to the low growth temperature (305°C) of the chemical vapor deposition using Ge2H6, the GeSn:B with the bulk active [B] of $2.1\text{x}10^{20}\text{cm}^{-3} (>> > \text{the}$ solid solubility of B in $\text{Ge}=5.5\text{x}10^{18}\text{cm}^{-3}$ ) and the bulk [Sn] of 4.9% is successfully grown. Without the needs of the previously reported Ga dopants and the high temperature annealing for dopant activation, the record low $\rho_{\text{c}}$ is achieved with all the process temperatures $\leq 400^{\text{o}}\text{C}$ .

The aim of this work is to provide a systematic and comparative study on the material characteristics and electrical contact performance for a germanium-tin (GeSn) alloy with a high percentage of Sn (8%). Thin metal films (10 nm) of Nickel (Ni), Titanium (Ti), or Platinum (Pt) were deposited on Ge 0.92 Sn 0.08 layers and subsequently annealed at different temperatures ranging from 300°C up to 500°C. Various experimental techniques were employed to characterize the metal morphology and the electrical contact behavior, with the intention of identifying the most promising metal candidate, in terms of low sheet resistance and low surface roughness, considering a low formation temperature. The investigations carried out show that for nano-electronic contact applications, nickel-stanogermanide (NiGeSn) turns out to be the most promising candidate among the three different metals analyzed. NiGeSn presents low sheet resistance combined with low formation temperatures, below 400°C; PtGeSn shows better thermal stability when compared to the other two options while, Ti was found to be unreactive below 500°C, resulting in incomplete TiGeSn formation.

The tensily strained high Ge content (85%) GeSi multi-channels stacked on the Si channel with channel size optimization have good subthreshold behaviors (SS, DIBL, and $\mathrm{I}_{\mathrm{off}}$ ), and meanwhile maintain high $\mathrm{I}_{\mathrm{on}}$ . By narrowing GeSi channel, the bandgap of the GeSi can be increased by quantum confinement and the short channel effect can be suppressed. This also causes the more positive $\mathrm{v}_{\mathrm{t}}$ for GeSi than Si. As a result, $\mathrm{SS}=76\mathrm{mV}/\mathrm{dec}, \mathrm{DIBL}=36\ \mathrm{mV}/\mathrm{V}$ can be achieved due to the benefit of superior subthreshold behaviors of the Si channel underneath. The $\mathrm{I}_{\mathrm{on}}/\mathrm{I}_{\mathrm{off}}$ is improves to be 1.2E7. The high $\mathrm{I}_{\mathrm{on}}=44\mu \mathrm{A}$ perstack at $\mathrm{Vov}= \mathrm{V}_{\mathrm{DS}}=1\mathrm{V}$ , is contributed from both the GeSi and Si channels, and it is further enhanced to $46\ \mu \mathrm{A}$ by the external strain. The relatively low flicker noise indicates that the novel structure can mitigate the reliability issue of GeSi channels by the highly reliable Si channel underneath.

The phosphorus incorporation by chemical vapor deposition and activation by laser annealing reaches the electron concentration of $\sim 3\times 10^{20}$ cm $^{-3}$ . The pulsed laser not only activates the phosphorus but also produces the biaxial tensile strain of 0.35%. With the nickel germanide contact, the specific contact resistivity reaches as low as $1.5\times 10^{-8}~\Omega $ -cm2 by greatly reducing the tunneling distance. Due to 4% misfit between Ge and Si, there are still misfit dislocations near the Ge/Si interface. The misfit dislocations at the Ge/Si interface lead to the ideality factor of 1.6 for the Ge/Si hetero-junction diode with ON/OFF ratio of $\sim 1\times 10^{5}$ .

High material quality of compressively strained GeSn quantum wells sandwiched by Ge barriers on 200mm SOI wafers by CVD are confirmed by reciprocal space mapping (RSM), X-ray diffraction (XRD), and photoluminescence (PL). Due to the growth of relaxed Ge buffer on SOI, the misfit dislocations are confined near the Ge buffer/SOI interface, yielding low defect densities in the stacked GeSn channels. The low selectivity of Cl 2 /HBr between GeSn and Ge, makes it impossible to perform the channel release for stacked devices by etching away the Ge barriers. The channel release by optimum H 2 O 2 etching for stacked two GeSn nanowires with [Sn] = 6%, hole concentration = 1.3E19cm−3, and channel length (L CH ) = 150nm yields I on per channel width = 1400μA/μm for junctionless (JL) devices. Further improvement of Ion to reach record value of I on = 1850 p.A/p.m is achieved by increasing [Sn] to 10%, hole concentration to 6.7E19cm−3 and reducing the L CH to 60nm. Additional 6.3% enhancement of I on is obtained by additional uniaxial compressive strain using wafer bending. The best SS values of 84mV/dec and 88mV/dec are obtained for single-wire and stacked two-wire channels, respectively. JL has lower low frequency (LF) noise than inversion mode (IM) due to its bulk conduction nature. The mobility of JL and IM is dominated by impurity scattering and phonon scattering, respectively, according to the temperature dependence.

In this article we provide a comparative and systematic study on contact formation for germanium-tin (GeSn) thin films containing a high percentage of Sn (8 at.%). 20 nm of Nickel (Ni), Titanium (Ti), or Platinum (Pt) was deposited on Ge0.92Sn0.08 layers grown on Ge substrates, and subsequently annealed between 300 and 500 °C to form stanogermanide alloys. Several experimental techniques were employed to characterize the material and the electrical contact behaviour, with the purpose of identifying the most promising stanogermanide contact candidate, in terms of low sheet resistance, low surface roughness and low formation temperature. Among these three different metals we found that, for nanoelectronic applications, nickel-stanogermanide (NiGeSn) was the most promising candidate based on a low sheet resistance combined with a low formation temperature, below 400 °C. PtGeSn showed better behaviour in terms of thermal stability compared with the other two options, while Ti was found to be relatively unreactive under these annealing conditions, resulting in poor TiGeSn formation. For the lowest resistance stanogermanide contact generated, namely NiGeSn formed at 300 °C, detailed lattice resolution Transmission Electron Microscopy imaging, combined with fast Fourier transformation analysis, identified the formation of the Nix-1(GeSn)y-1 phase.

The Si FinFET architecture has been used in mass production in the industry for several technology nodes. Recently, the horizontal stacked channel GAAFET becomes a good candidate to achieve better power-performance properties than FinFETs in a certain area due to the promise of well controlled epitaxy, selective etching, and GAA nature. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate the CVD grown, vertically-stacked strained GeSi channels for nGAAFETs and GeSn channels for pGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to improve the electrostatics for Ge-based channel GAAFETs while the stacked GeSn pGAAFETs has record high ION and Gm with highly competitive subthreshold behaviors among GeSn pFinFETs and pGAAFETs. In addition, record low contact resistivity (4.4x10-10 ohm-cm2) to Ge using in-situ B and Sn incorporation by CVD is also demonstrated with low thermal budget (≦400oC) and without any Ga doping. The Ge/Ge0.85Si0.15 and Ge/Ge0.91Sn0.09 multi layers are epitaxially grown on SOI substrates by CVD. Ge buffer layers and sacrificial layers are not only used to be selectively etched in preference to GeSi and GeSn to form the vertical stacked GeSi channels and GeSn channels, but also to stress both GeSi N-channels tensily and GeSn P-channels compressively, respectively. The high temperature anneal for the buffer can confine the dislocations at the bottom of Ge buffer and reduce the defect density in the channels to improve the device performance. The heavy in-situ doping of source and drain, post metal annealing, laser annealing for nFETs, and NiGe/ PtGeSn formation can reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi and GeSn channels. For GeSi nFETs, rhe △Ec between GeSi and Si is nearly zero. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. The Vt difference between GeSi and Si can be tuned by the channel size optimizing. By narrowing the GeSi channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive Vt for GeSi than Si is observed. The Si channel turn on first with good SS=76mV/dec and DIBL=36mV/V due to low Dit and good short channel control. Ioff is also dramatically reduced and the Ion/Ioff are improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow GeSi channels. The improved flicker noise also indicates the enhanced reliability. For GeSn pFETs, the {111} plane has high mobility, low dangling bond density, low Dit, and better gate control than the rectangular channel. Vertically stacked triangular Ge0.91Sn0.09 pGAAFETs with compressive strain of ~2% in the channel and low surface roughness are achieved by orientation dependent etching on natural etching stop {111} plane by the optimized etching process. The 22% reduction of SSlin=84mV/dec, 50% improvement of ION=120mA/mm at VOV=VDS=-0.5V, and 71% improvement of Gm=312mS/mm at VDS=-0.5V are achieved as compared to our previous work of 3 stacked Ge0.93Sn0.07 nanosheets. The device has the record ION of 19.3mA per stack at VOV= VDS=-0.5V and record Gm,max of 50.2mS per stack at VDS=-0.5V with competitive subthreshold behaviors among GeSn pFinFETs and pGAAFETs. For the p-type contact resistivity (ρc) reduction, B (>1x1021cm-3) and Sn (>12%) segregations at the Ti/GeSn:B interface are used to reduce the hole tunneling distance and the Schottky barrier height of holes, respectively. The GeSn:B is grown by CVD using Ge2H6, SnCl4, and B2H6 in H2 ambient at ≦320oC. Due to the Sn segregation, there is no need to grow high-[Sn] GeSn layer for the ρc reduction, which makes the pseudomorphic growth of the compressively strained GeSn possible. After metal deposition at elevated temperature and 400oC annealing, the ρc of 4.4x10-10 ohm-cm2 is achieved. Ge nGAAFETs, GeSn pGAAFETs, and the S/D with extremely low contact resistivity fabricated by CVD growth and optimized process are compatible with Si technologies and becomes promising candidates for CMOS applications in the future technology nodes. Acknowledgements: The MOST (107-2218-E-002-044-, 107-2622-8-002-018) and MOE (NTU-CC-108L891701), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.

It is the first time that CVD-grown GeSn channels with low thermal budget of 400°C significantly outperforms the Ge channel processed at high thermal budget of 550°C. Low thermal budget is necessary to prevent the Sn loss during the process. Note that only MBE-grown GeSn had large mobility reportedly in the past. Even with high Sn content (9%), the strong photoluminescence is observed from GeSn layers on Ge buffer on 300mm Si (001), indicating the high crystalline quality by CVD epitaxy. Ge cap with significant Δ Ev at Ge/GeSn interface can ensure the gate stack quality, and reduce the scattering of holes in the GeSn quantum wells by oxide/interface charges and surface roughness. However, the mobility is degraded by thick cap due to low hole population in the GeSn wells. The ∼7% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain of ∼0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at both high and low inversion carrier density, indicating that the mobility is dominated by phonon scattering. On the contrary, Ge channels are dominated by Coulomb scattering at low inversion carrier density, which has decreasing mobility with decreasing temperature. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.

The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.

Pseudomorphic Ge 0.91 Sn 0.09 on Ge on Si with strong photoluminescence and low defect density is used for p-MOSFET channels. The mobility of Ge 0.91 Sn 0.09 Quantum Well p-MOSFETs are higher than control Ge p-MOSFETs due to hole population in the GeSn wells. The 7.5% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain (∼0.11%). The highest [Sn] of 9% in the channels grown by CVD, Pt SB S/D, high I on /I off ratio, and strain-enhanced mobility are obtained in this work.

The electron concentration of 3×1020 cm−3 in phosphorus-doped Ge is obtained by in-situ chemical vapor deposition doping and laser annealing. The laser annealing effectively improve the crystallinity in the Ge layer. The pulse laser not only activates the phosphorus, but also produces the biaxial tensile strain. With the nickel germanide contact, the contact resistivity is as low as 1.5×10−8 Ω-cm2 by greatly reducing the tunneling distance. The misfit dislocations at the Ge/Si interface lead to the ideality factor of 1.6 for the Ge/Si hetero-junction diode with on/off ratio of ∼1×105.

A Ge/GeSn/Ge single quantum well with 5% Sn content was grown by chemical vapor deposition on a Si substrate using Ge2H6 and SnCl4 precursors. External biaxial tensile strain was mechanically applied to the Ge/Ge0.95Sn0.05/Ge quantum well for the photoluminescence measurement. Note that the Ge0.95Sn0.05 layer is still under compressive strain due to the large internal compressive strain of the GeSn, although the external bending produces the tensile strain. The direct emission of tensily strained Ge buffer shifts toward lower energy, while the direct emission of pseudomorphic Ge0.95Sn0.05 quantum well does not have significant shift. The strain-induced energy changes of heavy holes and light holes in the Γ valley are extracted by fitting the photoluminescence spectra. Based on the nonlocal empirical pseudopotential method and the model-solid theory, a type-I band alignment is used for the fitting of photoluminescence spectra. The experimentally extracted band edge shifts from the photoluminescence measurement have good agreement with theoretical calculation.

The SiGe pFINFETs and Si nFINFETs have been used in the industry. To further improve the performance and reduce power consumption of the transistors, tremendous works have been spent on GAAFETs with higher mobility channel materials such as Ge. Recently, CVD grown strained-GeSn on Ge/Si was reported to have larger hole mobility than Ge, due to Sn incorporation in Ge and the compressive strain response. Good crystalline quality and strong PL are achieved from CVD-grown fully strained GeSn single layer and multi-layers on relaxed Ge buffers on Si. Due to the growth of relaxed Ge buffer on Si, the misfit dislocations are confined near the Ge buffer/Si interface, yielding low defect densities in the stacked GeSn channels. Gate stacks with low thermal budget of 400oC for GeSn with low Dit of IL, high-k material and low dispersion is realized to prevent Sn segregation and diffusion. The high mobility (~418cm2/V-s) of the CVD-grown fully compressively strained GeSn QW pMOSFETs with schottky S/D is achieved by the optimized Ge cap thickness and gate stack process. The external uniaxial strain can further reduce the hole effective mass and enhance the mobility. For the vertically stacked GeSn nanowire pGAAFETs, circular GeSn channels and the high inter-channel uniformity with low roughness are obtained by Ge sacrificial layer on the top GeSn layer and ultrasonic-assisted etching process. After the fin formation, the biaxial strain is then transformed into uniaxial strain and it gives a smaller hole effective mass than that giving by biaxial strain. The strain is then further enhanced by microbridge structure after the channel release process. Optimization for in-situ doped GeSn S/D and PtGeSn/PtGe formation to decrease parasitic resistance are also achieved. The optimized etching process and GAA structure make the SS in the lower side of GeSn as compared to others. The stacked GeSn JL pGAAFETs with 3 channels and LCH=60nm has record high Ion=1975μA/μm (normalized by channel footprint) among all published GeSn pFETs. For Ge nGAAFETs application, junctionless GAAFETs with S/D resistance reduction, high drive current and high Ion/Ioff are achieved. After the CVD growth, the 1st laser annealing with the laser fluence of 0.14 J/cm2 is performed to achieve the Hall electron concentration of 3x1020 cm-3 in the epi-Ge. The temperature distribution and the melting depth of epi-Ge can be determined by the laser fluence, which is carefully measured and is consistent with the simulation results. However, the electron concentration is reduced to 2.4x1019 cm-3 after the RTO at 550oC for 3 min in gate stack process. Due to higher P solubility in the liquid Ge than the solid Ge, the selective 2nd laser annealing in S/D region can re-melt Ge and the active dopant concentration can be recovered. The 2nd selective laser annealing simultaneously reaches low dopant concentration in the channel regions for good gate controllability, and high concentration in the S/D regions with low parasitic resistance. With selectively 2nd laser annealing and NiGe contact formation, the contact resistivity can be reduced to 1.2x10-8 Ω-cm2, the current of the Ge+Si nFET can be enhanced by 21% with Ion/Ioff = 2×106, and the SS remains nearly the same. The Si channel underneath the Ge channel also contributes about 38% of the total current. GeSn pGAAFET and Ge nGAAFET fabricated by CVD growth and optimized process are compatibile with Si technologies and becomes the promising candidates for CMOS applications in the future technology nodes to further extend the Moore’s law. The support of MOST of Taiwan (No. 106- 2221-E-002 -197 -MY3, 106-2221-E-002 -232 -MY3, 106-2622-8-002 -001 -) and NDL are highly acknowledged.

To boost the drive current of transistor and/or reduce power consumption, new channel materials with high carrier mobility such as SiGe/Ge/GeSn have been considered as the promising candidates for the continuous scaling of Moore’s law. SiGe channel have been used in the industry for pFETs, and the addition of Sn into Ge to further enhance the hole mobility is the attractive area of research. The strained GeSn on Ge/Si grown by CVD provides higher hole mobility than Ge due to the biaxial compressive strain and effective mass reduction by Sn incorporation. To ensure the gate stack quality, and reduce the scattering of holes in the GeSn channel by oxide/interface charges and surface roughness, the epitaxy Ge cap with significant ΔEV has been integrated. The Ge-cap/GeSn/Ge quantum well structure with [Sn] up to 9% is grown by CVD on SOI, and the low temperature process is used to fabricate the devices without Sn segregation/diffusion. By optimizing the cap thickness and thermal budget of gate stack formation, the high mobility (~430cm2/V-s) of the CVD-grown GeSn quantum well p-MOSFETs is achieved to demonstrate the possible integration of GeSn material in industrial fabrication. The high hole mobility and reduced low frequency noise are obtained using quantum well structures with optimal cap thickness of 1 nm. The Ge cap also reduces the defects formed by Sn diffusion into dielectric. To improve the gate controllability and increase drive current with same footprint, the gate-all-around (GAA) pFETs using GeSn channels will be reported. For Ge nFETs, junctionless GAAFETs with high drive current and high Ion/Ioff are investigated. To boost the drive current and to suppress short channel effects, the optimized doping profile is needed. Since the subthreshold characteristic of JL FET is highly related to the channel cross-section and channel doping, the channel doping of 1.2x1019cm-3 is used. However, it is too low for the S/D region, and heavily doped Ge (~1.2x1020 cm-3) is used in S/D by selective laser annealing with NiGe contact to reduce the parasitic resistance. The optimized doping profile is achieved by selective laser annealing in the S/D, with Pt as hard mask on channel region to reflect the laser light in the channel. The demonstrated Ge JL nGAAFET with fin width (Wfin) down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/μm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. Note that the increasing mobility with increasing temperature indicates the impurity scattering is dominant. With Ge/GeSn CVD growth and optimized process, GAA transistors with high mobility channels can be realized as promising candidates for future CMOS scaling.