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Electrical characterization of AlGaN/GaN heterojunctions isolated by Ar-implantation identified three conduction regimes. These include an Ohmic regime below 100 V associated with conduction across the implanted area itself as well as an exponential regime above 400 V associated with a conduction across the buffer or buried interfaces with the substrate. While the extraction of activation energies found an average of roughly 0.85 eV for the Ohmic regime, activation energies above 400 V were consistent with a Poole-Frenkel conduction mechanism. Variations in epitaxial structure, lateral and vertical electric field enabled the distinction between a conduction path in the top layers of the structure and a conduction path which is at least partially vertical across the structure. In addition, time-dependent measurements showed a capacitive effect for conduction across the buffer at room temperature. Having identified the performance limiting conduction path through the buffer layers, these experimental results can also be used as a tool for epitaxy assessment very early on in the production process.

To improve 20nm FD-SOI pMOS transistor performances, salicide process must be optimized on SiGe source&drain. In this paper, we propose an investigation on Ni and Pt/Si1-xGex (x=0.15, 0.3) systems. In a first part, process window is studied to determine thermal budget domain where the less resistive phase is stable morphologically and thermically. Solid state reactions in terms of phase sequence, thermal stability and morphology have been examined. At high temperature, two kinds of degradations have been observed. In Ni case, Ge out diffusion leads to the film agglomeration. In Pt case, grain coalescence degrades germanosilicide film. In a second part, contact resistivity has been extracted on lateral germanosilicides thanks to new designed structures. After a validation on Pt/Si system, RC extraction has been carried out on Si1-xGex substrate up to 30% of Ge. RC seems to be better with Pt compared to Ni with the same conditions of process optimizations.

International audience; We present experimental and simulated J-V characteristics of Metal/Insulator/Semiconductor (MIS) junctions aiming at improving the contact resistivity for advanced CMOS nodes. We show that an Atomic Layer Deposition (ALD)-based Al2O3 process may induce a native silicon oxide regrowth leading to an additional tunneling resistance in series. A modelling-based analysis of Metal/Insulator/Insulator/Metal (MIIS) contacts, including the potentially beneficial interfacial dipole, provides a new outlook on high-kappa/SiO2 bilayers for low resistivity contacts.

Low temperature epitaxy is today necessary in thin film Fully Depleted SOI (FDSOI) MOSFETs in order to obtain good quality accesses. Indeed, high temperature process has been shown to be detrimental for the growth of raised sources and drains (RSD) on thin films, as dewetting of the starting film and/or islanding of the epitaxial layer can occur [1]. Besides, low temperature epitaxy is also a key enabler for 3D sequential CoolCubeTM integration, where the 3D fabrication of devices one on top of the other and on the same substrate requires low thermal budget processes (typically T Surface preparation is one of the most critical steps as it directly influences the subsequent epitaxy. Presence of contaminants (C, O, F mostly) can lead to lower growth rates and/or morphological defects in the epitaxial layer. High temperature H2 pre-bake (T>1000°C) yields H-passivated and contaminants-free surfaces, yet it is not compatible with thin films technologies. Nevertheless, native oxide can be removed using a “HF-last” wet clean as well, allowing a reduction in the pre-bake temperature necessary for a good surface preparation (750°C-775°C in [3]). Besides, native oxide can also be removed using the Siconi process, where a NH3/NF3 dry plasma transforms the oxide into a salt which can then be sublimated at temperatures below 200°C [4]. In our work, we show the influence of wet and dry cleans on the quality of the subsequent raised sources and drains epitaxy, the best surface being obtained when using both processes successively (Figures 1a to 1c). Using the optimum wet and dry cleans combination, the thermal budget of the H2 bake could then be reduced from two steps (650°C 2min + 750°C 30s) down to 650°C 2min only. Although higher concentration of interfacial contaminants is to be expected with a lower thermal budget H2 bake, we found no morphological degradation after our standard 650°C epitaxy of SiGe:B raised sources and drains. (Figure 1d). Additionally, equivalent electrical performances were obtained with the lower thermal budget bake (Figure 2). In a second time, the epitaxy temperature was also decreased. High order silanes (e.g. Si3H8, Si5H12) have been proposed to cope with the drastic Si growth rate decrease at low temperatures [5-6]. However, these liquid precursors are very costly, making them less appealing for industrial use. Meanwhile, use of germane (GeH4) and diborane (B2H6) also yields higher growth rates thanks to the preferential desorption of H atoms on B and Ge surface sites. Hence, SiGe:B epitaxy at 500°C was evaluated structurally in a previous work [7]. At such a low temperature, straightforward co-flow selective epitaxial growth (SEG) using chlorinated gases (SiH2Cl2 or HCl) is not possible anymore. Selectivity is then achieved using a deposition/etch (D/E) approach using Si2H6, GeH4 and B2H6 as growth precursors and HCl for the selective etching of polycrystalline materials on dielectrics. Good quality 2D epitaxial layers can thus be obtained with full selectivity over the buried oxide and the nitride gate spacer (Figure 1e). We also show that doubling the number of cycles (i.e. to D/E/D/E strategy) yields smoother access regions, yet at the cost of the selectivity (Figure 1f). Use of more reactive chlorine gas is therefore proposed to obtain desired selectivity at 500°C. Finally, for the first time, pMOSFETs on thin SOI (tSi=11nm) substrate were fabricated using the new 500°C D/E recipe for SiGe:B raised sources and drains and functional transistors were obtained (Figure 3). A thorough electrical analysis of these devices (e.g. access resistance, mobility) will be provided in this work. [1] Y. Ishikawa et al., Appl. Surf. Sci. 90, 11-15, 2002. [2] P. Batude et al., Proceedings of 2015 VLSI Technology Symposium, 48-49, 2015. [3] A. Abbadie et al., Appl. Surf. Sci. 225, 256-266, 2004. [4] M. Labrot et al., Appl. Surf. Sci. 371, 436-446, 2016. [5] A. Gouyé et al., Appl. Phys. Lett. 96, 063102, 2010. [6] J. C. Sturm et al., ECS Trans. 16 (10), 799-805, 2008. [7] J-M. Hartmann et al., ECS J. Sol. State Sci. Technol. 3, 382-390, 2014. Figure 1

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