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A SiC MOSFET fabricated on a thin 15R-SiC layer on top of a 4H-SiC would benefit from both the higher inversion channel mobility of 15R-SiC and higher bulk mobility of 4H-SiC. In this work, a method based on Al implantation followed by UV laser annealing (UV-LA) to form 15R-SiC on 4H is shown. Evaluation of crystal quality and SiC polytype identification are performed by Raman spectroscopy. We show that UV-LA is able to grow 15R-SiC and cure the crystal damaged by ion implantation until a level close to the pristine substrate. This opens new perspectives for fabrication of SiC n-type MOSFETs.

Three-dimensional (3D) CMOS technology encourages the use of UV laser annealing (UV-LA) because the shallow absorption of UV light into materials and the process timescale typically from nanoseconds (ns) to microseconds (us) strongly limit the vertical heat diffusion. In this work, us UV-LA solid phase epitaxial regrowth (SPER) demonstrated an active carrier concentration surpassing 1 x 10^21 at./cm^-3 in an arsenic ion-implanted silicon-on-insulator substrate. After the subsequent ns UV-LA known for improving CMOS interconnect, only a slight (about 5%) sheet resistance increase was observed. The results open a possibility to integrate UV-LA at different stages of 3D-stacked CMOS., Comment: Accepted manuscript for Applied Physics Express (IOP science)

UV nanosecond pulsed laser annealing (UV-NLA) is demonstrating clear benefits in the emerging 3D-integrated electronic devices, where the allowed thermal budget is strictly limited to preserve underlying device performance. A possible drawback of UV-NLA is that melting a solid substrate covered by a dielectric layer, which can be found in typical CMOS device structures, induces wrinkles on the surface and may be an issue for subsequent processes. In this study, UV-NLA is performed in thermally-grown SiO2/Si structures to systematically investigate the formation of wrinkles. A classical analytical model adopted from literature shows a good agreement with our experimental results if a fitting coefficient is involved. Interestingly, its value is rapidly increasing for a thinner (roughly less than 50 nm) SiO2 film, whereas it becomes closer to unity for a thicker (roughly greater than 50 nm) SiO2 film. This might infer a possible discrepancy of the material properties taken from literature and those of real industrial thin SiO2 films. The impact of the as-grown SiO2 film stress on the growth of wrinkles is also investigated, improving the statistics of the measurements. The results do not show any significant impact possibly because of the degree of the as-grown SiO2 film stress being negligible compared to the SiO2 shear modulus.

The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds ({\mu}s) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices., Comment: 25 pages, 20 figures, review paper

International audience

Highly strained SiGe-on-insulator (SGOI) channels are desired for p-type transistor performance enhancement. A fine characterization of the crystal quality as a function of depth of such films would be of great interest as the SiGe crystal quality influences its electrical properties. The crystal quality of SGOI films fabricated by the condensation technique is measured by the Medium Energy Ion Scattering technique using the channeling effect. Indeed, the presence of structural defects such as dislocations is associated with atoms displaced from their normal lattice sites that contribute as a consequence to the scattering yield in channeling conditions. This paper compares the crystal quality of low Ge content and high Ge content SGOI films fabricated by condensation. It is shown that the SiGe crystal is degraded in the top part of the film, both before and after condensation, and that the presence of Ge, even at low fraction, at the interface with the buried oxide, induces crystal damage in the immediate vicinity of the interface. We finally highlight that, except close to the interfaces with oxide films, SGOI films fabricated by condensation feature high crystal qualities up to 57% Ge concentration and 2% compressive strain.

International audience; The fabrication of ultrathin compressively strained SiGe-On-Insulator layers by the condensation technique is likely a key milestone towards low-power and high performances FD-SOI logic devices. However, the SiGe condensation technique still requires challenges to be solved for an optimized use in an industrial environment. SiGe oxidation kinetics, upon which the condensation technique is founded, has still not reached a consensus in spite of various studies which gave insights into the matter. This paper aims to bridge the gaps between these studies by covering various oxidation processes relevant to today's technological needs with a new and quantitative analysis methodology. We thus address oxidation kinetics of SiGe with three Ge concentrations (0%, 10%, and 30%) by means of dry rapid thermal oxidation, in-situ steam generation oxidation, and dry furnace oxidation. Oxide thicknesses in the 50 angstrom to 150 angstrom range grown with oxidation temperatures between 850 and 1100 degrees C were targeted. The present work shows first that for all investigated processes, oxidation follows a parabolic regime even for thin oxides, which indicates a diffusion-limited oxidation regime. We also observe that, for all investigated processes, the SiGe oxidation rate is systematically higher than that of Si. The amplitude of the variation of oxidation kinetics of SiGe with respect to Si is found to be strongly dependent on the process type. Second, a new quantitative analysis methodology of oxidation kinetics is introduced. This methodology allows us to highlight the dependence of oxidation kinetics on the Ge concentration at the oxidation interface, which is modulated by the pile-up mechanism. Our results show that the oxidation rate increases with the Ge concentration at the oxidation interface. Published by AIP Publishing.

The demand for higher speed and lower power consumption ICs has motivated research for higher mobility channel materials (1). Compressively strained SiGe is known to feature higher hole mobility than Si and is largely compatible with the Si CMOS manufacturing platform. Besides, the FDSOI transistor architecture allows power consumption reduction (2), thus making SiGe-On-Insulator (SGOI) channels promising. SGOI layers can be fabricated by the so-called condensation technique, which is based on concurrent Si selective thermal oxidation of SiGe and SiGe composition homogenization by Si and Ge interdiffusion (see Figure 1) (3). Therefore, a sound understanding of kinetics of oxidation and interdiffusion of SiGe is required to develop optimized SGOI structures. SiGe dry oxidation rate has been reported to be higher (4) than or equal (5)(6) to the one of Si. It therefore remains unclear. Few groups investigated Rapid Thermal Oxidation (RTO) (4) while most of them looked at furnace oxidation. Moreover, most studies only considered the initial Ge content to compare oxidation kinetics. Indeed, the Ge concentration below the SiGe-oxide interface is strongly varying with time because of two mechanisms: firstly, the Si-selective oxidation of SiGe tends to pile-up Ge below the oxidizing interface; and secondly, interdiffusion of SiGe favors homogenization of the layer (6). This paper focuses on the oxidation rate of SiGe in regards to the varying Ge concentration in the SiGe layer for various oxidation conditions. Thick (> 20 nm) SiGe layers with either 10% or 30% Ge concentrations were epitaxially grown on bulk Si wafers. Oxidation was performed by RTO in 1 atmosphere of pure O2, with different oxidation temperatures and durations. Oxide thickness and SiGe composition versus depth were measured by Spectroscopic Ellipsometry and X-Ray Reflectivity, and by Secondary Ion Mass Spectroscopy respectively. Figure 2 shows the Ge concentration profile below the oxide. A rapid creation of a pile-up layer is observed at all temperatures. Then, three regimes of evolution of the pile-up layer are distinguished: the Ge concentration at the oxidizing interface (a) increases, (b) is constant, and (c) decreases. The regime of evolution of the pile-up layer is determined by a competition between the oxidation speed and the interdiffusion speed. As schematically illustrated Figure 3, the interdiffusion speed overcomes the oxidation one at higher temperatures because the activation energy of interdiffusion in SiGe ([4,5] eV (7)) is well above the one of SiGe oxidation ([2,2.6] eV (4)). Phrased in a different way, the temperature dependence of interdiffusion is higher than the oxidation one. Figure 4 shows the oxide thickness versus the oxidation duration for dry RTO at 900°C, 1000°C and 1100°C. A higher oxidation rate is observed for SiGe compared to Si for all temperatures. Then, to highlight the effect of the Ge concentration at the oxidizing interface, we fitted the curves to extract oxidation rates for each oxidation conditions. We define the Growth Rate Enhancement (GRE) as the ratio of the oxidation rate of SiGe to the one of Si at a given oxide thickness and for identical oxidation conditions. It is indeed important to highlight that comparing oxidation rates at the same oxide thickness is mandatory: if we want to examine the effect of Ge on the oxidation rate, we have to take into consideration the fact that the oxidation rate also decreases with the oxide thickness. Such an approach allows us to freeze the system and to find more easily correlations. We report on Figure 5 four GRE values extracted from our data versus the Ge concentration at the oxidizing interface. We thus observe that the higher the Ge concentration at the oxidizing interface is, the higher the GRE tends to be. We thus showed that Ge redistribution by interdiffusion during SiGe oxidation can follow different regimes. We also evidenced that for dry RTO conditions, the higher the Ge concentration at the oxidizing interface is, the higher the GRE is. Understanding the interdependence of these two mechanisms is essential to get an accurate picture of the condensation process. Therefore, data for dry RTO will be completed and an in-depth discussion will be led. A similar study will also be conducted for a wet oxidation process called In-Situ Steam Generation (ISSG). (1) Pillarisetty, R., Nature 479.7373 (2011): 324-328. (2) Weber, O., et al., VLSIT IEEE, 2014. (3) Tezuka, T., et al., JJAP 40.4S (2001): 2866. (4) Spadafora, M., et al. MSSP 8.1 (2005): 219-224. (5) LeGoues, et al., APL 54.7 (1989): 644-646. (6) Long, E., et al., PSS (a) 209.10 (2012): 1934-1939. (7) Kube, R., et al., JAP 107.7 (2010): 073520. Figure 1