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International audience; The digital economy has now a widespread impact on the whole economy and leads companies to transform and adopt new competition rules. The objectives of this paper are (1) to analyze these evolutions; and (2) to understand the role of information systems in these changes. The authors have investigated two opposite environments: a pure Internet player selling a SaaS offering, and a traditional business that distributes products through a physical network of thousands of outlets. Our results show that both the Internet players and traditional companies experience changes in the industry value chain, a growing importance of services, and develop new business models focused on an extended value proposition and cooperation with customers. The role of information systems is characterized by the evolution of the IT infrastructure, the expansion of inter-organizational information systems and digital platforms and the development of new IT capabilities.

International audience; New many-core architectures such as the Kalray MPPA-256 provide energy-efficiency and high performance for embedded systems. However, to take advantage of these opportunities, careful manual op-timizations are required. We investigate the automatic streamization of image processing applications, implemented in C on top of a dedicated API, onto this target accessed through the ΣC dataflow language. We discuss compiler and runtime design choices and their impact on perfor-mance. Our compilation techniques are implemented as source-to-source transformations in the PIPS open-source compilation framework. Ex-periments show lowest energy consumption on the Kalray MPPA target compared to other hardware targets for a range of 8 test applications.

International audience; This paper provides both theoretical and experimental evidence for the existence of an Energy/Frequency Convexity Rule, which relates energy consumption and CPU frequency on mobile devices. We monitored a typical smartphone running a speci c computing-intensive kernel of multiple nested loops written in C using a high-resolution power gauge. Data gathered during a week-long acquisition campaign suggest that energy consumed per input element is strongly correlated with CPU frequency, and, more interestingly, the curve exhibits a clear minimum over a 0.2 GHz to 1.6 GHz window. We provide and motivate an analytical model for this behavior, which ts well with the data. Our work should be of clear interest to researchers focusing on energy usage and minimization for mobile devices, and provide new insights for optimization opportunities.

Nous allons maintenant etudier une entreprise americaine emblematique d’une tendance forte des entreprises de l’economie numerique: Salesforce.com. Cette entreprise californienne s’est resolument orientee des son origine (1999) vers le «Software as a Service» (SaaS). Cette entreprise pionniere a propose dans le domaine des logiciels de management de la relation client de fournir a ses clients un service et non un logiciel. Apres une presentation de la societe et de son environnement, nous allons etudier, comme nous l’avons fait pour REXEL, la place de la coproduction de valeur dans sa strategie.

La revolution numerique transforme profondement les regles de l'economie et bouleverse les regles du jeu strategique. Au cœur de ces evolutions, les systemes d'information peuvent aider les entreprises a initier et developper de nouveaux business models ou l'attention constante au client, la coproduction de valeur avec les partenaires et l'enrichissement de l'offre par de nouveaux services sont les enjeux cles. Au travers de deux cas d'etude d'entreprises, l'une emblematique du monde numerique, l'autre appartenant au secteur traditionnel de la distribution de produits electriques, les auteurs analysent les facteurs cles de l'economie numerique et expliquent les menaces et defis de ce nouvel environnement competitif. Au-dela de la diversite des situations, l'ouvrage met en evidence les strategies des organisations pour s'adapter au monde numerique et le role central des systemes d'information dans cette evolution.

Le groupe Rexel est l’un des leaders mondiaux de la distribution de materiels electriques basse tension et courants faibles. Apres une periode difficile due a la crise economique (CA en baisse de 17,9 % en 2009), Rexel a reussi en 2010 a redresser ses ventes, a augmenter d’un point sa rentabilite et a reduire sa dette de 128 M€. En 2010, il a realise un chiffre d’affaires de 12 Mds€, est present dans 36 pays avec 40 enseignes commerciales et compte 28 000 collaborateurs.

Cette etude sur les nouvelles regles de l’economie numerique, l’evolution des business models et l’adaptation des systemes d’information nous permettent de degager un ensemble de resultats et de questions complementaires.

Dans les annees 1990, les entreprises ont effectue des investissements massifs sur ce que l’on appelait a l’epoque les «nouvelles technologies de l’information»5. Attirees par les potentialites de ces technologies, elles ont ainsi innove: beaucoup se sont transformees, certaines ont disparu, et dans le meme temps on a vu arriver de nouveaux acteurs nes avec ces technologies et qui ont directement fonde leur modele d’affaire sur une conception radicalement differente du rapport de l’organisation a son ecosysteme.

International audience; We present an API-based compilation strategy to optimize image applications, developed using a high-level image processing library, onto three different image processing hardware accelerators. We demonstrate that such a strategy is profitable for both development cost and overall performance, especially as it takes advantage of optimization opportunities across library calls otherwise beyond reach. The library API provides the semantics of the image computations. The three image accelerator targets are quite distinct: the first one uses a vector architecture; the second one presents a SIMD architecture; the last one runs both on GPGPU and multi-cores through OpenCL. We have adapted standard compilation techniques to perform these compilation and code generation tasks automatically. Our strategy is implemented in\IfAnon{ an existing}{ PIPS, a} source-to-source compiler which greatly reduces the development cost as standard phases are reused and parameterized. We carried out experiments with applications on hardware functional simulators and GPUs. Our contributions include: 1)~a general low-cost compilation strategy for image processing applications, based on the semantics provided by library calls, which improves locality by an order of magnitude; 2)~specific heuristics to minimize execution time on the target accelerators; 3)~numerous experiments that show the effectiveness of our strategies. We also discuss the conditions required to extend this approach to other application domains.

L’objet de cette recherche soutenue par la fondation CIGREF est d’analyser les evolutions des business models qui accompagnent la transformation du modele dominant de la chaine de valeur de nombreux secteurs economiques. L’usage de plus en plus intensif des technologies de l’information contribue fortement a ce mouvement, accompagne et rend possibles de nouvelles formes de coproduction de valeur. Ces nouvelles formes de cooperation ont elles-memes de nombreuses consequences sur les systemes d’information et sur le role des technologies de l’information.

International audience; We present an automatic, static program transformation that schedules and generates e cient memory transfers between a computer host and its hardware accelerator, addressing a well-known performance bottleneck. Our automatic approach uses two simple heuristics: to perform transfers to the accelerator as early as possible and to delay transfers back from the accelerator as late as possible. We implemented this transformation as a middle-end compilation pass in the pips/Par4All compiler. In the generated code, redundant communications due to data reuse between kernel executions are avoided. Instructions that initiate transfers are scheduled e ectively at compile-time. We present experimental results obtained with the Polybench 2.0, some Rodinia benchmarks, and with a real numerical simulation. We obtain an average speedup of 4 to 5 when compared to a naïve parallelization using a modern gpu with Par4All, hmpp, and pgi, and 3.5 when compared to an OpenMP version using a 12-core multiprocessor.

International audience; Modular static analyzers use procedure abstractions, a.k.a. summarizations, to ensure that their execution time increases linearly with the size of analyzed programs. A similar abstraction mechanism is also used within a procedure to perform a bottom-up analysis. For instance, a sequence of instructions is abstracted by combining the abstractions of its components, or a loop is abstracted using the abstraction of its loop body: fixed point iterations for a loop can be replaced by a direct computation of the transitive closure of the loop body abstraction. More specifically, our abstraction mechanism uses affine constraints, i.e. polyhedra, to specify pre- and post-conditions as well as state transformers. We present an algorithm to compute the transitive closure of such a state transformer, and we illustrate its performance on various examples. Our algorithm is simple, based on discrete differentiation and integration: it is very different from the usual abstract interpretation fixed point computation based on widening. Experiments are carried out using previously published examples. We obtain the same results directly, without using any heuristic.

In today's embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia applications using temporary multi-dimensional arrays that are typically used to store intermediate results during multimedia processing. In this paper, the authors propose a new technique that optimizes the use of caches and registers. It consists in combining buffer and register allocation to reduce the size of the temporary arrays. The authors use the concept of live data to replace each array by a smaller buffer. The authors then replace references to this buffer by registers. The experiments are made on a Unix environment and on the StepNP simulator. The results show that the technique yields significant reduction of the number of data cache misses

The MIMD distributed memory architecture is the choice architecture for massively parallel machines. It insures scalability, but at the expense of programming ease. New languages such as HPF were introduced to solve this problem: the user advises the compiler about data distribution and parallel computations through directives. This paper focuses on the compilation of I/O communications for HPF. Data must be efficiently collected to or updated from I/O nodes with vectorized messages, for any possible mapping. The problem is solved using standard polyhedron scanning techniques. The code generation issues to handle the different cases are addressed. Then the method is improved and extended to parallel I/Os. This work suggests new HPF directives for parallel I/Os. >

Many mobile devices now integrate optic sensors; smartphones, tablets, drones... are foreshadowing an impending Internet of Things (IoT). New image processing applications (filters, compression, augmented reality) are taking advantage of these sensors under strong constraints of speed and energy efficiency. Modern architectures, such as manycore processors or GPUs, offer good performance, but are hard to program.This thesis aims at checking the adequacy between the image processing domain and these modern architectures: conciliating programmability, portability and performance is still a challenge today. Typical image processing applications feature strong, inherent parallelism, which can potentially be exploited by the various levels of hardware parallelism inside current architectures. We focus here on image processing based on mathematical morphology, and validate our approach using the manycore architecture of the Kalray MPPA processor.We first prove that integrated compilation chains, composed of compilers, libraries and run-time systems, allow to take advantage of various hardware accelerators from high-level languages. We especially focus on manycore processors, through various programming models: OpenMP, data-flow language, OpenCL, and message passing. Three out of four compilation chains have been developed, and are available to applications written in domain-specific languages (DSL) embedded in C or Python. They greatly improve the portability of applications, which can now be executed on a large panel of target architectures.Then, these compilation chains have allowed us to perform comparative experiments on a set of seven image processing applications. We show that the MPPA processor is on average more energy-efficient than competing hardware accelerators, especially with the data-flow programming model. We show that compiling a DSL embedded in Python to a DSL embedded in C increases both the portability and the performance of Python-written applications.Thus, our compilation chains form a complete software environment dedicated to image processing application development. This environment is able to efficiently target several hardware architectures, among them the MPPA processor, and offers interfaces in high-level languages.; Nous assistons à une explosion du nombre d’appareils mobiles équipés de capteurs optiques : smartphones, tablettes, drones... préfigurent un Internet des objets imminent. De nouvelles applications de traitement d’images (filtres, compression, réalité augmentée) exploitent ces capteurs mais doivent répondre à des contraintes fortes de vitesse et d’efficacité énergétique. Les architectures modernes — processeurs manycore, GPUs,... — offrent un potentiel de performance, avec cependant une hausse sensible de la complexité de programmation.L’ambition de cette thèse est de vérifier l’adéquation entre le domaine du traitement d’images et ces architectures modernes : concilier programmabilité, portabilité et performance reste encore aujourd’hui un défi. Le domaine du traitement d’images présente un fort parallélisme intrinsèque, qui peut potentiellement être exploité par les différents niveaux de parallélisme offerts par les architectures actuelles. Nous nous focalisons ici sur le domaine du traitement d’images par morphologie mathématique, et validons notre approche avec l’architecture manycore du processeur MPPA de la société Kalray.Nous prouvons d’abord la faisabilité de chaînes de compilation intégrées, composées de compilateurs, bibliothèques et d’environnements d’exécution, qui à partir de langages de haut niveau tirent parti de différents accélérateurs matériels. Nous nous concentrons plus particulièrement sur les processeurs manycore, suivant les différents modèles de programmation : OpenMP ; langage flot de données ; OpenCL ; passage de messages. Trois chaînes de compilation sur quatre ont été réalisées, et sont accessibles à des applications écrites dans des langages spécifiques au domaine du traitement d’images intégrés à Python ou C. Elles améliorent grandement la portabilité de ces applications, désormais exécutables sur un plus large panel d’architectures cibles.Ces chaînes de compilation nous ont ensuite permis de réaliser des expériences comparatives sur un jeu de sept applications de traitement d’images. Nous montrons que le processeur MPPA est en moyenne plus efficace énergétiquement qu’un ensemble d’accélérateurs matériels concurrents, et ceci particulièrement avec le modèle de programmation flot de données. Nous montrons que la compilation d’un langage spécifique intégré à Python vers un langage spécifique intégré à C permet d’augmenter la portabilité et d’améliorer les performances des applications écrites en Python.Nos chaînes de compilation forment enfin un environnement logiciel complet dédié au développement d’applications de traitement d’images par morphologie mathématique, capable de cibler efficacement différentes architectures matérielles, dont le processeur MPPA, et proposant des interfaces dans des langages de haut niveau.