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The large amount of memory usage in recent machine learning applications imposes a significant system burden with respect to power and processing speed. To cope with such a problem, Processing-In-Memory (PIM) techniques can be applied as an alternative solution. Especially, the recommendation system, which is one of the major machine learning applications used in data centers, requires a large memory capacity and therefore represents a suitable candidate application that could be helped by the PIM technique. In this paper, we introduce a machine learning framework, PIMCaffe, designed for in-memory neural processing units and its evaluation environment. PIMCaffe consists of two components: a Caffe2-based deep learning framework that supports PIM acceleration and a PIM-emulating hardware platform. We develop a suite of functions, libraries, application programming interfaces, and a device driver to support the framework. In addition, we implement a prototype Neural Processing Unit (NPU) in PIMCaffe to evaluate the performance of our platform with machine learning applications. Our prototype NPU design includes a vector processor for parallel vector processing and a systolic array unit for matrix multiplication. Using the proposed software framework, we perform a detailed analysis of the in-memory neural processing unit. PIMCaffe supports evaluations of recommendation systems and various convolutional neural network models on the in-memory neural processing unit. PIMCaffe with the NPU shows up to $2.26\times $ , $5.99\times $ , and $1.71\times $ speedup, compared to the ARM Cortex-A53 CPU, for the recommendation system, AlexNet, and ResNet-50, respectively.

National audience; Cet article présente une analyse de la consommation énergétique de la norme Wi-Fi IEEE 802.11ac, au niveau de la couche physique. La puissance dissipée par les circuits intégrés des émetteurs et récepteurs est prise en compte en plus de la puissance d'émission antennaire classique. Des simulations permettent d'évaluer la consommation en puissance des composants qui exécutent les algorithmes de traitement du signal, et les résultats sont validés par des mesures et des développements sur circuit logique programmable. Les éléments les plus énergivores sont ainsi identifiés, ce qui constitue une première étape vers un Wi-Fi à faible consommation d'énergie.

International audience; In this paper we presents a platform based design approach for fast HW/SW embedded smart Advanced Driver Assistant System (ADAS) design and prototyping. Then, we share our experience in designing and prototyping a HW/SW vision based smart embedded system as an ADAS that helps to increase the safety of car's drivers. We present a physical prototype of the vision ADAS based on a Zynq FPGA. The system detects the fatigue state of the driver by monitoring the eyes closure and generates a real-time alert. A new HW/SW codesign skin segmentation step to locate the eyes/face is proposed. Our presented new approach migrates the skin segmentation step from processing system (SW) to programmable logic (HW) IP taking the advantage of High Level Synthesis (HLS) tool flow to accelerate the design and prototyping flow of the vision based ADAS on a hardware Zynq platform.

Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitation of conventional shared bus architecture for many-core system-on-chip (MCSoC). Current field-programmable gate arrays (FPGAs) have over million lookup tables, making it possible to prototype a complete NoC-based MCSoC on a single FPGA device. FPGA prototyping allows rapid system verification and optimum design parameters estimation. However, existing NoC-based MCSoC prototypes are usually adopting simple NoC architectural functionality. These NoC prototypes cannot represent a realistic projection of the state-of-the-art application-specific integrated circuit (ASIC) NoCs as these prototypes have limited overall system performance. This paper presents ProNoC, an integrated tool for rapid prototyping and validation of NoC-based MCSoC projects targeting FPGA devices. ProNoC adopts most advanced NoC features such as the support of virtual channel (VC), virtual network, low latency routing and different routing algorithms. Results show that NoC interconnect in ProNoC outperforms CONNECT, the most recent VC based prototype NoC with lower logic cell utilization, higher maximum operating frequency, higher average saturation throughput, and lower average communication latency. Moreover, ProNoC is equipped with graphical user interface to facilitate the development of MCSoC prototypes on FPGA platforms.

Domain-specific accelerators are a reaction adapting to device scaling and the dark silicon era. This paper describes a radar signal processing oriented configurable accelerator and the application space exploration of the system. The system is built around accelerator engines and general-purpose processors (GPPs) that make it suitable for intensive computing kernel acceleration and complex control tasks. It is geared toward high-performance radar digital signal processing; we characterize the applications and find that each of them contains a series of serializable kernels. Taking advantage of this discovery, we design an algorithm pool that shares the same computation resource and memory resource, and each algorithm is size reconfigurable. On the other hand, shared on-chip addressable scratchpad memory eliminates unnecessary explicit data copy between accelerators. Performance of the system is evaluated from measurements performed both on an FPGA SoC test chip and on a prototype chip fabricated by CMOS 40 nm technology. The experimental results show that for different algorithms, the proposed system achieves 1.9× to 10.1× performance gain compared with a state-of-the-art TI DSP chip. In order to characterize the application of the system, a complex real-life task is adopted, and the results show that it can obtain high throughput and desirable precision.

Edge detection of color images is usually performed by applying the traditional techniques for gray-scale images to the three color channels separately. However, human visual perception does not differentiate colors and processes the image as a whole. Recently, new methods have been proposed that treat RGB color triples as vectors and color images as vector fields. In these approaches, edge detection is obtained extending the classical pattern matching and convolution techniques to vector fields. This paper proposes a hardware implementation of an edge detection method for color images that exploits the definition of geometric product of vectors given in the Clifford algebra framework to extend the convolution operator and the Fourier transform to vector fields. The proposed architecture has been prototyped on the Celoxica RC203E Field Programmable Gate Array (FPGA) board. Experimental tests on the FPGA prototype show that the proposed hardware architecture allows for an average speedup ranging between 6x and 18x for different image sizes against the execution on a conventional general-purpose processor. Clifford algebra based edge detector can be exploited to process not only color images but also multispectral gray-scale images. The proposed hardware architecture has been successfully used for feature extraction of multispectral magnetic resonance (MR) images.

Large variety of channel coding techniques are specified in existing and emerging digital communication standards, each suitable for specific application needs (frame size, transmission channel, signal-to-noise ratio, bandwidth, etc). Considering the emerging multi-mode and multi-standard applications, as well as the increasing interest for Software Defined Radio (SDR) and Cognitive Radio (CR) applications, flexible implementations combining multiple error correction techniques becomes mandatory. However, the need of optimal solutions in terms of performance, area, and power consumption is increasing too and cannot be neglected against flexibility. In this context, this thesis work has investigated multi-ASIP architecture model towards the target of unifying flexibility-oriented and optimization-oriented approaches in the design of flexible channel decoders. By considering mainly the challenging Turbo and LDPC decoding applications, multi-ASIP channel decoder architectures are proposed targeting high flexibility combined with high architecture efficiency in terms of bits/cycle/iteration/mm2. Different architecture alternatives and design approaches are explored. Three original contributions have been proposed. The first one concerns the design of a scalable and flexible high throughput multi-ASIP LDPC/Turbo decoder. Several design objectives have been attained in this work in terms of scalability, resource sharing, and configurability speed. The proposed DecASIP supports the decoding of LDPC and Turbo codes specified in WiFi, WiMAX, and LTE standards. The achieved scalability through the multi-ASIP NoC based approach enables the accommodation of current and future high throughput requirements. The second contribution concerns the design of a parameterized ASIP for Turbo decoding (TDecASIP). Here the objective was to investigate the maximum attainable architecture efficiency for ASIP-based Turbo decoding when maximizing the usage of sub-block parallelism. Furthermore, with this architecture we demonstrated the possibility to design application-specific parameterized cores using the available ASIP design flow. The third contribution corresponds to the design of an optimized ASIP for LDPC decoding (LDecASIP). As for TDecASIP, the objective was to investigate the maximum attainable architecture efficiency for ASIP-based LDPC decoding by increasing the parallelism degree and the necessary memory bandwidth. A fourth main contribution of this thesis work concerns the hardware prototyping. A complete communication system platform including 4-DecASIP channel decoder has been prototyped on an FPGA-based logic emulation board. To our knowledge, this is the first demonstrated multi-ASIP NoC-based FPGA prototype that is capable of decoding LDPC and Turbo (SBTC and DBTC) codes. Furthermore, an ASIC integration of the 4-DecASIP system decoder has been accomplished by the CEA-LETI on the MAG3D Telecom chip which targets 4G communication applications. These results demonstrate the rapid design cycle and the effectiveness offered by the ASIP based design approach in this application domain to fine tune design trade-offs w.r.t. diverse design objectives.; De nombreuses techniques de codage de canal sont spécifiées dans les nouvelles normes de communications numériques, chacune adaptée à des besoins applicatifs spécifiques (taille de trame, type de canal de transmission, rapport signal-à-bruit, bande-passante, etc.). Si l'on considère les applications naissantes multi-mode et multi-standard, ainsi que l'intérêt croissant pour la radio logicielle et la radio cognitive, la combinaison de plusieurs techniques de correction d'erreur devient incontournable. Néanmoins, des solutions optimales en termes de performance, de consommation d'énergie et de surface sont encore à inventer et ne doivent pas être négligées au profit de la flexibilité. Dans ce contexte, ce travail de thèse a exploré le modèle d'architecture multi-ASIP dans le but d¿unifier l'approche orientée sur la flexibilité et celle orientée sur l'optimalité dans la conception de décodeurs de canal flexibles. En considérant principalement les applications exigeantes de décodage itératif des turbocodes et des codes LDPC, des architectures multi-ASIP de décodeurs de canal sont proposées ciblant une grande flexibilité combinée à une haute efficacité architecturale en termes de bits/cycle/iteration/mm2. Différentes solutions architecturales et différentes approches de conception sont explorées pour proposer trois contributions originales. La première contribution concerne la conception d'un décodeur LDPC/Turbo multi-ASIP extensible, flexible et haut débit. Plusieurs objectifs de conception sont atteints en termes d'extensibilité, de partage de ressources, et de vitesse de configuration. Le décodeur proposé, nommé DecASIP, supporte le décodage des codes LDPC et turbocodes spécifiés dans les normes WiFi, WiMAX et LTE. L'extensibilité apportée par l'approche multi-ASIP basée sur des réseaux sur puces (NoC) permet d'atteindre les besoins en haut débit des normes actuelles et futures. La deuxième contribution concerne la conception d'un ASIP paramétré pour le turbo-décodage (TDecASIP). L'objectif étant d'étudier l'efficacité maximale atteignable pour un turbo décodeur basé sur le concept ASIP en maximisant l¿exploitation du parallélisme de sous-blocs. En outre, avec cette architecture nous avons démontré la possibilité de concevoir des c¿urs de traitement paramétrables et dédiés à l¿application en utilisant le flot de conception ASIP existant. La troisième contribution correspond à la conception d'un ASIP optimisé pour le décodage des codes LDPC (LDecASIP). Comme pour TDecASIP, l'objectif étant d'étudier l'efficacité maximale atteignable pour un décodeur de codes LDPC basé sur le concept ASIP en augmentant le degré de parallélisme et la bande passante des mémoires. Une quatrième contribution principale de cette thèse porte sur le prototypage matériel. Une plateforme de communication complète intégrant 4-DecASIP pour le décodage de canal a été prototypé sur une carte à base de circuits FPGA. À notre connaissance, c'est le premier prototype FPGA publié de décodeur de canal flexible supportant le décodage des turbocodes et des codes LDPC avec une architecture multi-ASIP intégrant des NoC. De plus, une intégration ASIC de ce décodeur a été réalisée par le CEA-LETI dans la puce MAG3D visant des applications de communications pour la 4G. Ces résultats démontrent le cycle de conception rapide et l'efficacité offerte par l'approche de conception basée sur le concept ASIP dans ce domaine d'application, permettant ainsi d¿affiner les compromis de conception par rapport aux divers objectifs ciblés.

Systems-on-chips in the field of digital communications are becoming extremely diversified and complex with the continuous emerging of new digital communication systems and standards. In this field, Turbo decoding is one of the most computation, communication, and memory intensive, and thus, power-consuming component. Besides the increasing performance requirements, emerging digital communication systems imply multi-standard interoperability which introduces the new implementation flexibility requirement. In this context, recent efforts have targeted the use of Application-Specific Instruction-set Processor models (ASIP). Such an architecture model enables the designer to freely tune the flexibility/performance trade-off as required by the considered application. However, the architecture efficiency of application-specific processors is directly related to the devised instruction set and pipeline stages usage. Most of recently proposed works do not present this key issue explicitly. Hence, the main objective of this thesis work is related to unifying flexibility-oriented and optimization-oriented approaches in the design of channel decoders. Towards this objective, several contributions have been proposed: (1) designing of a multi-standard ASIP-based Turbo decoder achieving high architecture efficiency in terms of bit/cycle/iteration/mm2, (2) optimizing of the dynamic reconfiguration speed of the proposed ASIP architecture supporting all parameters of 3GPP-LTE/WiMAX/DVB-RCS standards, (3) designing of low complexity ARP and QPP interleavers for butterfly scheme with Radix4 trellis compression technique, and (4) proposing and designing of a complete FPGA prototype for the proposed multi-standard Turbo decoder. Furthermore, towards the support of LDPC decoding, a first effort has been proposed for the design of a scalable and ¿exible high throughput multi-ASIP combined architecture for LDPC and Turbo decoding., Les systèmes sur puces dans le domaine des communications numériques deviennent extrêmement diversifiés et complexes avec la constante émergence de nouveaux standards et de nouvelles applications. Dans ce domaine, le turbo-décodeur est l'un des composants les plus exigeants en termes de calcul, de communication et de mémoire, donc de consommation d'énergie. Outre les exigences de performances croissantes, les nouveaux systèmes de communications numériques imposent une interopérabilité multi-standard qui introduit la nouvelle exigence de flexibilité de l'implémentation. Dans ce contexte, des travaux récents ont proposé l'utilisation du nouveau concept de processeurs à jeu d'instructions dédié à l'application (ASIP). Un tel modèle d'architecture permet au concepteur d'affiner librement le compromis flexibilité/performance tel que requis par l'application considérée. Toutefois, l'efficacité architecturale des processeurs dédiés à l'application est directement liée au jeu d'instruction défini ainsi qu'au taux d'utilisation des étages de pipeline. La plupart des travaux proposés récemment ne considèrent pas ces aspects explicitement. Par conséquent, ce travail de thèse s'inscrit dans l'objectif principal d'unifier l'approche orientée sur la flexibilité et celle orientée sur l'optimalité dans la conception de décodeurs de canal. Dans cet objectif, plusieurs contributions ont été proposées : (1) conception d'un turbo-décodeur multi-standard basé sur le concept ASIP assurant une efficacité architecturale élevée en bit/cycle/iteration/mm2, (2) optimisation de la vitesse de reconfiguration dynamique de l'ASIP proposé supportant tous les paramètres spécifiés dans les normes 3GPP-LTE/WiMAX/DVB-RCS, (3) conception d'entrelaceurs ARP et QPP de faible complexité pour le schéma de décodage de type papillon avec la technique de compression de treillis de type Radix4 et (4) proposition et mise en oeuvre d'un prototype FPGA de système de communication complet intégrant le turbo-décodeur multi-standard proposé. De plus, une première contribution a été proposée vers la conception d'une architecture multi-ASIP flexible et extensible supportant le décodage des turbocodes et des codes LDPC.

Systems-on-chips in the field of digital communications are becoming extremely diversified and complex with the continuous emerging of new digital communication systems and standards. In this field, Turbo decoding is one of the most computation, communication, and memory intensive, and thus, power-consuming component. Besides the increasing performance requirements, emerging digital communication systems imply multi-standard interoperability which introduces the new implementation flexibility requirement. In this context, recent efforts have targeted the use of Application-Specific Instruction-set Processor models (ASIP). Such an architecture model enables the designer to freely tune the flexibility/performance trade-off as required by the considered application. However, the architecture efficiency of application-specific processors is directly related to the devised instruction set and pipeline stages usage. Most of recently proposed works do not present this key issue explicitly. Hence, the main objective of this thesis work is related to unifying flexibility-oriented and optimization-oriented approaches in the design of channel decoders. Towards this objective, several contributions have been proposed: (1) designing of a multi-standard ASIP-based Turbo decoder achieving high architecture efficiency in terms of bit/cycle/iteration/mm2, (2) optimizing of the dynamic reconfiguration speed of the proposed ASIP architecture supporting all parameters of 3GPP-LTE/WiMAX/DVB-RCS standards, (3) designing of low complexity ARP and QPP interleavers for butterfly scheme with Radix4 trellis compression technique, and (4) proposing and designing of a complete FPGA prototype for the proposed multi-standard Turbo decoder. Furthermore, towards the support of LDPC decoding, a first effort has been proposed for the design of a scalable and ¿exible high throughput multi-ASIP combined architecture for LDPC and Turbo decoding.; Les systèmes sur puces dans le domaine des communications numériques deviennent extrêmement diversifiés et complexes avec la constante émergence de nouveaux standards et de nouvelles applications. Dans ce domaine, le turbo-décodeur est l'un des composants les plus exigeants en termes de calcul, de communication et de mémoire, donc de consommation d'énergie. Outre les exigences de performances croissantes, les nouveaux systèmes de communications numériques imposent une interopérabilité multi-standard qui introduit la nouvelle exigence de flexibilité de l'implémentation. Dans ce contexte, des travaux récents ont proposé l'utilisation du nouveau concept de processeurs à jeu d'instructions dédié à l'application (ASIP). Un tel modèle d'architecture permet au concepteur d'affiner librement le compromis flexibilité/performance tel que requis par l'application considérée. Toutefois, l'efficacité architecturale des processeurs dédiés à l'application est directement liée au jeu d'instruction défini ainsi qu'au taux d'utilisation des étages de pipeline. La plupart des travaux proposés récemment ne considèrent pas ces aspects explicitement. Par conséquent, ce travail de thèse s'inscrit dans l'objectif principal d'unifier l'approche orientée sur la flexibilité et celle orientée sur l'optimalité dans la conception de décodeurs de canal. Dans cet objectif, plusieurs contributions ont été proposées : (1) conception d'un turbo-décodeur multi-standard basé sur le concept ASIP assurant une efficacité architecturale élevée en bit/cycle/iteration/mm2, (2) optimisation de la vitesse de reconfiguration dynamique de l'ASIP proposé supportant tous les paramètres spécifiés dans les normes 3GPP-LTE/WiMAX/DVB-RCS, (3) conception d'entrelaceurs ARP et QPP de faible complexité pour le schéma de décodage de type papillon avec la technique de compression de treillis de type Radix4 et (4) proposition et mise en oeuvre d'un prototype FPGA de système de communication complet intégrant le turbo-décodeur multi-standard proposé. De plus, une première contribution a été proposée vers la conception d'une architecture multi-ASIP flexible et extensible supportant le décodage des turbocodes et des codes LDPC.

International audience; Hardware prototyping has been the key to system validation, once the hardware simulation matches the software model results and before the final silicon tape-out. On the other hand, flexible multi-standard implementations are being widely investigated these last years for the challenging channel decoding application. The latest contributions explore ASIP (Application-Specific Instruction-set Processor) concept and target to achieve efficient resource sharing between advanced Turbo and LDPC iterative decoders.In this paper we present an FPGA-based prototype of a multi-standard Turbo/LDPC Encoding and Decoding. The functional prototype implements a full communication system including encoder, channel model, ASIP-based decoder and performance counters. All components are flexible and are dynamically configurable through a dedicated GUI (Graphical User Interface). The prototype supports all communication modes defined in LTE, WiFi, WiMAX, and DVB-RCS wireless communication standards.

Large variety of channel coding techniques are specified in existing and emerging digital communication standards, each suitable for specific application needs (frame size, transmission channel, signal-to-noise ratio, bandwidth, etc). Considering the emerging multi-mode and multi-standard applications, as well as the increasing interest for Software Defined Radio (SDR) and Cognitive Radio (CR) applications, flexible implementations combining multiple error correction techniques becomes mandatory. However, the need of optimal solutions in terms of performance, area, and power consumption is increasing too and cannot be neglected against flexibility. In this context, this thesis work has investigated multi-ASIP architecture model towards the target of unifying flexibility-oriented and optimization-oriented approaches in the design of flexible channel decoders. By considering mainly the challenging Turbo and LDPC decoding applications, multi-ASIP channel decoder architectures are proposed targeting high flexibility combined with high architecture efficiency in terms of bits/cycle/iteration/mm2. Different architecture alternatives and design approaches are explored. Three original contributions have been proposed. The first one concerns the design of a scalable and flexible high throughput multi-ASIP LDPC/Turbo decoder. Several design objectives have been attained in this work in terms of scalability, resource sharing, and configurability speed. The proposed DecASIP supports the decoding of LDPC and Turbo codes specified in WiFi, WiMAX, and LTE standards. The achieved scalability through the multi-ASIP NoC based approach enables the accommodation of current and future high throughput requirements. The second contribution concerns the design of a parameterized ASIP for Turbo decoding (TDecASIP). Here the objective was to investigate the maximum attainable architecture efficiency for ASIP-based Turbo decoding when maximizing the usage of sub-block parallelism. Furthermore, with this architecture we demonstrated the possibility to design application-specific parameterized cores using the available ASIP design flow. The third contribution corresponds to the design of an optimized ASIP for LDPC decoding (LDecASIP). As for TDecASIP, the objective was to investigate the maximum attainable architecture efficiency for ASIP-based LDPC decoding by increasing the parallelism degree and the necessary memory bandwidth. A fourth main contribution of this thesis work concerns the hardware prototyping. A complete communication system platform including 4-DecASIP channel decoder has been prototyped on an FPGA-based logic emulation board. To our knowledge, this is the first demonstrated multi-ASIP NoC-based FPGA prototype that is capable of decoding LDPC and Turbo (SBTC and DBTC) codes. Furthermore, an ASIC integration of the 4-DecASIP system decoder has been accomplished by the CEA-LETI on the MAG3D Telecom chip which targets 4G communication applications. These results demonstrate the rapid design cycle and the effectiveness offered by the ASIP based design approach in this application domain to fine tune design trade-offs w.r.t. diverse design objectives., De nombreuses techniques de codage de canal sont spécifiées dans les nouvelles normes de communications numériques, chacune adaptée à des besoins applicatifs spécifiques (taille de trame, type de canal de transmission, rapport signal-à-bruit, bande-passante, etc.). Si l'on considère les applications naissantes multi-mode et multi-standard, ainsi que l'intérêt croissant pour la radio logicielle et la radio cognitive, la combinaison de plusieurs techniques de correction d'erreur devient incontournable. Néanmoins, des solutions optimales en termes de performance, de consommation d'énergie et de surface sont encore à inventer et ne doivent pas être négligées au profit de la flexibilité. Dans ce contexte, ce travail de thèse a exploré le modèle d'architecture multi-ASIP dans le but d¿unifier l'approche orientée sur la flexibilité et celle orientée sur l'optimalité dans la conception de décodeurs de canal flexibles. En considérant principalement les applications exigeantes de décodage itératif des turbocodes et des codes LDPC, des architectures multi-ASIP de décodeurs de canal sont proposées ciblant une grande flexibilité combinée à une haute efficacité architecturale en termes de bits/cycle/iteration/mm2. Différentes solutions architecturales et différentes approches de conception sont explorées pour proposer trois contributions originales. La première contribution concerne la conception d'un décodeur LDPC/Turbo multi-ASIP extensible, flexible et haut débit. Plusieurs objectifs de conception sont atteints en termes d'extensibilité, de partage de ressources, et de vitesse de configuration. Le décodeur proposé, nommé DecASIP, supporte le décodage des codes LDPC et turbocodes spécifiés dans les normes WiFi, WiMAX et LTE. L'extensibilité apportée par l'approche multi-ASIP basée sur des réseaux sur puces (NoC) permet d'atteindre les besoins en haut débit des normes actuelles et futures. La deuxième contribution concerne la conception d'un ASIP paramétré pour le turbo-décodage (TDecASIP). L'objectif étant d'étudier l'efficacité maximale atteignable pour un turbo décodeur basé sur le concept ASIP en maximisant l¿exploitation du parallélisme de sous-blocs. En outre, avec cette architecture nous avons démontré la possibilité de concevoir des c¿urs de traitement paramétrables et dédiés à l¿application en utilisant le flot de conception ASIP existant. La troisième contribution correspond à la conception d'un ASIP optimisé pour le décodage des codes LDPC (LDecASIP). Comme pour TDecASIP, l'objectif étant d'étudier l'efficacité maximale atteignable pour un décodeur de codes LDPC basé sur le concept ASIP en augmentant le degré de parallélisme et la bande passante des mémoires. Une quatrième contribution principale de cette thèse porte sur le prototypage matériel. Une plateforme de communication complète intégrant 4-DecASIP pour le décodage de canal a été prototypé sur une carte à base de circuits FPGA. À notre connaissance, c'est le premier prototype FPGA publié de décodeur de canal flexible supportant le décodage des turbocodes et des codes LDPC avec une architecture multi-ASIP intégrant des NoC. De plus, une intégration ASIC de ce décodeur a été réalisée par le CEA-LETI dans la puce MAG3D visant des applications de communications pour la 4G. Ces résultats démontrent le cycle de conception rapide et l'efficacité offerte par l'approche de conception basée sur le concept ASIP dans ce domaine d'application, permettant ainsi d¿affiner les compromis de conception par rapport aux divers objectifs ciblés.

International audience; Rotated QAM constellations improve Bit-Interleaved Coded Modulation (BICM) performance over fading channels. Indeed, an increased diversity is obtained by coupling a constellation rotation with interleaving between the real and imaginary components of transmitted symbols either in time or frequency domain. Iterative processing at the receiver side can provide additional improvement in performance. In this paper, an efficient shuffled iterative receiver is investigated for the second generation of the terrestrial digital video broadcasting standard DVB-T2. Scheduling an efficient message passing algorithm with low latency between the demapper and the LDPC decoder represents the main contribution. The design and the FPGA prototyping of the resultant shuffled iterative BICM receiver are then described. Architecture complexity and measured performance validate the potential of iterative receiver as a practical and competitive solution for the DVB-T2 standard.

International audience; Signal Space Diversity (SSD) has been lately adopted into the second generation of the terrestrial digital video broadcasting standard DVB-T2. In this paper, a bit-interleaved coded modulation receiver for the DVB-T2 standard is detailed. An LDPC decoder based on a vertical layered schedule is the main novelty of this work. It enables an efficient exchange of extrinsic information between the rotated demapper and the LDPC decoder if an iterative receiver is considered. The FPGA prototyping of the resultant architecture is then described. Low architecture complexity and good performance represent the main features of the proposed receiver.

This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. Optical packets are assembled by aggregating IP packets, and attaching an optical packet header. Conventional schemes process optical packet headers one by one, in a sequential form. Then, the worst case algorithm response time is tightly coupled to switch size. In contrast, in PI-OPS all the optical packets received during a given time window are jointly processed to optimize the delay and output wavelength allocation, applying void filling techniques. The scheduler has a deterministic response time, independent of the traffic arrival's pattern. In addition, PI-OPS has been specifically designed to allow a parallel electronic implementation similar to the ones found in VOQ schedulers. In this respect, we evaluate the traffic loss performance of the scheduler in different settings, to dimension a set of hardware related parameters. Finally, we conduct an emulation of an FPGA implementation of a large-scale version of the scheduler. Results support the feasibility of its implementation.

Last three decades can undoubtedly be said as the decades of wireless communications. New state of the art data processing techniques have been developed and used in practical system. These techniques include advanced Error Control Coding (ECC), Bit Interleaved CodedModulation (BICM), high ordered Quadrature Amplitude Modulations (QAM), Signal Space Diversity (SSD), Multi Input Multi Output (MIMO), Orthogonal Frequency Division Multiplexing (OFDM), and others. To guide the wireless communication industry, for the adoption of new developed techniques in the commercial devices, diverse wireless communication standards have been evolved rapidly in the domain of cellular telephone network, local/wide wireless area networks and Digital Video Broadcast (DVB). These standards propose best combination of evolved data processing schemes at the transmitter to protect data from destructive channel effects under different transmission conditions. Taking an example of mobile telephony, by using newly developed concepts such as spatial multiplexing feature of MIMO, the evolving 3GPP-LTE standard is aimed at achieving 100 Mega bits per second to support high data rate real-time applications on a mobile terminal. Similar trends are also visible in other public domains of wireless communication such as DVB-NGH (Next Generation Handheld), which is the next generation standard for video broadcasting, providing services for fixed and mobile terminals. The other aspect under consideration is the global roaming or seamless coverage across geographical regions which demands multi-mode radios compatible with different systems and standards to provide seamless services at fixed location. While translating these requirements on the physical layer of a radio terminal, this can be seen as a flexible high throughput hardware platform which can be configured to the required air interface. The overall flexibility of the radio platform can be achieved through the flexibility of individual components at transmitter side (encoder, interleaver, mapper, etc.) and at receiver side (equalizer, demapper, deinterleaver, decoder, etc.). This emerging flexibility need in digital baseband design constitutes a new major challenge when added to the ever increasing requirements in terms of throughput and area. In addition to technical requirements associated with rapid growth in wireless communication industry, the severe time-to-market constraints compel the designers for adopting the rapid design, validation and prototyping flow to conceive these wireless radio terminals for their successful and timely delivery in the market. In short, the diverse requirements of wireless communication standards imply, between others, two crucial requirements on hardware implementation: (1) 14

International audience; In order to meet flexibility and performance constraints of current and future digital communication applications, a novel ASIP architecture is proposed in this paper. Flexibility of the presented DemASIP architecture allows its reuse for any modulation type ranging from QPSK to 256-QAM, rotated/non-rotated, Gray/non-Gray and in both iterative and non-iterative context.

International audience; Rapid emergence of diverse wireless communication standards implies two crucial requirements on hardware implementation: (1) Hardware platform flexibility for multistandard support, and (2) Rapid prototyping methodology for system validation under different use case scenarios. ASIP based platform, designed through Architecture Description Language(ADL) fulfills both of these requirements in an elegant way. This paper presents the design summary and prototyping flow of an ASIP-based flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications. The rapid development and prototyping flow has been described starting from LISA ADL description till the FPGA implementation. Using a logic emulation board integrating Virtex 5 FPGA,the prototype of 2×2 spatially multiplexed MIMO system achieves a throughput of 65 MSymbol/Sec at a clock frequency of 130MHz.

International audience; Present and future digital communication standards in the field of wireless communication, fiber-optic communication and storage applications are proposing more and more the use of turbo codes as error correcting codes. In this application domain, flexibility and high-throughput requirements are being widely investigated during the last few years. In this context, multiprocessor platforms constitute a promising architectural solution for the design of high-throughput flexible turbo decoders. Besides application algorithm optimizations and application-specific processor design, the on-chip communication network connecting the multiple on-chip cores constitutes a major issue. Our aim in this work is to propose a network-on-chip architecture allowing efficient multiprocessor turbo decoder implementation. Proposed NoC architectures should accommodate the intensive and random extrinsic information exchange between the iterative processing components. Scalability is required in order to cope with the increasingly severe constraints in terms of throughput and error rates, while flexibility is required in order to support any interleaving rule, and thus, any application standard. In this context, appropriate flexible and scalable application-specific NoC topologies, routing algorithms and resources management techniques are being proposed.