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Semiconducting carbon nanotubes are robust molecules with nanometer-scale diameters that can be used in field-effect transistors, from larger thin-film implementation to devices that work in conjunction with silicon electronics, and can potentially be used as a platform for high-performance digital electronics as well as radio-frequency and sensing applications. Recent progress in the materials, devices, and technologies related to carbon nanotube transistors is briefly reviewed. Emphasis is placed on the most broadly impactful advancements that have evolved from single-nanotube devices to implementations with aligned nanotubes and even nanotube thin films. There are obstacles that remain to be addressed, including material synthesis and processing control, device structure design and transport considerations, and further integration demonstrations with improved reproducibility and reliability; however, the integration of more than 10,000 devices in single functional chips has already been realized. [ABSTRACT FROM AUTHOR]

Tailoring the electronic states of the dielectric oxide/diamond interface is critical to the development of next generation semiconductor devices like high-power high-frequency field-effect transistors. In this work, we investigate the electronic states of the TiO2/diamond 2 × 1–(100) interface by using first principles total energy calculations. Based on the calculation of the chemical potentials for the TiO2/diamond interface, it is observed that the hetero-interfaces with the C-OTi configuration or with two O vacancies are the most energetically favorable structures under the O-rich condition and under Ti-rich condition, respectively. The band structure and density of states of both TiO2/diamond and TiO2/H-diamond hetero-structures are calculated. It is revealed that there are considerable interface states at the interface of the anatase TiO2/diamond hetero-structure. By introducing H on the diamond surface, the interface states are significantly suppressed. A type-II alignment band structure is disclosed at the interface of the TiO2/diamond hetero-structure. The valence band offset increases from 0.6 to 1.7 eV when H is introduced at the TiO2/diamond interface. [ABSTRACT FROM AUTHOR]

A new vertical field-effect transistor (FET) has been fabricated inside a through silicon VIA (TSV). Front side and backside of a 200- $\mu \text{m}$ -thin p-doped Si wafer were highly n-doped to shape the source/drain areas of the FET. The lateral surface of the TSV forms the channel with a length of $200~\mu \text{m}$ (wafer thickness) and a width of $63~\mu \text{m}$ (circumference of the 20- $\mu \text{m}$ hole). A stack of SiO2 and Al2O3 was used as gate dielectric material and Ru/TaN/Ru was deposited as gate metal using atomic layer deposition. The n-channel TSVFETs showed saturation currents of 150 $\mu \text{A}$ for a gate voltage of 4 V and an ON/OFF current ratio of about 104. [ABSTRACT FROM AUTHOR]

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio. [ABSTRACT FROM AUTHOR]

There are considerable interests to detect and monitor the abnormal level of minerals in water for avoiding/preventing any toxic effects after consumption. Herein, we report the fabrication of solution-gated field-effect-transistor (FET) based potassium sensor using iron oxide nanoparticles (Fe 2 O 3 NPs) modified directly grown zinc oxide nanorods (ZnO NRs). The Fe 2 O 3 NPs modification of ZnO NRs provided stability to nanorods surface and improved surface area for valinomycin immobilization. As-fabricated potassium sensor (valinomycin-Fe 2 O 3 NPs-ZnO NRs/SiO 2 /Si) provided enhanced current response with increasing potassium concentration. During sensing measurements, FET sensor showed high sensitivity (4.65 μA/μM/cm 2 ) in the linear range of 0.1 μM to 125 μM, low limit of detection (∼0.04 μM), good stability, excellent reproducibility, and favorable selectivity. Thus, good sensing performance of the FET based potassium sensor presents it as simple, low-cost, and convenient device for selective detection of potassium in solution. [ABSTRACT FROM AUTHOR]

A new vertical JFET transistor has been recently developed at the IMB-CNM, taking advantage of a deep-trenched 3D technology to achieve vertical conduction and low switch-off voltage. The silicon V-JFET transistors were mainly conceived to work as rad-hard protection switches for the renewed HV powering scheme (HV-MUX) of the ATLAS upgraded tracker. This work presents the features of the first batch of V-JFETs produced at the IMB-CNM clean room, together with the results of a full pre-irradiation characterization of the fabricated prototypes. Details of the technological process are provided and the outcome quality is also evaluated with the aid of reverse engineering techniques. Concerning the electrical performance of the prototypes, promising results were obtained, already meeting most of the HV-MUX specifications, both at room and below-zerotemperatures. [ABSTRACT FROM AUTHOR]

We demonstrate a transfer-free method for producing 3-5 monolayers, large area MoS2 by preoxidation of metallic Mo. The growth temperature was reduced, eliminating free sulfur-induced degradation of the SiO2 gate dielectric in strong accumulation, which suppressed the leakage current at VGS=3V by a factor of ≤108, when compared to a single step direct sulfidation method. Back-gated field effect transistors with an accumulation electron mobility of >80 cm²/Vs, an on/ off ratio of >105, and a subthreshold swing of 84 mV/dec from this MoS2 represent the state-ofthe- art on SiO2. In accumulation, current saturation was attributed to charge control rather than velocity saturation. The hysteresis-free transistor characteristics were stable up to a temperature of 500 K. [ABSTRACT FROM AUTHOR]

Recently, exceptionally high field-effect mobility in organic field-effect transistors (OFETs) has been fabricated using semiconducting films with one-dimensionally aligned, highly planar electron donor-acceptor copolymers, within the channel of transistors. Here, we propose an extremely simple coating method, called rotation coating, for preparing highly aligned, conjugated polymer thin films for applications in various organic electronic devices. We realize highly aligned polymer films using various conjugated polymers and applied the films as active layers for high-performance OFETs. Significantly high field-effect mobility values of 1.45 ± 0.46 cm²/Vs have been achieved for rotation coated diketopyrrolopyrrole-thieno[3,2-b]thiophene copolymer films. [ABSTRACT FROM AUTHOR]

Biocompatible and biodegradable materials are attractive for environmentally safe, flexible and biosustainable devices since they are nontoxic renewable materials with a low cost. Gelatin, a natural protein, is a promising biopolymer for photography, cosmetic manufacturing and food. In this paper, solution-processed natural gelatin was used as a gate dielectric for the fabrication of oxide field-effect transistors (FETs). Similarly to a polyelectrolyte, mobile ions can be generated in gelatin in air environment. A high gate specific capacitance larger than 0.93 μF/cm 2 was obtained in gelatin processed at low concentrations, due to the formation of electric-double-layers (EDLs). As gelatin films processed at a low concentration of 0.02 g/mL, the fabricated FETs showed excellent electrical performances. The average current on/off ratio and the mobility were estimated to be 1.36 × 10 5 and 33.2 cm 2 /V, respectively. The proposed technique may be application in the bioelectronics field, including biosensors and synaptic devices. [ABSTRACT FROM AUTHOR]

We have fabricated top-gate field-effect transistors (FETs) based on an oxide semiconductor for high-performance driving capability. The optimization of the plasma treatment enabled a 50-nm-thick gate insulating film and a short channel length of these FETs, enabling a high FET performance. [ABSTRACT FROM AUTHOR]

A strong demand for even more compact and reliable power electronic devices has powered the development of advanced design techniques. A key role is played in these techniques by the reliability assessment, a procedure that estimates the expected lifetime according to given mission profiles. The reliability assessment of a low voltage MOSFET working in avalanche mode is considered in this paper through an experimental approach based on the Coffin–Manson law. Differently from previously proposed techniques, based on a thermodynamic analysis, a direct measurement of the thermal strain over the source aluminum layer is instead exploited. The consistence of the proposed technique is evaluated by comparing estimation of the progressive increment of the on-state resistance with results of endurance tests and estimation obtained from previously presented reliability models. The described technique can be applied to assess the reliability of MOSFETs in applications typical of the automotive field, where they are tasked to power inductive loads in unclamped mode. More in general, the method can be exploited to characterize the front metal of MOSFET devices subjected to power cycling, or short-circuit stress tests. [ABSTRACT FROM AUTHOR]

In this letter, we report flexible fully oxide-based complementary metal–oxide–semiconductor (CMOS) inverters and ring oscillators by the monolithic integration of flexible n-channel zinc oxide (ZnO) and p-channel tin monoxide (SnO) thin-film transistors (TFTs). Inverted-staggered bottom-gated TFTs were fabricated by a low-temperature RF-sputtering technique. The static voltage gain of a flexible oxide-TFT-based CMOS inverter with a geometric aspect ratio of 5 is \sim 12 at a supplied voltage ( \text{V}_{\mathrm {DD}} ) of 12 V. An oscillation frequency of \sim 18.4$ kHz is obtained from a five-stage flexible oxide-TFT-based CMOS voltage control ring oscillator at \text{V}_{\mathrm {DD}} of 12 V. Degradations of TFTs, inverters, and ring oscillators have been observed when a mechanical tensile strain is applied, whereas the influence of compressive strain is negligible. [ABSTRACT FROM PUBLISHER]

Organic thin-film transistors were fabricated directly on the surface of commercially available cleanroom paper using the vacuum-deposited small-molecule semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT). A thin, high-capacitance gate dielectric that allows the TFTs to be operated with low voltages of 2 V was employed. The TFTs have a charge-carrier mobility of 1.6 cm 2 /Vs, an on/off current ratio of 10 6 , and a subthreshold slope of 90 mV/decade. In addition, the TFTs also display a very large differential output resistance, which is an important requirement for applications in analog circuits and active-matrix displays. [ABSTRACT FROM AUTHOR]

Probing the role of the first monolayer in the evolution of the film polymer microstructure is essential for the fundamental understanding of the charge carrier transport in polymeric field-effect transistors (FETs). The monolayer and its subsequent microstructure of a conjugated polymer [poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene), PBTTT] film were fabricated via solution deposition by tuning the dip-coating speed and were then studied as accumulation and transporting layers in FETs. Investigation of the microstructure of the layers prepared at different coating velocities revealed that the monolayer serves as an important base for further development of the film. Significant improvement of the charge carrier transport occurs only at a critical multilayer network density that establishes the required percolation pathways for the charge carriers. Finally, at a low dip-coating speed, the polymer chains are uniaxially oriented, yielding pronounced structural anisotropy and high charge carrier mobilities of 1.3 cm² V-1 s-1 in the alignment direction. [ABSTRACT FROM AUTHOR]

An obstacle to the use of graphene as an alternative to silicon electronics has been the absence of an energy gap between its conduction and valence bands, which makes it difficult to achieve low power dissipation in the OFF state. We report a bipolar field-effect transistor that exploits the low density of states in graphene and its one-atomic-layer thickness. Our prototype devices are graphene heterostructures with atomically thin boron nitride or molybdenum disulfide acting as a vertical transport barrier. They exhibit room-temperature switching ratios of ≈50 and ≈10,000, respectively. Such devices have potential for high-frequency operation and large-scale integration. [ABSTRACT FROM AUTHOR]

We have developed NEMO-VN2, a new quantum device modeling tool that simulates a wide variety of quantum devices including the resonant tunneling diode, the single electron transistor, the molecular field effect transistor, the carbon nanotube field effect transistor, and the spin field effect transistor. In this work the nonequilibrium Green's function is used to performa comprehensive study of the emerging nanoelectronics devices. The program has been written by using graphic user interface of Matlab. NEMOVN2 uses Matlab to solve Schrodinger equation to get current-voltage characteristics of quantum devices. In the paper, we present a short overview of the theoretical methodology using non-equilibrium Green's function formodeling of various quantum devices and typical simulations used to illustrate the capabilities of the NEMO-VN2. [ABSTRACT FROM AUTHOR]

This letter reports the fabrication of a GaN heterostructure field-effect transistor with oxide spacer placed on the mesa sidewalls. The presence of an oxide spacer effectively eliminates the gate leakage current that occurs at the channel edge, where the gate metal is in contact with the 2-D electron gas edge on the mesa sidewall. From the two-terminal gate leakage current measurements, the leakage current was found to be several nA at VG=-12~V and <1~\muA at VG=-450~V. The benefits of the proposed spacer scheme include the patterning of the metal electrodes by plasma etching and a lower manufacturing cost. [ABSTRACT FROM AUTHOR]

Reducing the contact resistance without degrading the mobility property is crucial to achieve high-performance graphene field effect transistors. Also, the idea of modifying the graphene surface by etching away the deposited metal provides a new angle to achieve this goal. We exploit this idea by providing a new process method which reduces the contact resistance from 597 Ω·μm to sub 200 Ω·μm while no degradation of mobility is observed in the devices. This simple process method avoids the drawbacks of uncontrollability, ineffectiveness, and trade-off with mobility which often exist in the previously proposed methods. [ABSTRACT FROM AUTHOR]

In this paper, the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors (MOSFFETs) have been fabricated and characterized. A sandwich- (nitridation–oxidation–nitridation) type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H–SiC/SiO2 were examined by the measurement of HF I–V, G–V, and C–V over a range of frequencies. The ideal C–V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H–SiC was reduced to 2 × 1011 eV−1·cm−2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field-effect mobility is about 32.5 cm2·V−1·s−1, and the maximum peak field-effect mobility of 38 cm2·V−1·s−1 was achieved in fabricated lateral 4H–SiC MOSFFETs. [ABSTRACT FROM AUTHOR]