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Coherent Ising Machine (CIM) is a network of optical parametric oscillators that solve combinatorial optimization problems by finding the ground state of an Ising Hamiltonian. In CIMs, a problem arises when attempting to realize the Zeeman term because of the mismatch in size between interaction and Zeeman terms due to the variable amplitude of the optical parametric oscillator pulses corresponding to spins. There have been three approaches proposed so far to address this problem for CIM, including the absolute mean amplitude method, the auxiliary spin method, and the chaotic amplitude control (CAC) method. This paper focuses on the efficient implementation of Zeeman terms within the mean-field CIM model, which is a physics-inspired heuristic solver without quantum noise. With the mean-field model, computation is easier than with more physically accurate models, which makes it suitable for implementation in field programmable gate arrays and large-scale simulations. First, we examined the performance of the mean-field CIM model for realizing the Zeeman term with the CAC method, as well as their performance when compared to a more physically accurate model. Next, we compared the CAC method to other Zeeman term realization techniques on the mean-field model and a more physically accurate model. In both models, the CAC method outperformed the other methods while retaining similar performance. [ABSTRACT FROM AUTHOR]

A 1 millisecond (1‐ms) vision system that guarantees high efficiency and timely response for tomato defect detection is essential for factory automation. Because of various defect appearances, recently many existing researches focus on CNN based defect detection, but few of them attempt to reach high processing speed to adapt to the factorial assembly line. This paper proposes a global to multi‐scale local based parallel architecture with hardwired CNN for tomato defect detection. This architecture breaks down image‐wise detection into pixel‐wise localization and block‐wise classification. The pixel‐wise localization utilizes tomato‐aware information as constraints for localization performance. The block‐wise classification uses a fully pipelined network structure to obtain the classification result for each block as the pixel stream moves through the network. The classification network has a six‐layer lightweight network structure with quantization for hardwired type implementation on FPGA. The experiment results show that the proposed architecture processes 1000 FPS images with 0.9476 ms/frame delay. And for detection performance, this architecture keeps f1−score$f_{1}-score$ at 80.18%, only 1.31% lower than ResNet50 based detection system. [ABSTRACT FROM AUTHOR]

Polar codes are the popular error-correcting codes and increased their attention after being adopted for the control channel in fifth-generation new radio (5G NR) standards. An efficient hardware architecture for polar code is often required with minimal encoding and decoding complexity. This work proposes a Multi-folded pipelined architecture and analyzes the performance in terms of latency, hardware utilization, and throughput. The designed architecture has two folded architectures interconnected in parallel to output 4-bits simultaneously. Folding transformations are used to reduce the number of idle processing elements (PEs) in every stage leading to the effective utilization of PE. Precomputation is effectively utilized in the PE to reduce the critical path delay, which improves the maximum operating frequency. A Loop-based shifting register (LSR) is employed to reduce the number of registers used. The analytical model for latency and utilization rate has been derived from the scheduling of the proposed architecture. The proposed design shows 63–71% higher hardware utilization than conventional semi-parallel design for code length N = 512 suitable for the physical downlink control channel (PDCCH) in 5G NR. The architecture is also implemented in Virtex-6, ZYNQ-Ultrascale+ MPSoC device for maximum supported code length of 5G NR, i.e., up to 2 10 , compared with the existing decoders. The proposed design also has the benefit of lesser look-up-table (LUT) consumption and zero random-access-memory (RAM) usage with some additional registers, making it suitable for resource-constraint applications. [ABSTRACT FROM AUTHOR]

An improved combined-mode power converter (CMPC) for a solar photovoltaic (SPV) system is presented in this paper. Ten-power electronic switches are utilised for the functioning of the converter. The proposed converter has four modes of operation: buck, boost, inverter, and mixed mode. The new CMPC topology provides a unique and complex switching sequence for implementing the mixed-mode operation. This work uses a field-programmable gate array (FPGA) for mode selection and to create PWM (MS-PWM) signals. A digital MS-PWM controller is configured to switch between improved stepped perturb and observe (ISPO) maximum-power point tracking (MPPT) and sine wave PWM (SPWM). The ISPO provides the appropriate duty cycle for buck/boost operation, while the SPWM controls the inverter operation. This work's new digital PWM control algorithm supports mode selection, PWM generation, and reconfiguring PWM generation timings. The whole framework for constructing the MS-PWM controller employs a very high-speed integrated circuit hardware description language (VHDL). Simulation and experimental results are presented, proving that the digital MS-PWM controller uses fewer resources with improved accuracy. [ABSTRACT FROM AUTHOR]

This paper provides design framework of digital controller design for power conditioning unit comprising rectifier and boost converter for piezoelectric energy harvesting system. Complete design of digitally controlled boost converter interfaced with piezoelectric energy harvester has been carried out in this work. Simulation results validate the different theoretical aspects of design. Field Programmable Gate Array (FPGA) based hardware implementation of digital controller has been illustrated. [ABSTRACT FROM AUTHOR]

March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms. [ABSTRACT FROM AUTHOR]

Taking a lot of time to solve optimization problems has become a challenge for metaheuristic algorithms. Due to independence of the metaheuristics components, parallel processing is a good option to reduce the computational time and to find high quality solutions that are close to the optimum with an acceptable cost. One of these metaheuristic algorithms is the Sailfish Optimizer (SFO) which is inspired by a group of hunting sailfish. The SFO algorithm uses a simple method to provide a dynamic balance between exploration and exploitation phases, creates a swarm diversity, avoids local optima, and guarantees high convergence speed. It has been shown that the SFO algorithm outperforms various state-of-art metaheuristic algorithms for multimodal and high dimensional benchmark functions and complicated real-world optimization problems in terms of accuracy and speed by CPU and GPU implementation. In this paper, to speedup this algorithm and increase its performance we propose a reconfigurable hardware version of SFO implemented on Field Programmable Gate Array (FPGA). The FPGA-based SFO can be a very good option in many applications with massive calculations. Due to the inherent parallelism and high computing capabilities of FPGA, the SFO algorithm gains optimum computational time despite the complexity of optimization problems. We have compared the performance of the proposed FPGA-based SFO with its CPU and GPU implementation and some other metaheuristic algorithms. The results show the FPGA implementation is considerably faster than the CPU and GPU implementation. Also, it outperforms other compared FPGA-based metaheuristic algorithms in terms of execution time and convergence speed. [ABSTRACT FROM AUTHOR]

Nowadays, establishing security in data transmission is essential, and it is achieved by cryptography. Encryption of still or video images in specific applications such as Internet of Things, medical and satellite imaging, in applications requiring high-speed encryption, or even in applications where a personal computer is unavailable or cannot be used needs special hardware. In this paper, an image encryption algorithm based on chaos theory named Parallel Chaotic Checksum-based Image Encryption or PCCIE algorithm is proposed that has been able to provide a fast, efficient and secure algorithm with a hardware perspective on the design and parallel system structure. Using high-level synthesis, PCCIE is implemented on a Field Programmable Gate Array (FPGA). The proposed algorithm using small and independent local image buffers solved FPGA internal memory limitation for encryption of large images. Ultimately, a Hexa-core crypto-processor with single-precision floating-point and fixed-point precision has been designed, capable of encrypting 256 × 256 and Full HD images in 2.13 and 59.52 milliseconds, respectively, at 469 and 16 frames per second. [ABSTRACT FROM AUTHOR]

A key benefit of the Open Computing Language (OpenCL) software framework is its capability to operate across diverse architectures. Field programmable gate arrays (FPGAs) are a high-speed computing architecture used for computation acceleration. This study investigates the impact of memory access time on overall performance in general FPGA computing environments through the creation of eight benchmarks within the OpenCL framework. The developed benchmarks capture a range of memory access behaviors, and they play a crucial role in assessing the performance of spinning and sleeping on FPGA-based architectures. The results obtained guide the formulation of new implementations and contribute to defining an abstraction of FPGAs. This abstraction is then utilized to create tailored implementations of primitives that are well-suited for this platform. While other research endeavors concentrate on creating benchmarks with the Compute Unified Device Architecture (CUDA) to scrutinize the memory systems across diverse GPU architectures and propose recommendations for future generations of GPU computation platforms, this study delves into the memory system analysis for the broader FPGA computing platform. It achieves this by employing the highly abstracted OpenCL framework, exploring various data workload characteristics, and experimentally delineating the appropriate implementation of primitives that can seamlessly integrate into a design tailored for the FPGA computing platform. Additionally, the results underscore the efficacy of employing a task-parallel model to mitigate the need for high-cost synchronization mechanisms in designs constructed on general FPGA computing platforms. [ABSTRACT FROM AUTHOR]

Reconfigurable hardware, extensively employed in mission-critical digital applications like space and military electronics due to its adaptability, encounters the issue of soft errors, especially in control path elements, which could result in functional failure. Various system-level fault tolerance methodologies exist, and this paper implements a bio-inspired fault tolerance technique called evolvable hardware (EHW). The preferred implementation of the EHW system involves hosting the evolutionary algorithm on the processor alongside the reconfigurable hardware. However, this approach encounters delays in the intercommunication of the evolved circuit between the reconfigurable hardware and the processor. To address this issue, the paper proposes a two-tier architecture to achieve absolute fault mitigation in the controller. In this architecture, Tier-1 involves the digital implementation of the genetic algorithm on the reconfigurable hardware to mitigate errors in the controller, while Tier-2 focuses on mitigating errors occurring in Tier-1. The aim is to establish an absolute and self-resilient controller hardware to mitigate faults. The study simulates faults at the target circuit and genetic module as a proof of concept. The proposed two-tier single event upset (SEU) mitigation is deployed on Microsemi's ProAsic3e FPGA (Field Programmable Gate Array), achieving an average efficiency of 91%. This efficiency is accompanied by ten times lesser resource utilization compared to traditional methodologies and a 30% accelerated speed when compared to hybrid evolvable systems. [ABSTRACT FROM AUTHOR]

A new four-dimensional chaotic system with high complexity is proposed, and the analysis of its dynamics reveals that the system shows a rare topological attractor structure symmetry phenomenon. The phenomenon of inverse multiplicative bifurcation and multistability, which changes from a quadruple period to a double period and then to a single period, are found. A complex oscillatory transformation between chaos and period can be observed, highlighting the complexity of the system. The transient hyperchaos and burst oscillations are found in the time series and Lyapunov exponential spectra of the system, and the rich dynamical behavior of the system is verified by the 0–1 test and complexity spectral entropy test. The analog circuitry of the system is simulated based on Multisim, and the actual digital circuitry of the system is implemented through a Field Programmable Gate Array. The experimental results and the numerical simulation results agree and prove the feasibility of the constructed system. An image encryption algorithm is designed by combining the disruption-diffusion algorithm with the DNA encoding algorithm, and the system is analyzed and verified to be highly sensitive to the chaotic sequence key and initial value. Moreover, the key space of the algorithm is large and the information entropy is close to the ideal value, so the new system proposed can contribute to play a role in the field of secure communication. [ABSTRACT FROM AUTHOR]

This paper presents a novel discrete memristor model that incorporates exponential and absolute value functions. A discrete coupled memristor neural network model is constructed based on this memristor design. The periodic and chaotic regions of the discrete neural network model are determined using bifurcation and Lyapunov exponent spectrum. Furthermore, by varying the initial values of the discrete memristive neural network, we observe the coexistence of chaos and periodic attractors, as well as periodic attractors. Additionally, an application to color image encryption based on the discrete system model is given. Security analysis is conducted in the aspects of key space, histogram analysis, correlation analysis, sensitivity analysis, Peak Signal-to-Noise Ratio (PSNR), and information entropy analysis. The analysis results show that the algorithm has a key space size of 2 2 5 8 , and the information entropy of baboon graph is 7.9993, which is very close to the ideal value of 8. It shows that the image encryption algorithm is feasible and effective. Finally, the implementation of the discrete memristive neural network model is realized using Field Programmable Gate Array (FPGA). The experimental implementation is conducted using the Verilog language on the Vivado 2018.3 platform, and the obtained results align with the numerical simulation results obtained through MATLAB. [ABSTRACT FROM AUTHOR]

Measurement of vibration without having contact with the target is crucial for many applications. However, real time vibration signals are frequently mixed with various levels of dynamic noises. In this research, a non-contact type vibration measurement system based on laser triangulation method is proposed by using a PSD (Position sensitive detector) and here a single axis Brüel and Kjaer piezoelectric accelerometer is used to validate the experimental results. The primary goal of this measurement system is to develop a Gabor Transform based signal denoising technique, in order to eliminate noise from the real-time vibration data. Furthermore, PSD platform vibration, which might cause unanticipated inaccuracies in the detected vibration data, has also been eliminated by utilizing a self-vibration compensation approach using an ADXL-345 three-axis accelerometer. The self-vibration compensated vibration measurement technique has been designed using an NI (national instruments) cRIO (CompactRIO) 9074 real-time FPGA (field programmable gate array) based embedded controller. Consequently, a Gabor Transform and Expansion-based Signal Processing Technique is designed using NI cRIO-9074 real time platform to reduce external noise from the self-vibration compensated vibration data. It has been observed that the implementation of Gabor Transform has improved the performance of the system in term of enhancing the SNR (Signal-to-noise ratio). [ABSTRACT FROM AUTHOR]

In this letter, a tunable hybrid metasurface (THMS) with electromagnetic switching characteristics based on the field‐programmable logic gate array (FPGA) is developed, which combines the mechanisms of both phase cancellation and absorption. Compared to other hybrid metasurface, the proposed design possesses two major functions of electromagnetic switching and dynamic tuning. By adjusting the bias voltage of the active components controlled by FPGA module, the in‐band tuning and active switching at different frequency bands of 3.63–5.57, 4.86–10.47, and 9.40–12.36 GHz can be obtained. A physical prototype with the size of 350 mm × 370 mm is fabricated and measured for verification, and the measurement shows that the monostatic radar cross section achieves varying degrees of reduction from 1.66 to 12.04 GHz. [ABSTRACT FROM AUTHOR]

Approximation approaches have been developed for very large-scale integration architecture to limit power consumption and increase effective throughput. The full adder (FA) and block-based designs are the approximate adder designs widely used in the existing techniques to accelerate the additions by partitioning a long carry propagation chain. However, these techniques require more power and area than the standard FA-based techniques. To overcome this issue, this paper presents an error-reduced carry prediction approximate full adder (ERCPAA) technique to achieve faster additions and performance by adding a constant truncation mechanism with an error reduction strategy. Deep learning and neural network technology had made great progress in recent years for field programmable gate array implementation and real-time object detection. It is essential to maintain high accuracy rates in image processing applications, as any errors introduced during the processing can significantly impact the quality of the output image and impact the hardware implementation. Therefore, we propose an ERCPAA that utilizes a lightweight convolutional neural network (ERCPAA–lightweight CNN) to fit well in a fixed-point CNN accelerator architecture. A lightweight CNN that is both thin (with fewer feature maps per layer) and deep (four layers) with just one fully connected hidden layer can enable faster training while achieving higher accuracy. In addition, in a few positions of the higher-order bits of the incorrect part, a full adder (FA) cell is used to simplify the traditional one-bit FA cell, creating an approximate summation and carry. The proposed method is verified by randomly selecting specific images from the Fruit 360, ImageNet, and the Caltech 256 Image Dataset. The proposed model offers an normalized mean error distance, error rate, and mean relative error distance values of 0.154, 6.55%, and 4.6E-4. The recognition accuracy of the proposed model in the ImageNet database is 96% with an execution time of 1420 µs. [ABSTRACT FROM AUTHOR]

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%). [ABSTRACT FROM AUTHOR]

Developing chaotic systems-on-a-chip is gaining much attention due to its great potential in securing communication, encrypting data, generating random numbers, and more. The digital implementation of chaotic systems strives to achieve high performance in terms of time, speed, complexity, and precision. In this paper, the focus is on developing high-speed Field Programmable Gate Array (FPGA) cores for chaotic systems, exemplified by the Lorenz system. The developed cores correspond to numerical integration techniques that can extend to the equations of the sixth order and at high precision. The investigation comprises a thorough analysis and evaluation of the developed cores according to the algorithm complexity and the achieved precision, hardware area, throughput, power consumption, and maximum operational frequency. Validations are done through simulations and careful comparisons with outstanding closely related work from the recent literature. The results affirm the successful creation of highly efficient sixth-order Lorenz discretizations, achieving a high throughput of 3.39 Gbps with a precision of 16 bits. Additionally, an outstanding throughput of 21.17 Gbps was achieved for the first-order implementation coupled with a high precision of 64 bits. These outcomes set our work as a benchmark for high-performance characteristics, surpassing similar investigations reported in the literature. [ABSTRACT FROM AUTHOR]

Background: FLASH Radiotherapy (RT) is an emergent cancer RT modality where an entire therapeutic dose is delivered at more than 1000 times higher dose rate than conventional RT. For clinical trials to be conducted safely, a precise and fast beam monitor that can generate out‐of‐tolerance beam interrupts is required. This paper describes the overall concept and provides results from a prototype ultra‐fast, scintillator‐based beam monitor for both proton and electron beam FLASH applications. Purpose: A FLASH Beam Scintillator Monitor (FBSM) is being developed that employs a novel proprietary scintillator material. The FBSM has capabilities that conventional RT detector technologies are unable to simultaneously provide: (1) large area coverage; (2) a low mass profile; (3) a linear response over a broad dynamic range; (4) radiation hardness; (5) real‐time analysis to provide an IEC‐compliant fast beam‐interrupt signal based on true two‐dimensional beam imaging, radiation dosimetry and excellent spatial resolution. Methods: The FBSM uses a proprietary low mass, less than 0.5 mm water equivalent, non‐hygroscopic, radiation tolerant scintillator material (designated HM: hybrid material) that is viewed by high frame rate CMOS cameras. Folded optics using mirrors enable a thin monitor profile of ∼10 cm. A field programmable gate array (FPGA) data acquisition system generates real‐time analysis on a time scale appropriate to the FLASH RT beam modality: 100–1000 Hz for pulsed electrons and 10–20 kHz for quasi‐continuous scanning proton pencil beams. An ion beam monitor served as the initial development platform for this work and was tested in low energy heavy‐ion beams (86Kr+26 and protons). A prototype FBSM was fabricated and then tested in various radiation beams that included FLASH level dose per pulse electron beams, and a hospital RT clinic with electron beams. Results: Results presented in this report include image quality, response linearity, radiation hardness, spatial resolution, and real‐time data processing. The HM scintillator was found to be highly radiation damage resistant. It exhibited a small 0.025%/kGy signal decrease from a 216 kGy cumulative dose resulting from continuous exposure for 15 min at a FLASH compatible dose rate of 237 Gy/s. Measurements of the signal amplitude versus beam fluence demonstrate linear response of the FBSM at FLASH compatible dose rates of >40 Gy/s. Comparison with commercial Gafchromic film indicates that the FBSM produces a high resolution 2D beam image and can reproduce a nearly identical beam profile, including primary beam tails. The spatial resolution was measured at 35–40 µm. Tests of the firmware beta version show successful operation at 20 000 Hz frame rate or 50 µs/frame, where the real‐time analysis of the beam parameters is achieved in less than 1 µs. Conclusions: The FBSM is designed to provide real‐time beam profile monitoring over a large active area without significantly degrading the beam quality. A prototype device has been staged in particle beams at currents of single particles up to FLASH level dose rates, using both continuous ion beams and pulsed electron beams. Using a novel scintillator, beam profiling has been demonstrated for currents extending from single particles to 10 nA currents. Radiation damage is minimal and even under FLASH conditions would require ≥50 kGy of accumulated exposure in a single spot to result in a 1% decrease in signal output. Beam imaging is comparable to radiochromic films, and provides immediate images without hours of processing. Real‐time data processing, taking less than 50 µs (combined data transfer and analysis times), has been implemented in firmware for 20 kHz frame rates for continuous proton beams. [ABSTRACT FROM AUTHOR]

An educational studies and understanding about theoretical and practical laboratory in power quality issues. Interline dynamic voltage restorer is used in the proposed system for mitigating voltage sag, swell, harmonics, and interruptions. The conventional topology of dynamic voltage restorer possessing voltage source inverter is modified into a switched coupled inductor inverter which has the clear edge in power transfer over the former one. The versatility of the controller is enhanced in this work by deploying an artificial neural network combined discrete wavelet transform. The artificial neural network and discrete wavelet transform aided pulse width modulation generation enhances the controller performance by mitigating the harmonics considerably. The simulation and experimental results reveal that interline dynamic voltage restorer renders solution for major power quality issues like voltage sag and swell. Interline dynamic voltage restorer-based SCII is implemented with field programmable gate array Spartan 6 controller and signal processing technique such as discrete wavelet transform that mitigates voltage sag and harmonics. Paper is constructed such that the students in Bachelor's and Master's program of Electrical engineering can understand the power quality, various issues, and mitigating the total harmonic distortion value. The equations related to real power transfer are derived which enable the students to clearly understand about the power exchange between the feeders. Further, it is applied in practical laboratory setup facility for understanding about power quality issues to students of both undergraduate and postgraduate courses. [ABSTRACT FROM AUTHOR]

In contemporary warfare, radar countermeasures have become multifunctional and intelligent, rendering the conventional jamming method and platform unsuitable for the modern radar countermeasures battlefield due to their limited efficiency. Reinforcement learning has been proven to be a practical solution for cognitive jamming decision-making in the cognitive electronic warfare. In this paper, we proposed a radar-jamming decision-making algorithm based on an improved Q-Learning algorithm. This improved Q-Learning algorithm ameliorated the problem of overestimating the Q-value that exists in the Q-Learning algorithm by introducing a second Q-table. At the same time, we performed a comprehensive design and implementation based on the classical Q-Learning algorithm, deploying it to a Field Programmable Gate Array (FPGA) hardware. We decomposed the implementation of the reinforcement learning algorithm into individual steps and described each step using a hardware description language. Then, the reinforcement learning algorithm can be computed on FPGA by linking the logic modules with valid signals. Experiments show that the proposed Q-Learning algorithm obtains considerable improvement in performance over the classical Q-Learning algorithm. Additionally, they confirm that the FPGA hardware can achieve great efficiency improvement on the radar-jamming decision-making algorithm implementation. [ABSTRACT FROM AUTHOR]

The low-bit quantization can effectively reduce the deep neural network storage as well as the computation costs. Existing quantization methods have yielded unsatisfactory results when being applied to lightweight networks. Additionally, following network quantization, the differences in data types between the operators can cause issues when deploying networks on Field Programmable Gate Arrays (FPGAs). Moreover, some operators cannot be accelerated heterogeneously on FPGAs, resulting in frequent switching between the Advanced RISC Machine (ARM) and FPGA environments for computation tasks. To address these problems, this paper proposes a custom network quantization approach. Firstly, an improved PArameterized Clipping Activation (PACT) method is employed during the quantization aware training to restrict the value range of neural network parameters and reduce the loss of precision arising from quantization. Secondly, the Consecutive Execution Of Convolution Operators (CEOCO) strategy is utilized to mitigate the resource consumption caused by the frequent environment switching. The proposed approach is validated on Xilinx Zynq Ultrascale+MPSoC 3EG and Virtex UltraScale+XCVU13P platforms. The MobileNetv1, MobileNetv3, PPLCNet, and PPLCNetv2 networks were utilized as testbeds for the validation. Moreover, experimental results are on the miniImageNet, CIFAR-10, and OxFord 102 Flowers public datasets. In comparison to the original model, the proposed optimization methods result in an average decrease of 1.2% in accuracy. Compared to conventional quantization method, the accuracy remains almost unchanged, while the frames per second (FPS) on FPGAs improves by an average of 2.1 times. [ABSTRACT FROM AUTHOR]

Absolute distance measurements based on femtosecond lasers have been extensively studied for precision metrology and advanced manufacturing, with the advantages of traceability, high speed, and nanometer precision. However, in previous studies, the dual femtosecond laser ranging system showed limitations such as system complexity, lower integration, dead zone problems in single optical path detection, and high requirements for laser coherence. It is challenging to achieve a high degree of integration and large-scale continuous measurements using femtosecond lasers, ineluctably limiting practical applications in engineering fields. Here, based on the free-running dual femtosecond lasers and the nonlinear asynchronous optical sampling method, we design a highly integrated absolute distance meter. In particular, the dead zone problem is solved by the polarization multiplexing technique, and the digital control system and signal processing system are completed by the Field Programmable Gate Array (FPGA). The absolute distance meter enables rapid, continuous, and accurate measurements over a considerable range without dead zones, which paves a promising way for the integration, instrumentation, and industrial applications of femtosecond laser ranging systems. [ABSTRACT FROM AUTHOR]

In a resource-constrained environment of the 21st century, the use of hardware-based reconfigurable systems such as Field Programmable Gate Array (FPGAs) is considered an effective way to enhance information security. In comparison with traditional custom circuitry that does not give a flexible approach, it is observed that the reconfigurable hardware shows an excellent potential for cyber security by increasing hardware speeds and flexibility. Therefore, in a quest to integrate multi-core systems, the Network-on-Chip (NoC) has become one of the popular widespread techniques to maximize router security. Due to the significant overhead of chip space and the power consumption of the routers, it is substantially more expensive to construct as compared to a bus-based system. The control component (CC) interacts with the networks that inject packets based on router switching and activity. These control components are coupled with each network to produce a system of controlled networks. The system is further linked with CFM or a Centralized Fabric Manager, which serves as the network's focal point. After that, the CFM runs the algorithm regularly. The analytic parameters comprise flip flop, power, latency, number of lookup tables (LUTs), and throughput. In the proposed method, the number of LUTs is 0. 3 5 mm 2 , the flip flop is 3. 5 mm 2 , the power is 3. 4 μ W, the latency is 5941 ns, and the planned throughput is 0.56 flits/cycle. Results indicate that the crossbar switch reduces errors and minimizes the delay in the architecture's outcome level, which further overcomes the descriptions of performance, power throughput, and area delay parameters. The findings of the research can be useful to enhance information security among lightweight devices besides minimizing the chances of network attacks in today's dynamic and complex cyberspace. [ABSTRACT FROM AUTHOR]

We report on the operation of a coherent population trapping (CPT) microcell atomic clock using a pulsed Ramsey-like interrogation. The Ramsey-CPT sequence, defined by two-step optical pulses separated by a free-evolution dark time, is produced by switching on and off the output power of a low-power vertical-cavity surface-emitting laser, through direct modulation of its driving current. High-contrast and narrow Ramsey-CPT fringes are detected without the use of any external optical modulator stage. We demonstrate closed-loop operation of the clock based on high-speed digital signal processing implemented in a field programmable gate array board. The clock's short-term fractional frequency stability is 1.3 × 10−10 τ − 1 / 2 until 2000 s. A power light-shift coefficient of 8 × 10−11/μW, in relative value, is obtained for a dark time of 150 μs. This value is about ten times lower than in the continuous regime. These results show the feasibility of fully integrated atomic clocks based on Ramsey spectroscopy, which could provide enhanced long-term stability. [ABSTRACT FROM AUTHOR]

Ocean bottom electromagnetic receivers (OBEMs) are invaluable tools for observing seafloor electromagnetic signals, primarily used in magnetotelluric (MT) sounding and marine controlled source electromagnetics (MCSEM). However, the high operational costs of deploying OBEMs require thorough pre-deployment testing to enhance the data reliability and quality. Commercial signal generators used for MT and controlled source electromagnetic (CSEM) testing often fall short of the restricted terms of the frequency range, signal-to-noise ratio, storage depth, time synchronization, and amplitude dynamics. To address these limitations, we developed a specialized marine MT and CSEM signal simulative generator. The generator employs pseudorandom number code-based white noise to simulate MT signals and uses multi-frequency synthesis and amplitude modulation (AM) to generate CSEM signals. The system is developed using a low-power microcontroller unit and a field programmable gate array platform, integrating various circuits such as power, clock, encoding, control, data storage, chopper, and amplification circuits. The generator simultaneously outputs four-channel white noise and AM signals. The white noise feature provides a wide and adjustable frequency band and amplitude, while the AM feature provides a large dynamic amplitude range and multi-frequency synthesis at various carrier frequency points. Comprehensive testing verified the performance of the proposed simulative generator. The test results demonstrate that the MT simulated signals cover a frequency range from 1 E4s to 100 Hz, providing adjustable amplitudes between 10 μVpp and 10 mVpp. The CSEM simulated signals include standard square waves, third harmonic waves, and seventh harmonic waves, with amplitudes adjustable from 10 mVpp to 10 Vpp. The proposed simulative generator enhances the efficiency of OBEM functional testing and provides essential equipment support for maintaining the quality of marine data. [ABSTRACT FROM AUTHOR]

Fractional-order differentiation (FOD) can record information from the past, present, and future. Compared with integer-order systems, FOD systems have higher complexity and more accurate ability to describe the real world. In this paper, two types of fractional-order memristors are proposed and one type is proved to have extreme multistability, local activity, and non-volatility. By using memristors to simulate the autapse of a neuron and to describe the phenomenon of electromagnetic induction caused by electromagnetic radiation, we establish a new 5D FOD memristive HNN (FOMHNN). Through dynamic simulation, rich dynamic behaviors are found, such as hyperchaos, multiscroll, extreme multistability, and "overclocking" behavior caused by order reduction. To the best of our knowledge, this is the first time that such rich dynamic behaviors are found in FOMHNN simultaneously. Based on this FOMHNN, a very efficient and secure image encryption scheme is designed. Security analysis shows that the encrypted Lena image has extremely low adjacent pixel correlation and high randomness, with information entropy of 7.9995. Despite discarding diffusion and scrambling, it has excellent plaintext sensitivity, with NCPR = 99.6095% and UACI = 33.4671%. Finally, this paper implements the proposed FOMHNN and image encryption on field programmable gate array (FPGA). To our knowledge, the related work of fully hardware implementation of fractional-order neural networks and image encryption schemes based on this is rare. [ABSTRACT FROM AUTHOR]

The majority of data exchanged between connected devices are confidential and must be protected against unauthorized access. To ensure data protection, so-called cryptographic algorithms are used. These algorithms have proven to be mathematically secure against brute force due to the key length, but their physical implementations are vulnerable against physical attacks. The physical implementation of these algorithms can result in the disclosure of information that can be used to access confidential data. Some of the most powerful hardware attacks presented in the literature are called fault injection attacks. These attacks involve introducing a malfunction into the normal operation of the device and then analyzing the data obtained by comparing them with the expected behavior. Some of the most common methods for injecting faults are the variation of the supply voltage and temperature or the injection of electromagnetic pulses. In this paper, a hardware design methodology using analog-to-digital converters (ADCs) is presented to detect attacks on cryptocircuits and prevent information leakage during fault injection attacks. To assess the effectiveness of the proposed design approach, FPGA-based ADC modules were designed that detect changes in temperature and supply voltage. Two setups were implemented to test the scheme against voltage and temperature variations and injections of electromagnetic pulses. The results obtained demonstrate that, in 100% of the cases, when the correct operating voltage and temperature range were established, the detectors could activate an alarm signal when the cryptographic module was attacked, thus avoiding confidential information leakage and protecting data from being exploited. [ABSTRACT FROM AUTHOR]

Rapid detection of fish freshness is of vital importance to ensuring the safety of aquatic product consumption. Currently, the widely used optical detecting methods of fish freshness are faced with multiple challenges, including low detecting efficiency, high cost, large size and low integration of detecting equipment. This research aims to address these issues by developing a low-cost portable fluorescence imaging device for rapid fish freshness detection. The developed device employs ultraviolet-light-emitting diode (UV-LED) lamp beads (365 nm, 10 W) as excitation light sources, and a low-cost field programmable gate array (FPGA) board (model: ZYNQ XC7Z020) as the master control unit. The fluorescence images captured by a complementary metal oxide semiconductor (CMOS) camera are processed by the YOLOv4-Tiny model embedded in FPGA to obtain the ultimate results of fish freshness. The circuit for the YOLOv4-Tiny model is optimized to make full use of FPGA resources and to increase computing efficiency. The performance of the device is evaluated by using grass carp fillets as the research object. The average accuracy of freshness detection reaches up to 97.10%. Moreover, the detection time of below 1 s per sample and the overall power consumption of 47.1 W (including 42.4 W light source power consumption) indicate that the device has good real-time performance and low power consumption. The research provides a potential tool for fish freshness evaluation in a low-cost and rapid manner. [ABSTRACT FROM AUTHOR]

Due to the absence of communication and coordination with external spacecraft, non-cooperative spacecraft present challenges for the servicing spacecraft in acquiring information about their pose and location. The accurate segmentation of non-cooperative spacecraft components in images is a crucial step in autonomously sensing the pose of non-cooperative spacecraft. This paper presents a novel overlay accelerator of DeepLab Convolutional Neural Networks (CNNs) for spacecraft image segmentation on a FPGA. First, several software–hardware co-design aspects are investigated: (1) A CNNs-domain COD instruction set (Control, Operation, Data Transfer) is presented based on a Load–Store architecture to enable the implementation of accelerator overlays. (2) An RTL-based prototype accelerator is developed for the COD instruction set. The accelerator incorporates dedicated units for instruction decoding and dispatch, scheduling, memory management, and operation execution. (3) A compiler is designed that leverages tiling and operation fusion techniques to optimize the execution of CNNs, generating binary instructions for the optimized operations. Our accelerator is implemented on a Xilinx Virtex-7 XC7VX690T FPGA at 200 MHz. Experiments demonstrate that with INT16 quantization our accelerator achieves an accuracy (mIoU) of 77.84%, experiencing only a 0.2% degradation compared to that of the original fully precision model, in accelerating the segmentation model of DeepLabv3+ ResNet18 on the spacecraft component images (SCIs) dataset. The accelerator boasts a performance of 184.19 GOPS/s and a computational efficiency (Runtime Throughput/Theoretical Roof Throughput) of 88.72%. Compared to previous work, our accelerator improves performance by 1.5× and computational efficiency by 43.93%, all while consuming similar hardware resources. Additionally, in terms of instruction encoding, our instructions reduce the size by 1.5× to 49× when compiling the same model compared to previous work. [ABSTRACT FROM AUTHOR]

The purpose is to explore the effect of iris image acquisition and real-time detection systems based on Convolutional Neural Network (CNN) and improve the efficiency of iris real-time detection. Based on existing iris data acquisition and detection systems, this study uses the light field focusing algorithm to collect iris data in live, introduces CNN in Deep Learning (DL) algorithm, and designs an iris image acquisition and live detection system based on CNN. Afterward, Radial Basis Function (RBF)-Support Vector Machines (SVM) algorithm is used to classify iris feature information. Based on Field Programmable Gate Array (FPGA), a system for iris image acquisition, processing, and display is constructed. Finally, the performance of the constructed system and algorithm are analyzed through simulation experiments. The research results show that the proposed algorithm can automatically select the qualified iris images in live, significantly improve the recognition accuracy of the whole iris recognition system, and the average time of live quality evaluation for each frame image is less than 0.05 s. The focal point of the investigation involves the exploration of a CNN-based iris image acquisition and real-time detection system, with an emphasis on enhancing the efficiency of real-time iris detection. The innovation of this research lies in the integration of deep learning algorithms and light-field focusing techniques, applied to the reconstruction of a FPGA system. Further, the proposed algorithm is compared with Super-Resolution Using Very Deep Convolutional Networks (VDSR), Deeply Recursive Convolutional Network (DRCN), Residual Dense Network (RDN), and Bicubic. The comparison analysis suggests that the recognition accuracy of the proposed algorithm is the highest, close to 100%. Additionally, the proposed algorithm is compared with the Image Quality Evaluation-based Algorithm (IQA) and the Feature Extraction-based Algorithm (FEA), showing that the proposed RBF-SVM algorithm has higher classification accuracy (96.38%) and lower Average Classification Error Rate (ACER) (3.69%). The research results can provide a reference for live iris image detection and data acquisition. [ABSTRACT FROM AUTHOR]

Ultra-narrow pulses serve as critical components in numerous applications. These pulses have ultra-fast leading edges that typically function as precision trigger signals to synchronize various instruments. Ultra-narrow pulses inherently exhibit an ultra-wide bandwidth, gaining significant attention in diverse electronic systems encompassing communications, radar imaging, electronic warfare, and others. Although several techniques have been explored for generating ultra-narrow pulses, field programmable gate arrays (FPGAs) offer a promising alternative in terms of flexibility and integration. This study introduces a scalable delay pulse synchronizer method with a resolution of 23 ps. A programmable, successive, narrow pulse sequence operating at a 1-GHz repetition frequency is implemented within a monolithic FPGA. The performance of the proposed method is evaluated using an existing board with a general commercial FPGA in the laboratory. This new method presents a convenient and efficient approach of achieving ultra-narrow pulse synchronization, being applicable across various fields. [ABSTRACT FROM AUTHOR]

A sub-nanosecond clock synchronization scheme based on the field programmable gate array (FPGA) is proposed for the Fiber Channel (FC) communication system in this paper. The counter value of the slave node is synchronized to that of the master node through the embedded IEEE 1588 protocol over the communication link. In order to ensure the counter clocks have the same frequency in both nodes, which is recovered from the FC communication link, the clock phase difference is measured by the digital dual mixer time difference technique and the data recovery technique in the Gigabyte Transceiver, and then it is compensated by the mixed-mode clock manager in FPGAs. The proposed clock synchronization approach is evaluated with an FC communication system that has a serial rate of 12.5 Gbps, and the reported experimental results show that the proposed clock synchronization module can achieve a time difference lower than 1 ns. [ABSTRACT FROM AUTHOR]

Microwave radiometers, possessing all-day and all-weather operational capabilities, are extensively utilized in the exploration of planetary atmospheres and surfaces. The potential of the hyperspectral detection technology to enhance the precision and resolution of microwave radiometer detection has made it a crucial research focus. This paper introduces an intermediate frequency (IF) module for hyperspectral microwave radiometers. The IF module is constructed with two 6.4 gigabit samples per second sampling-rate analog-to-digital converter (ADC) chips and a Xilinx Virtex-7 field programmable gate array. By implementing a parallel fast Fourier transform algorithm and a pipeline architecture, the IF module can efficiently process all ADC sampling data in real-time, generating 512 channels of output for each ADC. The test results, including linearity, sensitivity, and flatness, are presented and thoroughly analyzed for the IF module. Furthermore, the module is interfaced with the radio frequency front-end of the microwave radiometer to measure hot and cold calibration sources and assess its sensitivity. When combined with a suitable front-end receiver, the IF module can form a radiometer system suitable for various applications of microwave remote sensing. [ABSTRACT FROM AUTHOR]

By utilizing Field Programmable Gate Arrays in a configuration similar to that of the Mirror Langmuir Probe, it is possible to bias a single probe at three precise voltages in sequence. These voltages can be dynamically adjusted in real-time based on the measured plasma electron temperature to ensure the transition region is always sampled. The first results have been obtained by employing this method and have generated real-time outputs of electron temperature, ion saturation current, and floating potential on a low temperature pulsed-DC magnetron at 500 kHz. These results are in good agreement with the analysis of a conventionally swept Langmuir probe. This probe is designed with the intention of being implemented on MAST-U to aid in the study of exhaust physics and enable further investigation into filamentary behavior. [ABSTRACT FROM AUTHOR]

A complex-valued self-ordering radix-2 memory-based Fast Fourier Transform (FFT) architecture suitable for low end Field Programmable Gate Arrays (FPGA) is presented. Employing a self-ordering algorithm within the data flow, both input and output data are kept in normal sequential order, not in digit-reversed-order. This way, with an appropriate scheduling, last stage of the FFT and I/O operations are performed in parallel with no wait states. Self-ordering FFT algorithms are generally designed for software implementations. We designed and implemented one on FPGA (hardware), showing that considerable number of clock cycle savings can be obtained compared to unordered FFT counterparts. The approach is implemented on various FPGAs. The results are compared with similar radix-2 architectures in terms of required clock cycles and resource usage, confirming the advantage of the approach. [ABSTRACT FROM AUTHOR]

The discrete Fourier transform (DFT) is the most commonly used signal processing method in modern digital sensor design for signal study and analysis. It is often implemented in hardware, such as a field programmable gate array (FPGA), using the fast Fourier transform (FFT) algorithm. The frequency resolution (i.e., frequency bin size) is determined by the number of time samples used in the DFT, when the digital sensor's bandwidth is fixed. One can vary the sensitivity of a radio frequency receiver by changing the number of time samples used in the DFT. As the number of samples increases, the frequency bin width decreases, and the digital receiver sensitivity increases. In some applications, it is useful to compute an ensemble of FFT lengths; e.g., 2 P − j for j = 0 ,   1 ,   2 ,   ... ,   J , where j is defined as the spectrum level with frequency resolution   2 j · Δ f . Here Δ f is the frequency resolution at j = 0 . However, calculating all of these spectra one by one using the conventional FFT method would be prohibitively time-consuming, even on a modern FPGA. This is especially true for large values of P ; e.g., P ≥ 20 . The goal of this communication is to introduce a new method that can produce multi-resolution spectrum lines corresponding to sample lengths   2 P − j for all J + 1 levels, concurrently, while one long 2 P -length FFT is being calculated. That is, the lower resolution spectra are generated naturally as by-products during the computation of the 2 P -length FFT, so there is no need to perform additional calculations in order to obtain them. [ABSTRACT FROM AUTHOR]

In recent years, radar emitter signal recognition has enjoyed a wide range of applications in electronic support measure systems and communication security. More and more deep learning algorithms have been used to improve the recognition accuracy of radar emitter signals. However, complex deep learning algorithms and data preprocessing operations have a huge demand for computing power, which cannot meet the requirements of low power consumption and high real-time processing scenarios. Therefore, many research works have remained in the experimental stage and cannot be actually implemented. To tackle this problem, this paper proposes a resource reuse computing acceleration platform based on field programmable gate arrays (FPGA), and implements a one-dimensional (1D) convolutional neural network (CNN) and long short-term memory (LSTM) neural network (NN) model for radar emitter signal recognition, directly targeting the intermediate frequency (IF) data of radar emitter signal for classification and recognition. The implementation of the 1D-CNN-LSTM neural network on FPGA is realized by multiplexing the same systolic array to accomplish the parallel acceleration of 1D convolution and matrix vector multiplication operations. We implemented our network on Xilinx XCKU040 to evaluate the effectiveness of our proposed solution. Our experiments show that the system can achieve 7.34 giga operations per second (GOPS) data throughput with only 5.022 W power consumption when the radar emitter signal recognition rate is 96.53%, which greatly improves the energy efficiency ratio and real-time performance of the radar emitter recognition system. [ABSTRACT FROM AUTHOR]

In this paper, the improved design of an Ice Giants Net Flux Radiometer (IG-NFR), for inclusion as a payload on a future Uranus probe mission, is given. IG-NFR will measure the net radiation flux, in seven spectral bands, each with a 10° Field-Of-View (FOV) and in five viewing angles as a function of altitude. Net flux measurements within spectral filter bands, ranging from solar to far-infrared, will help derive radiative heating and cooling profiles, and will significantly contribute to our understanding of the planet's atmospheric heat balance and structure, tropospheric 3-D flow, and compositions and opacities of the cloud layers. The IG-NFR uses an array of non-imaging Winston cones integrated to a matched thermopile detector Focal Plane Assembly (FPA), with individual bandpass filters and windows, housed in a vacuum micro-vessel. The FPA thermopile detector signals are read out in parallel mode, amplified and processed by a multi-channel digitizer application specific integrated circuit (MCD ASIC) under field programmable gate array (FPGA) control. The vacuum micro-vessel rotates providing chopping between FOV's of upward and downward radiation fluxes. This unique design allows for small net flux measurements in the presence of large ambient fluxes and rapidly changing temperatures during the probe descent to ≥10 bar pressure. [ABSTRACT FROM AUTHOR]

This article proposes an adaptive Kernel-Hebbian least mean square (KHLMS) controller for a dual voltage source inverter (VSI). The recommended topology consists of a distributed energy resource (DER) supported VSI called main VSI (MVSI) and split capacitor supported VSI termed as auxiliary VSI (AVSI). Both the MVSI and AVSI are used to serve the shunt compensation when DER is not integrated with MVSI. The DER scenario is considered to suppress the active power flow shortage in the utility grid. Here, optimal active power flow control (OAPFC) is managed by MVSI and shunt compensation is achieved by AVSI during DER operated mode. Hence, a dual VSI based distribution static compensator (DSTATCOM) facilitates the configuration merits such as reduction in system downtime cost, filter rating switching stress etc. Supremacy of both the neural network (NN) based controller and topology is presented by comparing VSI (called AVSI) in the context of harmonic reduction in source side, voltage balancing, power factor (PF) enhancement, better voltage regulation and OAPFC. The experimental results are obtained through field programmable gate array (FPGA) based hardware units which exhibit radical improvement in the power quality (PQ) conferring as per the international standard grid code (IEEE-519-2017). [ABSTRACT FROM AUTHOR]

In Healthcare 4.0, Wireless Body Area Networks (WBAN) takes place a major role in gathering real-time data of patients. The gathered real-time medical data is transferred through an insecure channel which may lead to several security attacks. To secure from these attacks, the methodology adopted in this work involves the use of a lightweight secure anonymous authentication scheme with location privacy and the implementation of a WBAN system using a cadence tool. Moreover, the methodology encompasses several stages, including initialization, registration, authentication, and location privacy. Further, the study adopts a systematic approach to address key challenges, such as integrity, privacy, security, and non-repudiation. The hypothesis underlying this research is that WBANs can provide accurate and real-time healthcare monitoring using an anonymous authentication scheme and validated by using cadence software. In this work, a digital signature-based cryptographic technique is used to verify the authenticity and integrity of the messages. The security analysis section proves that the system is efficient in resisting different security attacks. Though there are several existing works related to authentication, the proposed protocol is very efficient in terms of performance analysis parameters which are validated using Cygwin software. Computational cost is diminished by 13% and communication overhead is reduced by 32% when compared to the relevant recent works. Additionally, a practical hardware approach is designed using a Verilog Hardware description language and implemented in hardware on an Arty A7-100 SoC FPGA (Silicon on Chip Field Programmable Gate Array) Development board where the number of bonded IOBs utilization is only 10% and lastly synthesized using a Cadence tool with CMOS GPDK 90 nm technology. [ABSTRACT FROM AUTHOR]

Downhole electric pulse technology is one of the new ways to achieve unblocked oil and gas wells to increase production, and the discharge switch is the basis to support its generation of shock pressure waves. A new type of oil and gas well production enhancement experimental device using thyristor series to constitute a discharge switch was designed for the disadvantage of uncontrollable discharge voltage of oil and gas well production enhancement device based on self-triggered gas switch. To ensure that the experimental device is safely used in high-power and high-voltage applications, static and dynamic voltage equalization circuits were designed to avoid overvoltage breakdown of the thyristor when the device is in operation. Using a field programmable gate array (FPGA) as the main control chip, the thyristor was controlled to conduct and discharge, achieving controllable adjustment of discharge voltage. The high-voltage energy extraction circuit was also designed to provide independent power supply for each thyristor drive circuit. The experimental results show that this device has good voltage clamp capability, precise discharge voltage control and obvious unblocking effect, which lays the foundation for the downhole operation of the new oil and gas well production enhancement device. [ABSTRACT FROM AUTHOR]

Feature extraction and matching are the basic procedures of the so-called Visual Odometer (VO), Simultaneous Localization and Mapping (SLAM) and many other image processing algorithms. Oriented features from accelerated segment test (FAST) and rotated binary robust independent elementary features (ORB) algorithm are widely used since they are computationally faster. In this paper, we proposed a method to generate a value for a feature, the value is called signature. In the matching step, we only compute Hamming distances of descriptors with the same signatures. Hence, the matching time is shortened. Compared with the original ORB algorithm, features to be matched dropped 69.63% on TUM datasets and 85.7% on VGG datasets by adopting our strategy. In addition, the precision is above 85% on both VGG and TUM datasets. We design a customized hardware architecture for ORB feature extraction and matching based on the proposed method. The hardware structure is implemented on Xilinx ZCU102 evaluation board. The clock frequency is set to 150 MHz. Our Field Programmable Gate Arrays (FPGA) system achieves 193 fps on 1 2 8 0 × 7 2 0 images with 1984 features on average and 314 fps on 6 4 0 × 4 8 0 images with 700 features on average, which is more efficient compared to the state-of-the-art works. [ABSTRACT FROM AUTHOR]

Synchronization of the chaotic systems has attracted much attention in recent years due to its vital applications in secured communication systems. In this paper, an implementation and comparative analysis of two different control approaches for synchronization between two identical four-dimensional hyperchaotic systems is presented. The two control approaches are the Adaptive nonlinear controller and the linear optimal quadratic regulator LQR. To demonstrate the effectiveness of each controller, the numerical simulation is presented using Matlab/Simulink and the control law is derived. The performance of the proposed controllers is compared based on four factors; response time, squared error integration, energy applied from the controller, and cost function. To measure the robustness of the control approaches, the performance factors are compared when there is a change in system parameters and a variation in the initial conditions. Then the proposed synchronization methods are implemented on the FPGA platform to demonstrate the utilized resources on Field Programmable Gate Array (FPGA) hardware platform and the operation speed. Finally, to generalize the results of the comparison, the study is implemented for the synchronization of another secured communication system consisting of two identical three-dimensional chaotic. The experimental results show that the LQR method is more effective than the Adaptive controller based on the performance factors we propose. Moreover, the LQR is much simpler to implement on hardware and requires fewer resources on the FPGA. [ABSTRACT FROM AUTHOR]

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)-based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively. [ABSTRACT FROM AUTHOR]

A recently developed linear convolution filter based on Hirschman theory has shown its advantage in saving computations compared with other convolution filters. Here, the Hirschman convolution filter is improved with the use of the split‐radix algorithm and explore its latency‐reduced advantage for the first time. A comparison of hardware resources in Field Programmable Gate Array (FPGA) between the proposed Hirschman‐based filter and other convolution filters is presented. Simulation results indicate that the split‐radix Hirschman convolution filter achieves a promising reduction in latency by 18.15% on average with an acceptable power consumption rise by about 3.05%. In the case of a device capacity limited implementation, the proposed Hirschman convolution filter is still computationally attractive as it uses a small‐size originator function instead of larger Fourier transform. [ABSTRACT FROM AUTHOR]