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Ultrathin SiO2 layers are of importance for the semiconductor industry. One of the techniques that can be used to determine the chemical composition and thickness of this type of layers is x-ray photoelectron spectroscopy (XPS). As shown by Seah and Spencer [Surf. Interface Anal. 33, 640 (2002)], it is not trivial to characterize this type of layer by means of XPS in a reliable way. We have investigated a series of ultrathin layers of SiO2 on Si (in the range from 0.3 to 3 nm) using XPS. The samples were also analyzed by means of transmission electron microscopy (TEM), Rutherford backscattering (RBS), and ellipsometry. The thickness of the SiO2 layers (d) was determined from the XPS results using three different approaches: the "standard" equation (Seah and Spencer) for d, an overlayer-substrate model calculation, and the QUASES-Tougaard [Surf. Interface Anal. 26, 249 (1998), QUASES-Tougaard: Software package for Quantitative Analysis of Surfaces by Electron Spectroscopy, version 4.4 (2000); http://www.quases.com] method. Good agreement was obtained between the results of XPS analyses using the "standard" equation, the overlayer-substrate model calculation, and RBS results. The QUASES-Tougaard results were approximately 62% above the other XPS results. The optical values for the thickness were always slightly higher than the thickness according to XPS or RBS. Using the model calculation, these (relatively small) deviations from the optical results could be explained as being a consequence of surface contaminations with hydrocarbons. For a thickness above 2.5 nm, the TEM results were in good agreement with the results obtained from the other techniques (apart from QUASES-Tougaard). Below 2.5 nm, significant deviations were found between RBS, XPS, and optical data on the one hand and TEM results on the other hand; the deviations became larger as the thickness of the SiO2 decreased. This effect may be related to interface states of oxygen, which have been investigated [D. A. Muller, T. Sorsch, S. Moccio, F. H. Baumann, K. Evans-Lutterodt, and G. Timp, Nature (London) 399, 758 (1999); D. A. Muller and J. B. Neaton, Structure and Energetics of the Interface Between Si and Amorphous SiO2 in Fundamental Aspects of Silicon Oxidation, edited by Y. J. Chabal (Springer, Berlin, 2001), pp. 219-246.] by means of high-resolution electron energy loss spectroscopy measurements of the O K edge in ultrathin gate oxides of SiO2. (C) 2004 American Vacuum Society.

Depth profiling of ultra-thin SiO x N y gate dielectrics calls for a precise and reproducible SIMS measurement protocol and quantification scheme to give accurate N- and O-concentrations and film thickness. We apply 500 eV Ar + oblique-incidence primary ions to minimize transient effects and Si 2 M + /Si 2 + (M=N, O) secondary ion intensity ratios for concentration depth profiles. Determination of N- and O-concentrations at different compositions is established by linear interpolation between sensitivities, as measured in the pure materials (i.e. Si, SiO 2 , Si 3 N 4 ). Integral amounts of N and O thus obtained are in excellent agreement with high-resolution RBS. Apparently, sensitivities are surprisingly well constant (within a factor 2) over almost the full range of compositions. Crater depths below 10 nm are easily measured using optical profilometry, taking into account the different optical properties of transparent SiO x N y films and difference in erosion rates between Si, SiO 2 , Si 3 N 4 . The film thickness thus obtained is in good agreement with ellipsometry.

We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

This paper investigates the use of pulsed-RF decoupled plasma nitridation (DPN) for the growth of oxynitride gate dielectrics for 65 nm general purpose (GP) applications. The effects of several DPN plasma parameters, base oxide thickness and post-nitridation anneal (PNA) conditions on device performance were evaluated. Significant gate leakage reduction and improved trade-off between the equivalent-oxide-thickness (EOT) and mobility, for scaled EOT, have been found in devices with oxynitrides grown from thicker base oxides and optimized DPN/PNA processing conditions. DPN oxynitrides with 1.1-1.4 nm EOT have maximum operating voltages above 0.8 V, as extrapolated for a 10 year lifetime.

A CMOS process is developed in a research environment for integration studies of sub-50 nm MOSFETs with high-k (HiK) dielectrics, metal gates (MG), ultra-shallow junctions with laser thermal annealing (LTA), raised source/drain (RSD) and novel device architectures (e.g., double-gate transistors, strained channels). We have optimized the process parameters and show that high-performance transistors can be realized, promising direct applicability of the results to future manufacturing.

In this paper, in-line measurements of ultrathin gate dielectrics are reported. Various plasma nitrided oxides down to 1.5 nm EOT have been studied using in-line optical and non-contact electrical measurement techniques. The good correlation obtained with physical analysis and "classic" capacitance-voltage measurements shows the suitability of in-line measurement techniques for a first qualitative evaluation of ultrathin dielectric films.

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

The limits of scaling of planar Si MOSFET devices has been a subject of increasing interest in recent years. Consumer demand for high-performance electronic products has stimulated an ever-increasing rate of scaling of mainstream CMOS. Several results for devices with sub-50 nm gate lengths have already been reported (e.g. Timp et al., 1998; Chau et al., 2000; Wakabayashi et al., 2000) to approach the required performance values. We present here the results of study of manufacturability of sub-50 nm MOSFETs using tools routinely available for production of the 0.18 /spl mu/m CMOS generation. We show that by adapting 248 nm lithography, using nonequilibrium n-type junction formation and specially developed low-temperature processing, it is possible to manufacture devices with gate lengths as small as 15 nm. It is also confirmed that heavily pocketed devices with sub-50 nm gates show deterioration in performance.

This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.

This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the IOFF current of 20 pA/ µm and improve the ION-IOFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 µA/µ m( at IOFF =16 pA/µm) and 170 µA/µ m( at I OFF =16 pA/µm), respectively. The obtained results are among the best values reported in the literature.

In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (I on=450 µA/µm at I off=250 nA/µm for devices with L g\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.

In this paper a new physical gate leakage model is introduced, which is both accurate and simple. It only uses 5 parameters, making parameter extraction straightforward. As a result the model can be used to extract effective length for modern CMOS technologies. The influence of gate current on the RF performance is studied.

In order to understand how N2plasma conditions impact on the incorporation of nitrogen species into a thin SiO2(1.4 nm), tuning of some pulsed RF (pRF) Decoupled Plasma Nitridation (DPN) process parameters was performed: duty cycle (DC) or on-time per period, frequency (f), process time (t) and some cross-combinations (DC*f, DC*t, DC*f*t). The N2plasma and the SiOxNyfilm were characterized using Langmuir probe analysis (LP) and Delay to Reoxidation (D2R) techniques, respectively. Correlations are established between ion density and electron temperature and the resultant nitrogen concentration and parasitic physical thickness increase. The LP results indicate that while DC impacts the ion density and energy, the frequency has no impact to first order. This is consistent with the physical characteristics of the film. From the combination of DC*f*t, the importance of the off-time portion of the pulse was revealed. With the help of a modified pulsed RF DPN generator, allowing a decrease of the frequency down to 2 kHz, a 5% improvement of the drive current for pMOS transistors was obtained.