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The principle of ∆-modulation has been leveraged in time-domain to cancel the nonlinearity of voltage to frequency transfer function in VCO-based ADCs. The proposed modulation technique features frequency-tracking loop (FTL) to compensate for the imperfection of frequency nonlinearities and to eliminate the analog Op-Amp. Injection locking is used to alleviate the mismatch effect between the feedforward and feedback paths. The circuit level design and simulation results validate the functionality. The proposed solution can achieve higher noise shaping orders and better resolutions without compromising the hardware complexity by using fully synthesizable digital accumulators.

In a direct modulation scheme and particularly in portable and wireless sensor network applications, the oscillator limits the transmitter efficiency therefore, the oscillator efficiency is critical and high-efficiency and high-power oscillators are increasingly required. This paper presents a high-efficiency and ultra-low-voltage power oscillator that operates at 2.4 GHz and is implemented in 65 nm CMOS technology. The power oscillator is a self-oscillating class-E power amplifier (PA) that utilizes a positive feedback system. A class-E PA is selected due to its high efficiency. The power oscillator has an optimized power consumption and output power, where a 2.4 mW power consumption is achieved under a 0.4 V power supply. The proposed oscillator demonstrates a maximum output power of $$-0.45$$ dBm and a peak efficiency of 37.5%. The oscillator is tunable between 1.66 and 2.78 GHz. The oscillator is robust to a $$\pm\,15\%$$ frequency deviation from a 2.44 GHz nominal frequency due to process, voltage, temperature variation.

This paper presents an autonomous energy harvester able to perform a high radio frequency (RF) power tracking to achieve a DC renewable power source. The proposed simultaneous triple RF band energy harvesting system has the potential of being deployed along with remote sensor nodes to enhance their operational life-times. Two multi-stages rectifiers harvest the RF energy from three bands: 900 MHz, 1.2 and 2.4 GHz are proposed. A control loop is implemented to reconfigure the operating frequency of the rectifier based on the amount of available input power. The harvester is designed using TSMC 65-nm CMOS technology and tunable matching network to vary the input impedance of the main rectifier between 900 MHz and 1.2 GHz and the second rectifier harvests from 2.4 GHz. The results show a peak efficiency of 57, 43 and 33% at 2.4 GHz, 900 MHz and 1.2 GHz respectively.

Solar power harvesting is one of the most effective ways of providing clean energy. However, the power transfer is a major issue due to the shading effect. Besides; the photo voltaic (PV) output impedance is non-constant and it changes in a nonlinear fashion. This creates a challenge to ensure a maximum power transfer and hence, degrades the efficiency. A recent trend to regulate the efficiency has employed a boost DC- DC converter through adjusting its duty cycle. This paper presents an impedance matrix and analytical study on a single boost converter in continuous current mode (CCM) for low power harvesting application with its limitations to adapt PV’s impedance change. It establishes the relationship between efficiency and output voltage by analyzing the dynamics between load, duty cycle, constantly changing impedance of the PV’s cell and the impact of optimal duty cycle on the efficiency and output voltage as well. It further sheds some light into the over-sensitivity of efficiency with respect to duty cycle. To verify the analysis, an example simulation of 1.4V/17.1mW single boost converter for wearable electronics has been simulated and the result confirms the proposed model and analysis. Furthermore, the paper highlights the trade-off between the efficiency and its impact on the voltage regulation as well.

This paper presents the design and testing results of a complementary metal–oxide–semiconductor double-bulk harmonic-rejection (HR) mixer for wideband applications. An optimal gate-source bias voltage in the sub-threshold regime of the input transistor is found theoretically to achieve maxim HR by analysing the mixing mechanism of double-bulk mixer; and a double-bulk mixer has been designed and fabricated to verify the theoretical analysis. Test results substantiate the existence of the optimal bias point for HR of double-bulk-driven mixer when the sinusoidal local oscillator (LO) is applied. This simple but effective topology can achieve higher than 36, 44, 60 and 62 dB HR ratio for the third-, fifth-, seventh- and ninth-order of LOs, respectively, over broadband. The double-bulk mixer which input bandwidth is from 250 MHz to 3 GHz, including the buffer, consumes 5 mA current from 1 V power supply; the mixer core only consumes 1.5 mA current.

While floating-gate MOS transistor in mixed-signal applications have been studied in the literature, little has been reported on modeling them with gate leakage current (GLC). This paper presents a simulation model for floating-gate MOS transistor in nanometer-scale technologies. The proposed model accounts for direct tunnelling GLC in sub 3 nm gate oxide thickness. The model can be used for both transient and DC simulations with any industry standard simulators. HSPICE simulations and measurements of an experimental chip using TSMC 90 nm technology were presented.

The distortion analysis of nano-scale bulk-driven (BD) CMOS RF amplifier is presented based on Volterra series. The first three-order Volterra kernels are computed; and the closed-form expressions of the second-order and third-order harmonic distortion (HD) are derived. These expressions give good accuracy comparing with the simulation results, and can provide insight into the nonlinearity of nano-scale BD amplifier. These expressions unveil and demonstrate that the nano-scale BD MOSFET has distinct nonlinear characteristics. Also, distortion-aware design guidelines for nano-meter CMOS BD amplifier are provided. A modified second-order intermodulation $({\rm IM}_{2})$ injection technique is presented to suppress the third-order intermodulation $({\rm IM}_{3})$ product. This modified technique which consumes only 64 $\mu{\rm A}$ current employs phase adjustment of the low-frequency ${\rm IM}_{2}$ ; and up to 20 dB ${\rm IM}_{3}$ reduction is achieved over 1 MHz–20 MHz two-tone spacing range without gain reduction or noise penalty.

This work presents a high data rate, energy efficient quadrature phase shift keying (QPSK) transmitter suitable for biomedical applications. The transmitter includes a dual tuning mechanism to enable flexible phase/frequency control by direct modulation of a class-E oscillator while maintaining synchronization by using injection locking. The circuit is implemented in TSMC 65-nm CMOS technology with a core size 1 mm2. Using a 1.3-V supply, a transmit power of 14.1 dBm. For an injection frequency of 2.2 GHz, the circuit achieves a high throughput data rate equal to 69 Mbps.

A design technique for an asynchronous Analog-to-Digital Converter (ADC) is presented. The proposed design retains a clockless level crossing sampling technique, and then applies a Wavelet Neural Network (WNN) technique. High-level simulation results are shown for various ADC resolutions. The Signal to Noise and Distortion Ratio (SNDR) achieved for 4-bit ADC systems are presented. It has been shown that a 4-bit system with the proposed asynchronous ADC architecture using a WNN technique achieves an Effective Number Of Bits (ENOB) of up to 38 bits depending on the input frequency and resolution.

In this paper, the `mixing' mechanism of CMOS bulk-driven (BD) mixer is analyzed in detail. Based on the theoretical analysis, a novel method to improve harmonic mixing rejection (HMR) which is important for wideband mixer is proposed. Three BD mixers of different structures are designed in TSMC 65 nm technology to verify this design methodology. Simulation proves that HMR performance is improved for different mixer structures by following the methodology. The broadband HMR is robust under process, temperature, bias and local oscillator amplitude variation without sacrificing other performances. These proposed mixers offer conversion gain above 4.6, ?0.5 and 11.0 dB, respectively, covering frequency from 850 MHz to 6 GHz. The simulated IIP3 are 14.51, 16.82 and 4.96 dBm respectively. Power consumptions are 0.96, 1.2 and 0.33 mW respectively under 1 V power supply.

Stochastic ADC with uniformly distributed comparators trip point is presented. A basic comparator will have an offset that follows Gaussian distribution. When the comparator offset is used as the trip points for stochastic ADC, only 68 % of the comparators will be in the useful input range. By adding voltages that follow random U-quadratic distribution to the comparators' reference inputs, their trip points will shape into uniform distribution, and 80 % of them will lie within the useful input range. That will not only increase the resolution of stochastic ADC but also its input dynamic range.

This paper presents two low-voltage and low-power CMOS voltage controlled ring oscillators (VCOs) for use in portable wireless sensor applications. The frequency is controlled using an inversion mode MOS voltage controlled capacitor (varactor) to generate a large tuning range between 166 MHz to 600 MHz for the first design and from 250 MHz to 850 MHz for the second one and consume only 151.2 μW and 146.19 μW respectively. The proposed three-stage VCOs are designed and simulated in TSMC 65nm technology. Both operate on a 0.6 V power supply.

This paper presents an enhanced efficiency simultaneous dual band energy harvesting system for wireless body area network. A bulk biasing is used to enhance the efficiency of the adapted rectifier design to reduce Vth of MOSFET. The presented circuit harvests the radio frequency (RF) energy from two frequency bands: 1 GHz and 2.4 GHz. It is designed with TSMC 65-nm CMOS technology and high quality factor dual matching network to boost the input voltage. Full circuit analysis and modeling is demonstrated. The simulation results demonstrate a harvester with an efficiency of 23% at 1 GHz and 46% at 2.4 GHz at an input power as low as -30 dBm., {"references":["E. P. J. Tozer. Broadcast Engineer's Reference Book 2004.","Federal Communications Commission. ISM Band Communication Equipment Regulation, FCC 15.247 (https://www.fcc.gov/Bureaus/ Engineering_Technology/Documents/)","Jie-Huang Huang, Jin-Wei Wu, Yi-Lin Chiou and C. F. Jou. A 24/60GHz dual-band millimeter-wave on-chip monopole antenna fabricated with a 0.13-μm CMOS technology. Presented at Antenna Technology, 2009. iWAT 2009. IEEE International Workshop On. 2009, DOI: 10.1109/IWAT.2009.4906869.","Qi Luo, H. M. Salgado and J. R. Pereira. Compact printed monopole antenna array for dualband WLAN application. Presented at EUROCON - International Conference on Computer as a Tool (EUROCON), 2011 IEEE. 2011. DOI: 10.1109/EUROCON.2011.5929189.","XuLin Quan, RongLin Li, YueHui Cui and M. M. Tentzeris. Analysis and design of a compact dual-band directional antenna. Antennas and Wireless Propagation Letters, IEEE 11pp. 547-550. 2012. DOI: 10.1109/LAWP.2012.2199458.","F. Kanwal, H. Sultan, M. Maqsood, Q. ul Islam and S. Gao. Novel dual-band antenna with simultaneous linear and circular polarizations. Presented at Antennas and Propagation Conference (LAPC), 2014 Loughborough. 2014. DOI: 10.1109/LAPC.2014.6996436.","L. Bo, S. Xi, N. Shahshahan, N. Goldsman, T. Salter and G. M. Metze, \"An Antenna Co-Design Dual Band RF Energy Harvester,\" Circuits and Systems I: Regular Papers, IEEE Transactions, vol. 60, pp. 3256,3266, Dec. 2013.","Y. Uzun and E. Kurt. Design and simulation of a new dual-band RF energy harvester with high efficiency. Presented at Consumer Electronics (ISCE), 2015 IEEE International Symposium On. 2015. DOI: 10.1109/ISCE.2015.7177837.","P. Kamalinejad, K. Keikhosravy, R. Molavi, S. Mirabbasi and V. C. M. Leung. Efficiency enhancement techniques and a dual-band approach in RF rectifiers for wireless power harvesting. Presented at Circuits and Systems (ISCAS), 2014 IEEE International Symposium On. 2014. DOI: 10.1109/ISCAS.2014.6865568.\n[10]\tJ. F. Dickson, \"On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique,\" Solid-State Circuits, IEEE Journal of, vol. 11, 1976. \n[11]\tK. Koji, S. Atsushi and I. Takashi, \"High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs,\" Solid-State Circuits, IEEE Journal, vol. 44, pp. 3011-3018, Nov. 2009."]}

This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm2.

This letter presents a new efficient architecture for high-speed advanced encryption standard (AES) encryptor. This technique is implemented using composite field arithmetic byte substitution, where higher efficiency is achieved by merging and location rearrangement of different operations required in the steps of encryption. The proposed architecture is presented with multistage subpipelined architecture that allows having higher efficiency in terms of (throughput/area) than any previous field-programmable gate array (FPGA) implementations.

A distortion-compensated charge transfer amplifier (DCCTA) is proposed to improve the linearity constraints of the differential charge transfer amplifier (DCTA). The proposed DCCTA effectively reduces distortion at its output by source degeneration, cross coupling, and making the drain-to-source voltage of the amplifying transistor independent of the applied input signal. This DCCTA yields an effective number of bits of 9.26 bits, compared with 6.05 bits for the DCTA at 40 MHz while consuming only 13.5 μW from a 1.2-V source. A 1.66-MHz cyclic pipeline analog-to-digital converter employing this DCCTA as a residue amplifier was simulated using 90-nm CMOS process, resulting in a peak resolution of 9.21 bits, without being limited by the thermal noise.

A bandgap voltage reference with high-order curvature compensation is presented in this study. It exploits subtraction and derivative equalisation of currents generated from two complementary NMOS and PMOS bandgap references (BGRs) using subthreshold MOSFETs. By equating the derivative with respect to temperature of the two currents, generated by the complementary bandgaps, and subtracting these currents, an accurate high-order curvature compensation is achieved. To overcome problems due to the limited input common-mode range of opamps used in BGRs, a transimpedance amplifier with new accurate current compensation that tracks the temperature variation is proposed. This bandgap is implemented using the 0.18 μm CMOS process with a supply voltage as low as 0.7 V. At 0.8 V power supply and an output reference voltage of 386 mV, the proposed circuit achieves a temperature coefficient of 19 ppm/°C from 0 to 130°C. The power consumption is 119 μW and the power supply reduction ratio is 24 dB at 1 kHz.

This brief presents an adaptive excess loop delay (ELD) compensation technique for continuous-time delta-sigma modulators. This technique utilizes a predictive comparator with adaptive control using the sign least-mean-square algorithm to estimate the compensation coefficients. Contrary to other state-of-the-art compensation methods, the proposed technique is immune to manipulation of the loop filter transfer function and loop circuitry. Consequently, it will not deteriorate the performance of the modulators. Simulations performed on two different delta-sigma modulators show the effectiveness of the proposed technique to compensate the ELD in low-pass and bandpass delta-sigma modulators.

The operational transconductance amplifier (OTA) is one of the most significant building-blocks in integrated continuous-time filters. Traditional OTAs suffer linearity reduction as a result of the MOSFET scaling trend. In this paper, a body-driven (BD) CMOS triode-based fully balanced OTA is proposed to achieve low distortion and linear frequency tuning. In contrast to the gate-driven based OTAs (that have the tradeoff of input and tuning range), BD-based OTAs operate under a wide input range over a large tuning interval. Common-mode (CM) feedforward and CM feedback schemes have been developed so that the CM voltage varies only 7 mV over a tuning range of 1.2 V = Vtune = 1.58 V. Using the 0.18-mum N-well CMOS process, a third-order elliptic low-pass filter is implemented with the aid of the proposed OTA. The total harmonic distortion ( is -45 dB for 0.8-V peak-peak (Vpp) fully differential input signals. A dynamic range of 45 dB is obtained with the OTA's noise integrated over 1 MHz.

As the Silicon oxide scaled down in MOSFET technology to few nanometers, gate Direct Tunneling (DT) in Floating gate (FGMOSFET) devices has become a major concern for analog designers. FGMOSFET has been used in many low-voltage and low-power applications, however, there is no accurate model that account for DT gate leakage in nano-scale. This paper studied and analyzed different simulation models for FGMOSFET using TSMC 90-nm technology. The simulation results for FGMOSFET cascade current mirror shows the impact of DT on circuit performance in terms of current and voltage without the need for fabrication. This works shows the significance of using an accurate model for FGMOSFET in nan-scale technologies., {"references":["J. Ramirez-Angulo, S. C. Choi and G. Gonzalez-Altamirano. Lowvoltage\ncircuits building blocks using multiple-input floating-gate\ntransistors. Circuits and Systems I: Fundamental Theory and\nApplications, IEEE Transactions on 42(11), pp. 971-974. 1995.","S. Sharma, S. S. Rajput, L. K. Magotra and S. S. Jamuar. FGMOS based\nwide range low voltage current mirror and its applications. Presented at\nCircuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific\nConference On. 2002,. DOI: 10.1109/APCCAS.2002.1115251.","D. I. R. Chavez, J. de la Cruz Alejo and J. C. S. Garcia. Design of S?\nModulators using FGMOS transistors. Presented at Electrical\nEngineering Computing Science and Automatic Control (CCE), 2011\n8th International Conference On. 2011, DOI:\n10.1109/ICEEE.2011.6106599.","J. Ramirez-Angulo, G. Gonzalez-Altamirano and S. C. Choi. Modeling\nmultiple-input floating-gate transistors for analog signal processing.\nPresented at Circuits and Systems, 1997. ISCAS '97. Proceedings of\n1997 IEEE International Symposium On. 1997.","Liming Yin, S. H. K. Embabi and E. Sanchez-Sinencio. A floating-gate\nMOSFET D/A converter. Presented at Circuits and Systems, 1997.\nISCAS '97. Proceedings of 1997 IEEE International Symposium On.\n1997.","Ai Chen Low and P. Hasler. Cadence-based simulation of floating-gate\ncircuits using the EKV model. Presented at Circuits and Systems, 1999.\n42nd Midwest Symposium On. 1999, DOI:\n10.1109/MWSCAS.1999.867228.","Dongwoo Lee, W. Kwong, D. Blaauw and D. Sylvester. Simultaneous\nsubthreshold and gate-oxide tunneling leakage current analysis in\nnanometer CMOS design. Presented at Quality Electronic Design, 2003.\nProceedings. Fourth International Symposium On. 2003. DOI:\n10.1109/ISQED.2003.1194747.","C. Choi, Kwang-Hoon Oh, Jung-Suk Goo, Zhiping Yu and R. W.\nDutton. Direct tunneling current model for circuit simulation. Presented at Electron Devices Meeting, 1999. IEDM '99. Technical Digest.\nInternational. 1999. DOI: 10.1109/IEDM.1999.824256.","C. Choi, Ki-Young Nam, Zhiping Yu and R. W. Dutton. Impact of gate\ndirect tunneling current on circuit performance: A simulation study.\nElectron Devices, IEEE Transactions On 48(12), pp. 2823-2829. 2001. .\nDOI: 10.1109/16.974710.\n[10] Z. Saheb and E. El-Masry, \"Modelling of direct tunneling gate leakage\ncurrent of floating-gate CMOS transistor in sub 100 nm technologies,\"\nAnalog Integrated Circuits and Signal Processing, 2015."]}

This paper presents a complete structure and model of a microelectromechanical-system variable capacitor that is able to achieve a theoretically infinite tuning range. For the first time, both stress and residual stress issues are treated simultaneously. Two capacitors were fabricated where actuation voltages of 4.5 and 9 V (that correspond to a tuning range of 3:1 and 3.4:1, respectively) were acquired. Simulation and measurements verify that the proposed variable capacitors possess higher performance and tuning ranges when compared with the same class varactors fabricated using the same process. Further, a finite-element model based on electrostatic-structural coupling is presented.

A CMOS current mirror (CM) based on the body-driven technique and active feedback scheme is presented. The proposed CM is immune to the threshold voltage limitation and offers much higher accuracy over wider current operating range than other body-driven CMs. The complete analysis of the input-output characteristics, system dc current transfer error, frequency, and noise performance is provided. By using a 1.5V/1V single power supply and 0.18-/spl mu/m n-well process, SPECTRE simulation results validate the analytical results and the overall good performance in terms of wider input-output voltage swing, lower input resistance, and larger output resistance compared with the conventional high-swing cascode CM.

The distortion analysis of nano-scale (65nm) CMOS RF amplifier is presented based on Volterra series. The first three-order Volterra kernels are computed; and compact closed-form expressions of the second-order and third-order harmonic distortion (HD) are derived. These expressions give good accuracy comparing with the simulation results, and can provide insight of the nonlinearity of nano-scale amplifier. These expressions unveil and demonstrate that the nano-scale MOSFET has distinct nonlinear characteristics. Also, distortion-aware design guidelines for nano-meter CMOS amplifier are provided throughout the paper.

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-μm mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm^2 without the i/o pads

A new fully differential class-AB log-domain integrator is proposed. The structure consists of two non-inverting integrators and an intersection circuit with a common-feedback circuit. The effects of transistor non-idealities and signal path mismatches on the differential integrator are investigated. A 5th-order Chebyshev low-pass filter which can be tuned from 1 to 45 MHz is designed. The validity and stability of the proposed circuits are verified using HSPICE simulations.

A design method of current-mode (CM) band-pass ladder filters is presented. The proposed method is based on the simulation of the passive RLC ladder networks using current-mode biquad blocks. Three scaled impedance functions are chosen to generate the biquadratic transfer functions. Based on these scaled impedance functions, three CM band-pass filters are obtained and implemented using OTAs. As an example, a sixth-order Chebyshev band-pass filter is designed and simulated using HSPICE.

A synthesis approach for a nth-order log-domain filter is proposed. Using the logexponential relation between current and voltage of a bipolar junction transistor (BJT) or MOS transistors operating in weak inversion, a circuit transformation from log-domain to linear OTA-C filters is developed. Based on the simulation of a signal-flow-graph on the nth-order transfer function, the realization of the highorder log-domain filter is presented. A 4th-order low-pass filter is designed and simulated in HSPICE.

A new design approach for current-mode (CM) filters is presented. The proposed method is based on simulating RLC ladder networks using coupled-biquad structures. The loop-and branch-currents are used as variables to generate transfer functions. These functions are realized by CM circuits implementing multiple output CMOS OTA's. The resulting CM structures use only grounded capacitors making them suitable for VLSI. To demonstrate the proposed approach, a low-pass and a band-pass ladder filter were designed and simulated using HSPICE.

The use of a current-mode pulse width modulation (CM-PWM) technique to implement analog artificial neural networks (ANNs) is presented. This technique can be used to efficiently implement the weighted summation operation (WSO) that are required in the realization of a general ANN. The sigmoidal transformation is inherently performed by the nonlinear transconductance amplifier, which is a key component in the current integrator used in the realization of WSO. The CM-PWM implementation results in a minimum silicon area, and therefore is suitable for very large scale neural systems. Other pronounced features of the CM-PWM implementation are its easy programmability, electronically adjustable gains of neurons, and modular structures. In this paper, all the current-mode CMOS circuits (building blocks) required for the realization of CM-PWM ANNs are presented and simulated. Four modules for modular design of ANNs are introduced. Also, it is shown that the CM-PWM technique is an efficient method for implementing discrete-time cellular neural networks (DT-CNNs). Two application examples are given: a winner-take-all circuit and a connected component detector.

In this paper, we present the design of a CMOS current operational amplifier (COA). A design technique based on current steering is proposed to enhance the frequency capability of the amplifier and achieve higher bandwidth of operation. A complete COA was designed and fabricated using a 1.2-/spl mu/m CMOS technology, the COA occupies an area of 0.13 mm/sup 2/. Results from HSPICE simulations and measurements indicate an open-loop gain of 70 dB, a gain-bandwidth product exceeding 200 MHz, and a settling time of 5.1 ns. The amplifier operated under /spl plusmn/3 V DC voltage supplies, and the power dissipation is approximately 4.5 mW.

This paper presents a novel high efficiency RF to DC converter for RFID applications. The proposed rectifier circuit is designed in 90 nm CMOS technology using single RF source. It exploits an internal Vth cancellation technique along with a leakage current reducer. The circuit performs well in the low input power threshold. The Simulation results at frequency of 920MHz show that the Power Conversion Efficiency (PCE) has improved compared to the conventional rectifier using diode connected transistor and Vth cancellation techniques. The measured PCE is 36.3% at -14.3dBm and is improved to 54.5% with an impedance matching network between the source and rectifiers' input.

The double sampling technique can be used to achieve twice the sampling frequency in a sampled-data system without extra requirements for op-amp's settling time, dc gain, etc. In this paper, theoretical analysis of path gain mismatch on the performance of double sampling delta-sigma modulators (/spl Delta//spl Sigma/M's) is given. Based on the result, a novel double sampling technique for /spl Delta//spl Sigma/M's that is insensitive to the path gain mismatch is presented. This technique uses a bilinear double sampling integrator in the first stage, achieving a first order shaping of the path gain mismatch error. Simulation results have been provided to verify the proposed technique.

This paper introduces a Switched-current Analysis Program (SIAP) that can perform both transient and frequency domain analysis of switched-current (SI) circuits. The program uses sparse matrices to reduce storage requirements and computation time. Transient analysis is performed using the large signal MOSFET model and the frequency domain analysis uses the small signal MOSFET model that includes all parasitic capacitance. All devices are modeled in a manner comparable with HSPICE and include almost all nonidealities, such as nonideal switches, clock feedthrough, channel-length modulation and transistor parasitic capacitors. Multiple inputs are allowed in both the transient and frequency domain analysis, thus differential circuits can be easily analyzed.

A novel continuous-time current-mode differentiator with a frequency range extending from DC to 100 MHz is presented. This circuit is constructed using a capacitively coupled current mirror. General first- and second-order circuits, using the differentiator, have also been introduced. To demonstrate how the proposed differentiator can be used to construct higher order filters, a sixth-order band-pass filter with a center frequency at 2.5 MHz and a 1 dB pass-band ripple has been realized and simulated. All simulations were performed using HSPICE for a 1.2 /spl mu/m CMOS process. The total power dissipation for the sixth-order filter is 23 mW from a single 3 V supply.

In this paper, a high-output impedance, wide output swing bulk-driven current source with dynamic biasing is proposed. To increase the output impedance, a bulk-driven gain-boosted cascode feedback amplifier is used. Two dynamic biasing circuits are introduced: one is used to adaptively bias the gate of the current source output transistor while the other is used to supplement current into the output node when the output voltage is low. In addition, the dynamic biasing circuits help to boost the output impedance further. Simulation results show that under 0.6 V supply voltage, the minimum output voltage is below 100 mV and the output impedance is over 200 MΩ.

A wide-band, fast settling CMOS complementary folded cascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder cascode (FC) or mirrored cascode (MC) approaches for VLSI amplifiers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm/sup 2/), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a DC gain of approximately 50 dB, with a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF. >

This paper presents an 0.8-V power supply multi-pass loop ring oscillator. The oscillator employs cross-coupled PMOS transistors to improve phase noise characteristic and multi-pass loop to obtain wide frequency tuning range. The coarse and fine controlled signals are also applied to lower the noise sensitivity of the oscillator. Simulations using TSMC 90 nm CMOS technology shows 394MHz to 4.4GHz frequency tuning range and −94.6dBc/Hz at 1MHz offset from 4.4GHz. The power consumption is 11.2mW.

A CMOS active inductor with thermal noise cancelling is proposed. The noise of the transistor in the feed-forward stage of the proposed architecture is cancelled by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. Simulation results using 90 nm CMOS process show that noise reduction by 80% has been achieved. The maximum resonant frequency and the quality factor obtained are 3.8 GHz and 405, respectively. An RF band-pass filter has been designed based on the proposed noise cancelling active inductor. Tuned at 3.46 GHz, the filter features total power consumption of 1.4 mW, low noise figure of 5 dB, and IIP3 of −10.29 dBm.

A method for the analysis of distributed MOSFET filters is presented. The effects of parasitic capacitances on distributed high-pass MOSFET filters are investigated. Three schemes of MOSFET configurations functioning as distributed high-pass filters are presented and analyzed to demonstrate the method and to illustrate the parasitic effects. The analyses are verified by SPICE simulation and the very high frequency numerical model of a MOSFET given by L.J. Pu and Y. Tsividis (1990). >

This paper presents charge sampling circuit using new high linearity transconductor (Gm) cell that has third order distortion cancellation. The proposed Gm-cell has almost constant transconductance value over ±200mV input voltage range. The charge sampling circuit has SNDR around 73 dB with ENOB of 11bits and it consumes 4.38mW power. Its input referred noise is 15.29nV/√Hz and noise figure is 24.67dB at 81MHz. This architecture is used to implement a programmable analog baseband filter for Bluetooth and UMTS. Simulations were carried out using the TSMC 0.18 µm CMOS technology with supply voltage of 1.6V.

This paper presents a new category of MEMS variable capacitance devices which can provide a specific tuning range tailored to the specific application being considered. Depending on the tuning range chosen, this device can play the role of a variable capacitor, a switched capacitor, or a switch. The proposed structure can provide theoretical tuning ranges anywhere from 4.9 to 35 with a simple, yet effective, layout modification as opposed to previously reported devices where the tuning range is fixed and cannot be varied. Three variations of the variable capacitance device were fabricated as proof-of-concept prototypes in the PolyMUMPS process to verify the theoretical analysis, and measurement results showed tuning ranges of 3, 3.4, and 4.4 respectively, confirming our theoretical analysis.

A bandgap reference with curvature corrected compensation which utilizes the subtraction of currents generated from complementary NMOS and PMOS bandgaps using MOS transistors in subthreshold is presented. A transimpedance amplifier with accurate input current compensation is used to overcome the problems due to input common range limitations of operational amplifiers. The bandgap reference uses power supply of 0.8V, the accuracy is 19ppm/K for 386mV in the temperature range of 0 to 130C. The PSRR is 24dB for 1kHz and 23dB for 10kHz.

A novel analog realization of a self-organizing neural network using switched-capacitors is presented. The design is entirely synchronous and incorporates a 'winner-take-all' circuit, as well as a circuit capable of computing the neural activity required by the dot product operation. A switched-capacitor circuit capable of implementing the basic learning law in self-organizing neural networks is also presented. The entire system, which avoids the cumbersome use of polysilicon resistors in VLSI technology, can easily form the backbone of a neurocomputer devoted to competitive learning systems. Also, the binary nature of the input pattern vectors lends itself to application areas such as pattern recognition and image processing. Design equations are presented and confirmed using HSPICE simulations. Experimental results of a breadboard version of the 'winner-take-all' circuit are also presented and verified, and a chip has been submitted for fabrication. >

A bidirectional associative memory using switched-capacitor (SC) filter techniques (SCBAM) is introduced and verified experimentally. The discrete-time equation that characterizes SC filter design is shown to be applicable in recalling m stored vector pairs that can be encoded in a correlation matrix M. The elements of M (and M/sup T/) are represented by the values of the capacitor ratios used in the SCBAM. The SCBAM exhibits similar error correcting properties as the normal BAM, making it a good candidate for analog VLSI neural network implementations. >

This paper presents some important design considerations usually ignored that need to be taken into account when designing MEMS parallel plate variable capacitors. Explicitly, it introduces an accurate method that incorporates parasitic and fringing capacitances in calculating the tuning range. Secondly, it shows, by the finite element method, that the etching hole effects for two-plate and three- plate varactors on the capacitance are low and can be ignored in the initial design stages. Finally a novel closed form expression, which calculates the capacitance of a varactor with a warped top suspended plate due to residual stress, is introduced; the expression is based on a second order model.

A current mirror circuit that uses body-driven MOSFETs to achieve an ultra-low input and output voltage is presented. High-gain amplifiers, suitable for a deep submicron process, are used to provide matching as well as input and output regulation. Simulation results were verified with measurements performed on a fabricated chip using the 90-nm CMOS process from ST-Microelectronics.