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A 60-GHz polar vector modulator with a lookup table (LUT)-based calibration for a variable gain active phase shifter is presented. It consists of an input buffer, an I/Q generator, a vector summing amplifier, and 6-bit phase/gain digital-to-analog converters (DACs). It is very difficult to obtain accurate gain and phase characteristics of a polar vector modulator due to circuit imperfections, such as I/Q imbalance, current mismatches of DACs, and impedance variations over polar vector states. Thus, calibrations are essential to have accurate gain and phase states. This letter introduces an LUT-based calibration method to map possible 213 states (5-bit gain and 8-bit phase) onto targeted polar states, which minimizes gain and phase errors drastically. The proposed phase shifter with a generated LUT shows an rms gain and phase errors of 0.13 dB and 0.8°, respectively, at the center frequency of 60 GHz. In addition, it has an rms gain and phase errors of

A new adaptive frequency search algorithm (A-FSA) is presented for a fast automatic frequency calibrator in wideband phase-locked loops (PLLs). The proposed A-FSA optimizes the number of clock counts for each frequency comparison cycle, depending on the difference between the target frequency and the PLL output frequency, as opposed to a binary frequency search algorithm (B-FSA), where the frequency search time per cycle is fixed. This eliminates unnecessary clocking times during the frequency comparison process, and thus reduces the total PLL lock time. The additional circuitry needed for A-FSA is only a simple counter controller, thus minimizing hardware overhead. To verify the effectiveness of the proposed algorithm, two wideband PLLs are designed and simulated using a 65-nm CMOS technology: one with B-FSA, and the other with A-FSA. The latter achieves a lock time faster than the former by at least a factor of 2, even under worst case conditions.

This paper proposes a new series-coupled voltage-controlled oscillator (VCO). The proposed VCO consists of four current-reuse Armstrong VCOs (CRA-VCOs) coupled by four transformers. The series-coupling, current-reuse, and Armstrong topologies improve the phase noise performance by increasing the negative-Gm of the VCO core with half the current consumption of a conventional differential VCO. The proposed VCO consumes 6.54 mW at 9.78 GHz from a 1-V supply voltage. The measured phase noise is −115.1 dBc/Hz at an offset frequency of 1 MHz, and the FoM is −186.5 dBc/Hz. The frequency tuning range is from 9.38–10.52 GHz. The core area is 0.49 mm 2 in a 0.13-μm CMOS process.

A dynamic feedback linearizer for an RF CMOS power amplifier (PA) is presented, which consists of a negative feedback network and a dynamic feedback control circuit to inject a reshaped envelope signal to the network. The linearizer compensates for the gain compression of the RF CMOS PA in high-power region by reducing the feedback dynamically, and it also reduces the amplitude-to-phase modulation (AM-PM) distortions. The PA including the linearizer was fabricated using a 0.18- $\mu \text{m}$ RF CMOS process, which has an output transmission-line transformer on a printed circuit board. It delivers an output power of 28.1 dBm at 1.7 GHz with power added efficiency of 40.9%, and adjacent channel leakage ratio (ACLR $_{\mathrm {E-UTRA}}$ ) of under −30 dBc for a 10-MHz 16-QAM long-term evolution signal without digital predistortions.

A wideband W-band 6-bit vector-sum based active phase shifter which was implemented using a 28-nm RF CMOS process is presented. The proposed phase shifter consists of a differential I/Q generator and a vector-summing amplifier with differential input and output buffers to use virtual grounds at high frequencies. The I/Q generator was designed with a differential hybrid coupler structure, and the mismatch in its differential input should be small to obtain accurate I/Q signals. To reduce the differential mismatch at the I/Q generator input, source cross-coupling capacitors are introduced at the common-gate stage of the cascode input buffer. The measured results indicate a root mean square (RMS) gain error of 0.69-0.98 dB and RMS phase error of 6.8-9.3 degrees over a wide frequency range of 76 GHz to 104 GHz. The average peak gain of all 64 states is 3.5 dB at 82 GHz. The fabricated phase shifter has a chip area of 0.32 mm2 with power consumption of 26 mW.

This paper presents a fractional-N phase-locked loop based spread spectrum clock generator (SSCG) using a programmable linear frequency modulator. The SSCG provides a programmable frequency deviation and modulation frequency regardless of its operating frequency. The ranges of frequency-deviation ratio and modulation frequency are 0–80% and 0–100 kHz with 610 Hz step resolution. The proposed SSCG successfully support five serial-link standards by using a single SSCG, and can be applied to various switching circuits such as class-D power amplifiers or switching power converters. The EMI reduction was measured to be 10.24–13.94 dB under 100-kHz resolution bandwidth. The proposed SSCG was fabricated using a 0.13-μm CMOS process with an active area of 0.11 mm2, while consuming an overall power of 6.28 mW at 1 GHz.

In this letter, we present a new linearization method for a voltage controlled oscillator (VCO)-based quantizer in an analog-to-digital converter (ADC). The nonlinearity of the VCO generates unwanted harmonic spurs and reduces the signal-to-noise and distortion ratio (SNDR) of the VCO-based quantizer. This letter suggests a frequency-to-current feedback method to effectively suppress harmonic distortion. The proposed method decreases the harmonic spurs by more than 53 dB. And a VCO-based quantizer employing the proposed linearization method achieves a high SNDR of 74.1 dB.

A novel low-power injection-locked frequency divider (ILFD) is proposed, in which a complementary G m -boosted Colpitts oscillator core is employed to improve negative transconductance ( G m ) and the current-reuse technique using a single transformer is applied to reduce the power consumption. The proposed ILFD exhibits a self-resonant frequency of 4.93 GHz with a maximum locking range of 870 MHz at 0 dBm of input power. The phase noises of the input and output signals are -128.54 and -134.53 dBc/Hz, respectively. The ILFD consumes 1.37 and 2.5 mW at 1.15 and 1.3 V, respectively. The chip area is 715.5 × 468 μm 2 in a 0.13 μm CMOS process. To the authors' knowledge, this is the first demonstration of the current-reuse ILFD.