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Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

This paper presents a collection of test data showing how the choice of package design and material can have a different effect on performance depending on the loading conditions. Board level temperature cycling, drop (JESD22-B111), and cyclic bend (JESD22-B113) tests were performed on 0.4 mm ball pitch packages. Factors investigated for this evaluation include mold compound material, mold cap thickness (0.45 vs. 0.7 mm), ball pad finish (NiAu vs. Cu OSP), solder ball composition (SAC305, SAC105, SAC125M, Sn3.5Ag), solder volume (ball vs. bump), package material (RoHS vs Green), and board material (RoHS vs Green). The data presented in this paper indicates that lower silver content solder balls perform better under drop conditions, while temperature cycling reliability suffers as silver content decreases. In addition, mold compound material and thickness, die size, and solder volume have the opposite effect depending on the loading condition. The Green material for test board also showed lower performance than RoHS compliant board material.

The molded underfill (MUF) process has a lot of advantages compared with capillary underfill process in view of reduction of process, cycle time of process, material and equipment cost since this application utilizes the conventional mold materials and equipment systems. But the extremely narrow gap at the underfill area for flip-chip bonding make it difficult to get stable MUF material set and appropriate processing conditions because of the severe void trapping problem. In this paper, the MUF process of flip-chip package on package (POP) is investigated. The rheological and cure- kinetic parameters of commercial MUF compound are acquired using parallel plate rheometer and dynamic DSC (differential scanning calorimeter) analysis. The experimental results showed severe void at the underfill area for both top- left and bottom-right pin type gate locations. The modeling results by full 3D mold filling simulation show good agreement with the actual void occurring area investigated by the SAT pictures. Applying the benchmarked constitutive relations and finite elements model, seven kinds of different gate types and locations are tried, but the void trapping is not completely removed. To resolve void trapping phenomena of current flip-chip structure, we devised a proprietary mold design. From the modeling results, the void trapping zone under the large die are effectively removed through the optimized design. From this study, we can conclude that the optimized mold design will be very effective on the elimination of void in the underfill area for flip-chip MUF processing.

In spite of a great success of stacked package (PoP) in the market, some reliability issues about package on package (PoP) have been raised by several customers. To guarantee a high reliability in board level performances, many process and material developments are attempted. In the material developments, low silver contented solder alloys are adopted for higher board level drop performances. In OSP substrate pad finish, Sn/1.2Ag/0.5Cu/0.05Ni solder is applied and in Ni/Au substrate pad finish, Sn/1.0Ag/0.5Cu solder is adopted for higher reliabilities. 2nd level underfill is also adopted for higher drop performances but in this case, board level temperature cycle performance is deteriorated. To accomplish of higher board level performances both in temperature cycle and drop test, higher Tg & low CTE underfill materials are developed In the process developments, stacking materials and processes are developed. Board level reliabilities of pre- stacking & SMT stacking process is evaluated and paste and flux materials for top package stacking process are also evaluated. This paper discusses about board level reliabilities in temperature cycle and drop tests with various material and process combinations - especially, solder alloys, substrate pad finish, 2nd level underfill, stacking method and stacking materials.

In spite of a great success of stacked package (PoP) in the market, some reliability issues have been raised. One of them is a board level reliability evaluation of PoP with 2nd level underfill. Some customers have issued the application of 2nd level underfill for PoP to improve the reliability for drop test. Unfortunately, using the 2nd level underfill for PoP package causes reducing the reliability for thermal cycling test. Under temperature cycling test, PoP with 2nd level underfill shows early failures before 300 cycles whereas most of samples without 2nd level underfill survived over 1000 cycles. This paper discusses the optimal underfill material for PoP to achieve reliable board level performances. Various factors such as filler content, CTE, Tg and underfill dispensing pattern are considered. As a result, it is found that lower CTE & higher Tg underfill are better than other factors for temperature cycle performance. Non filler type underfill was passed 500 cycles for PoP but filler type underfill was passed 2500 cycles under the JEDEC JESD22-104C Condition G (-40'C~125'C, 1 cycle/hour). Especially one of non filler type underfill material with different dispensing pattern passed 1730 cycles without any failure. We assumed that this results caused by specific dispensing patterns & damping effect of non filler type underfill. In the drop test, most of underfill materials have better performances than no underfill case. Especially, several no filler type underfills have no failure until 400 drops.

Recent data [Syed, A., et al., "Alloying Effect of Ni, Co, and Sb in SAC solder for Improved Drop Performance of Chip Scale Packages with Cu OSP Pad Finish," Proceedings of the 8th EPTC conference, 2006, pp. 404-411.] shows that significant improvement in drop performance can be achieved by utilizing solder balls of Sn1.2Ag0.5Cu0.05Ni composition on Cu OSP finish packages. Along with higher performance, the data also shows that the failure mode changes from brittle (IMC) to ductile (bulk solder) when this alloy is used as opposed to SAC305/SAC405 solder alloy. This implies that quantification of plastic deformation of solder joint due to drop/impact loading can be used in predicting the life of solder joints when this alloy is used for solder balls. This paper reports the correlation of accumulated plastic strain and plastic work (energy density) to the number of drops to failure. Board level drop tests were performed on two component types with varying component sizes, ball sizes, and ball pitch using Cu OSP finish and solder balls Sn1.2Ag0.5Cu0.05Ni composition. The drop to failure data was collected on these components at various locations on the board to generate enough spread in the data. Each of this data set was then simulated using the approach published previously [Syed, A., et al., "A Methodology for Drop Performance Prediction and Application for Design Optimization of Chip Scale Packages," Proceedings of 55th ECTC conference, 2005, pp. 472-479.] employing high strain rate stress-strain behavior of this solder alloy. The accumulated plastic strain and plastic work in the critical solder joint was computed for each component and at various locations on the board to determine the correlation with number of drops to failure. The simulation approach and the correlations achieved can be used not only to predict solder joint response in a board level test but also for a product level drop test. Also, the same methodology can be used for life prediction of solder joints using other solder alloys, as long as failure is in the bulk solder.

This paper discusses the optimal design for PS-etCSP to achieve reliable thermal fatigue life of solder joint. For this purpose design analysis was performed using both simulation and experimental approaches. Since reduction of warpage is most critical issue to ensure good solder joint connection for thin packages, parametric study was performed to find the optimal set of package outline dimensions using finite element method. Next to find the optimal design far solder joint reliability, 3D FEA fatigue model was established with non linear material properties of solder joint. Various factors such as ball land size, motherboard thickness and surface mounting type were studied. As a result, it is found that thin die with small size and small CTE molding compound is better for minimizing package warpage and larger opening size, thinner board and single mounting on board are good for solder joint reliability. The stack of package however has little effect on solder joint reliability. The effects of board thickness and surface mounting type (single/double) were investigated in terms of assembly stiffness and solder joint reliability. Simulation results showed good correspondence with experiment. The fatigue life and failure location predicted by simulation agreed well with experimental data. The fatigue life of optimal design was 1225 cycles for single PS-etCSP and 990 cycles for stacked PS-etCSP with single side mounting on board under the thermal cycling loading of temperature of -40/spl deg/C/spl sim/125/spl deg/C. Subsequently it can be concluded that optimal design of PS-etCSP can meet the requirement for most portable product applications.