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The slowdown of the CMOS technology scaling, and the trade-off between efficiency and flexibility have fueled the exploration into novel architectures with emerging post-CMOS technology [e.g., resistive-RAM (RRAM)]. In this article, a nonvolatile fully programmable processing-in-memory (PIM) processor named Liquid Silicon is demonstrated, which combines the superior programmability of general-purpose computing devices [e.g., field-programmable gate array (FPGA)] and the high efficiency of domain-specific accelerators. Besides the general computing applications, Liquid Silicon is particularly well suited for artificial intelligence (AI)/machine learning and big data applications, which not only poses high computational/memory demand but also evolves rapidly. To fabricate the Liquid Silicon chip, the HfO2 RRAM is monolithically integrated on top of the commercial 130 nm CMOS. Our measurement confirms that Liquid Silicon chip can operate reliably at a low voltage of 650 mV. It achieves 60.9 TOPS/W in performing neural network (NN) inferences, and 480 GOPS/W in performing content-based similarity search (a key big data application) at a nominal voltage supply of 1.2 V, showing $3\times $ and $100\times $ improvement over the state-of-the-art domain-specific CMOS-/RRAM-based accelerators. In addition, it outperforms the latest nonvolatile FPGA in energy efficiency by $3\times $ in general computing applications.

The implementation of current deep learning training algorithms is power-hungry, due to data transfer between memory and logic units. Oxide-based resistive random access memories (RRAMs) are outstanding candidates to implement in-memory computing, which is less power-intensive. Their weak RESET regime is particularly attractive for learning, as it allows tuning the resistance of the devices with remarkable endurance. However, the resistive change behavior in this regime suffers from many fluctuations and is particularly challenging to model, especially in a way compatible with tools used for simulating deep learning. In this work, we present a model of the weak RESET process in hafnium oxide RRAM and integrate this model within the PyTorch deep learning framework. Validated on experiments on a hybrid CMOS/RRAM technology, our model reproduces both the noisy progressive behavior and the device-to-device (D2D) variability. We use this tool to train binarized neural networks (BNNs) for the MNIST handwritten digit recognition task and the CIFAR-10 object classification task. We simulate our model with and without various aspects of device imperfections to understand their impact on the training process and identify that the D2D variability is the most detrimental aspect. The framework can be used in the same manner for other types of memories to identify the device imperfections that cause the most degradation, which can, in turn, be used to optimize the devices to reduce the impact of these imperfections.

Resistive random access memories (RRAMs) feature high-speed operations, low-power consumption, and nonvolatile retention, thus serving as a promising candidate for future memory applications. To explore the applications of the RRAM, switching variability and cycling endurance need to be addressed. This paper presents extensive characterizations of multi-kb RRAM arrays during forming, set, reset, and cycling operations. The relationships among programming conditions, memory window, and endurance features are presented. The experimental results are then used to perform variability-aware simulations of a 128-bit RRAM-based ternary content-addressable-memory (TCAM) macro. The tradeoff among endurance, search latency, and reliability in terms of match/mismatch detection is explored, identifying the programming conditions that allow to obtain a searching speed comparable to static random access memory-based TCAMs (2 ns on average and 3 ns at $3\sigma $ ) while guaranteeing good reliability metrics (with a time ratio of 3000 on average and 150 at $3\sigma $ ).

International audience; In this paper, we address the scalability of GeSeSbN based Ovonic Threshold Switch selector for high density crossbar integration. Impact of cell size down to 80nm on selector electrical characteristics, typical switching voltages and currents are deeply investigated on kbit arrays. Experimental results, combined with semi-analytical model, demonstrate a filamentary behavior in the OTS switching operation. OTS endurance failure is investigated. Device breakdown is correlated to a maximum amount of electronic charges flowing through the stack. Cell downscaling improves OTS insulating capabilities without any switching voltage increase, allowing high density crossbar integration and low voltage consumption, with 200Mb bank size estimated for 80nm OTS cell size with similar to 2.3V switching voltage.

Phase-Change Memory (PCM) demonstrated to be a mature Non- Volatile Memory technology to address Storage Class Memory (SCM) applications that can be distinguished in memory-type (M-SCM) and storage-type (S-SCM). In this work, we present how aGeSbTe (aGST) alloy can address both SCM types, in particular using Si doping. Thanks to the electrical characterization of 4 kb PCM arrays, we show how Si doping in aGST helps tuning the crystallization dynamic during the programming operations, leading to highly reliable intermediate resistance states. We support our results by TEM analyses and finally we present improved multi-level cell (MLC) operations in Si-doped devices, achieved already with a simple double-step protocol. We demonstrate the aGST alloy suitability for SCM applications: undoped alloy allows targeting M-SCM thanks to its high endurance and high programming speed, whereas Si-doped aGST featuring MLC capability and improved data retention can address S-SCM specifications.

International audience; In this paper, we demonstrate at array level and in industrial like devices, the extreme scaling down to nanometric dimensions of the Phase-Change Memory technology thanks to an innovative Self-Nano-Confined PCM device (SNC PCM). We show how such solution based on an optimized GeN/GeSbTe stack enables programming down to 50 $\mu$A and endurance up to more than 10$^8$ cycles in 4 kb arrays, with the huge advantage of having no dependency on the critical lithography dimension used. We further demonstrate that the high thermal confinement achieved in such extremely confined PCM makes the engineering of the SET pulse becoming fundamental in order to assure a reduced SET resistance drift. Moreover, thanks to physico-chemical analyses and 3D TCAD electro-thermal simulations we demonstrate the Self-Nano-Confined phenomenon, revealing an effective scaling of the PCM down to around 12 nm and how it improves the thermal efficiency of the device thanks to a reduced current density and thermal stress in the system.

We present for the first time Si-doped HfO 2 -based OxRAM 16kbit arrays integrated in the BEOL of 28nm FDSOI CMOS, targeting low cost and low power embedded applications. Excellent LRS/HRS raw distributions are reported on 1T-1R 16kbit arrays with zero bit-fail up to 105 cycles, using core logic (GO1) selector transistors. The OxRAM compatibility with GO1 transistors paves the way to arrays with minimum bitcell area of $0.066\ \mu \mathrm{m}^{2}$ at $125\mu \mathrm{A}$ programming current. We also demonstrate direct correlation between transistor compliance current variability within the 1T-1R array and the LRS distribution. This result indicates that the intrinsic LRS variability is smaller than the measured one. SPICE Monte-Carlo simulations confirm the large compliance current dispersion measured on transistors designed at minimum gate length and show path to improve even further the LRS distribution and hence the OxRAM memory window.

International audience; Scaling of planar HfO2-based ferroelectric capacitors is investigated experimentally by varying the capacitor area within 5 orders of magnitude, under the scope of limited thermal budget for crystallization. Both Hf0.5Zr0.5O2 (HZO) and Si-doped HfO2 (HSO) based metal/ferroelectric/metal (MFM) capacitors with 10 nm dielectric film thickness and TiN electrodes are demonstrated to be ferroelectric when integrated in a back-end of line (BEOL) of 130 nm CMOS technology, with a maximum thermal budget below 500°C. When the area of the ferroelectric capacitors is scaled down from 7850 µm² to 0.28 µm², no degradation of the remanent polarization (2•PR > 10 µC/cm² for HSO, > 30 µC/cm² for HZO) or of the switching kinetics (down to 100 ns at 3V) is observed. Significant improvement of the field cycling endurance is demonstrated upon area scaling, consistent with the reduction of the total number of defects when devices are shrunk. The results pave the way to future BEOL demonstrations in 130 nm and more advanced nodes with record endurance similar to perovskite ferroelectrics.

International audience; 1S1R operation behavior and read margin variability are elucidated for the first time to our knowledge. To this aim, an extensive experimental study is performed on HfO2 OxRAM technology co-integrated with GSSN-based Ovonic Threshold Selector (OTS) in 4kb memory arrays, supported by deep theoretical analysis. A semi-analytical dynamic model is developed for selector operation, describing OTS switching variability. The voltage repartition in the 1S1R stack during the switching operation is clarified. The 1S1R read voltage margin is quantified statistically, based on OTS switching voltage dispersion, OxRAM variability and margin degradation during endurance. Based on this theoretical and experimental study, 1S1R figures of merit (overall functionality, reliability, and maximum bank size) are optimized based on OTS and OxRAM devices' features and programming conditions.

In this work, we have investigated the structural properties of Germanium (Ge)-Antimony (Sb)-Tellurium (Te) (GST) and Ge-rich GST thin film samples. The structural properties of the films are studied after annealing temperatures from room temperature to 450 degrees C. We performed the annealing procedure using a heat rate of 10 degrees C/min to achieve the target temperature for a duration of 10 min under N2 flow. After heat treatment, we carried out X-Ray Diffraction (XRD), Fourier Infra-Red Spectroscopy (FTIR), Raman Spectroscopy and Scanning Electron Microscopy (SEM) equipped with Energy-dispersive X-ray spectroscopy (EDS) to investigate the evolution of the structure in the samples.

Hardware for deep neural network (DNN) inference often suffers from insufficient on-chip memory, thus requiring accesses to separate memory-only chips. Such off-chip memory accesses incur considerable costs in terms of energy and execution time. Fitting entire DNNs in on-chip memory is challenging due, in particular, to the physical size of the technology. Here, we report a DNN inference system—termed Illusion—that consists of networked computing chips, each of which contains a certain minimal amount of local on-chip memory and mechanisms for quick wakeup and shutdown. An eight-chip Illusion system hardware achieves energy and execution times within 3.5% and 2.5%, respectively, of an ideal single chip with no off-chip memory. Illusion is flexible and configurable, achieving near-ideal energy and execution times for a wide variety of DNN types and sizes. Our approach is tailored for on-chip non-volatile memory with resilience to permanent write failures, but is applicable to several memory technologies. Detailed simulations also show that our hardware results could be scaled to 64-chip Illusion systems. A networked system of eight computing chips, each with its own on-chip memory, can be used to efficiently implement a range of neural network models and sizes.

IEEE transactions on nuclear science 68(8), 1542 - 1547 (2021). doi:10.1109/TNS.2021.3085962, Published by IEEE, New York, NY

The design of systems implementing low precision neural networks with emerging memories such as resistive random access memory (RRAM) is a significant lead for reducing the energy consumption of artificial intelligence. To achieve maximum energy efficiency in such systems, logic and memory should be integrated as tightly as possible. In this work, we focus on the case of ternary neural networks, where synaptic weights assume ternary values. We propose a two-transistor/two-resistor memory architecture employing a precharge sense amplifier, where the weight value can be extracted in a single sense operation. Based on experimental measurements on a hybrid 130 nm CMOS/RRAM chip featuring this sense amplifier, we show that this technique is particularly appropriate at low supply voltage, and that it is resilient to process, voltage, and temperature variations. We characterize the bit error rate in our scheme. We show based on neural network simulation on the CIFAR-10 image recognition task that the use of ternary neural networks significantly increases neural network performance, with regards to binary ones, which are often preferred for inference hardware. We finally evidence that the neural network is immune to the type of bit errors observed in our scheme, which can therefore be used without error correction., Comment: arXiv admin note: substantial text overlap with arXiv:2005.01973

In the present study the structural properties of Germanium (Ge)-Antimony (Sb)-Tellurium (Te) (GST) and Ge-rich GST thin film samples are investigated after annealing temperatures ranging from room temperature up to 450°C. We performed the annealing procedure using a heat rate of 10 °C/s to achieve the target temperature for a duration of 10 minutes under N2 flow. After heat treatment, we carried out X-Ray Diffraction (XRD), Fourier Infra-Red Spectroscopy (FTIR) and Raman Spectroscopy measurements to investigate the evolution of the structure in the samples. We confirm the delayed crystallization and structure evolution at higher temperatures of Ge-rich samples with respect to standard GST.

10nm Si-implanted HfO 2 is demonstrated to be ferroelectric for the first time when integrated in a Back- End-Of - Line (BEOL) 130nm CMOS. Scaled $.28\mu \mathrm{m}^{2}$ . capacitors demonstrate excellent endurance (109 cycles measured at 4 V, extrapolated to be 1012 at 3V), with tight coercive field distributions at wafer scale and excellent data retention at 85°C. To extend the ferroelectric BEOL compatibility of 10nm or thinner HfO 2 - based films, but also to understand their crystallization dynamics, nanosecond laser anneal is demonstrated to be very appealing, even for undoped HfO 2 .

International audience; In this paper, we investigate an innovative Ovonic Threshold Switching Selector (OTS) based on Multilayer structure (ML). Thanks to physico-chemical analysis and electrical characterization we show how MLs properties and structure can be tuned thanks to the engineering of each individual layer stoichiometry, thickness and interfaces. Ge/N-doped SbSe-based MLs OTS are analyzed by FTIR and Raman spectroscopy revealing the structural features present in the as-deposited materials and the strong interaction among individual layers at interfaces. We demonstrate the improved variability control of electrical parameters wrt standard OTS achieved by co-sputtering technique, and the high endurance capability of MLs OTS up to more than 2·10$^9$ cycles with stable nA leakage current. Moreover, we show how Ge-N bonds play a huge role on OTS thermal stability at 400° C and how they can be tuned more easily in ML OTS. These developments pave the way towards a new class of OTS materials and their engineering, ensuring high temperature stability and best tuning of electrical performances.

This paper presents an outlook of crosspoint memory arrays. We survey the characteristics, strengths and challenges of crosspoint array composed by a resistive memory device integrated in series with a back-end selector. We present the performances of our 1S1R technology composed of an HfO 2 OxRAM (1R) combined with a GeSeSbN based Ovonic Threshold Switch (1S). We benchmark our results with a detailed collection of experimental data reported in the literature.

This work explores a new method to reduce the energy consumption during the writing of process-spread resistive-based memories (RRAM), based on setting an initial electrical charge into a writing capacitor rather than applying constant voltage over a fixed time. By connecting a charged capacitor (constant charge source, CQS) to a RRAM device, we benefit of a lower energy requirement for setting the memory cells, for a given success rate. We propose a RRAM set circuit model, where switching conditions were extrapolated from experimental data. We then benchmark our proposed writing procedure with respect to the constant voltage source (CVS) scheme. Finally, we give experimental proof of concept by realization of a circuit interface that integrates the CQS protocol and is connected to a RRAM load. Results support the fact that setting the initial charge is a better choice to efficiently control the variability of the filamentary process in RRAM.

International audience; The brain performs intelligent tasks with extremely low energy consumption. This work takes its inspiration from two strategies used by the brain to achieve this energy efficiency: the absence of separation between computing and memory functions and reliance on low-precision computation. The emergence of resistive memory technologies indeed provides an opportunity to tightly co-integrate logic and memory in hardware. In parallel, the recently proposed concept of a Binarized Neural Network, where multiplications are replaced by exclusive NOR (XNOR) logic gates, offers a way to implement artificial intelligence using very low precision computation. In this work, we therefore propose a strategy for implementing low-energy Binarized Neural Networks that employs brain-inspired concepts while retaining the energy benefits of digital electronics. We design, fabricate, and test a memory array, including periphery and sensing circuits, that is optimized for this in-memory computing scheme. Our circuit employs hafnium oxide resistive memory integrated in the back end of line of a 130-nm CMOS process, in a two-transistor, two-resistor cell, which allows the exclusive NOR operations of the neural network to be performed directly within the sense amplifiers. We show, based on extensive electrical measurements, that our design allows a reduction in the number of bit errors on the synaptic weights without the use of formal error-correcting codes. We design a whole system using this memory array. We show on standard machine learning tasks (MNIST, CIFAR-10, ImageNet, and an ECG task) that the system has inherent resilience to bit errors. We evidence that its energy consumption is attractive compared to more standard approaches and that it can use memory devices in regimes where they exhibit particularly low programming energy and high endurance. We conclude the work by discussing how it associates biologically plausible ideas with more traditional digital electronics concepts.

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Write Termination (WT) circuits are a potential solution to solve these issues. However, previously reported WT circuits do not demonstrate sufficient reliability. In this work, we propose an industrially-ready WT circuit that was simulated with a RRAM model calibrated on real measurements. We perform extensive CMOS and RRAM variability simulations to extract the actual performances of the proposed WT circuit. Finally, we simulate the effects of the proposed WT circuit with memory traces extracted from real Edge-level data-intensive applications. Overall, we demonstrate 2× to 40× of energy gains at bit level. Moreover, we show from 1.9× to 16.2× energy gains with real applications running depending on the application memory access pattern thanks to the proposed WT circuit.

International audience; We demonstrate successful scalability of conventional 100µm diameter TiN/HZO/TiN capacitors down to 300nm by successfully co-integrating them for the first time in the Back-End-Of-Line of 130nm CMOS technology. Excellent performance are reported on those scaled bitcells, such as remnant polarization 2.PR > 40µC/cm², endurance > 10 11 cycles, switching speeds < 100ns, operating voltages < 4V, and data retention at 125°C. Presented results pave the way to < 10fJ/bit ultra-low power FeRAM for IoT applications.