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As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

Today's microprocessors and Systems-on-Chip are thermally limited. Many, therefore, employ dynamic thermal management (DTM) to maximize performance under a reliability constraint. Accurate thermal monitoring is critical as temperature underestimation can hurt reliability by excessively aging devices and overestimation can hurt performance by unnecessarily throttling computing components. Placing temperature sensors close to potential hotspots can help accuracy, but it is non-trivial as hotspots often form inside digital blocks consisting of densely placed digital cells. Large sensors can disrupt cell placement thereby increasing wire lengths and circuit delays. Furthermore, the sensor needs to operate from the same digital power grid as the circuit, one that can be scaled down to near-threshold regime via dynamic voltage scaling. Absent this ability, a separate power grid and dedicated supply voltage for the sensors further increases area overhead. In this paper, we present a sensor circuit that is compact and deeply voltage-scalable and can be embedded among digital cells with little disruption. Simulation results show that it achieves a comparable accuracy to other compact sensor circuits for DTM.

3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers) because the TSV size and pitch continue to scale in μm range and the metal to insulator ratio becomes smaller. Consequently, dense TSV farms can create lateral thermal blockages in thinned silicon substrate and exacerbate the local hotspots. In this paper, we propose a thermal-aware via farm placement technique for 3-D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. By incorporating thermal conductivity profile of via farm blocks in the design flow and enabling placement/aspect ratio optimization, the corresponding hotspots can be minimized within the wire-length and area constraints.

Side-channel attacks are important security challenges as they reveal sensitive information about on-chip activities. Among such attacks, the thermal side-channel has been shown to disclose the activities of key functional blocks and even encryption keys. This paper proposes a novel approach to proactively conceal critical activities in the functional layers while minimizing the power dissipation by (i) leveraging inherent characteristics of 3D integration to protect from side-channel attacks and (ii) dynamically generating custom activity patterns to match the activity to be concealed in the functional layers. Experimental analysis shows that 3D technology combined with the proposed run-time algorithm effectively reduces the Side-channel Vulnerability Factor (SVF) below 0.05 and the Spatial Thermal Side-channel Factor (STSF) below 0.59.

3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans, secure IC manufacturing and IP piracy. By utilizing intrinsic characteristics of 2.5D and 3D technologies, we propose novel opportunities in designing secure systems. We present: (i) a 3D architecture for shielding side-channel information; (ii) split fabrication using active interposers; (iii) circuit camouflage on monolithic 3D IC, and (iv) 3D IC-based security processing-in-memory (PIM). Advantages and challenges of these designs are discussed, showing that the new designs can improve existing counter-measures against security threats and further provide new security features.

Three-dimensional integration provides a new way of performance growth for microprocessor architectures. While a recent studies report promising performance improvement numbers, majority of the processor stacking options are thermally-limited. Elevated stack temperatures have significant effect on the overall energy efficiency and reliability of the processor; they also limit the potential peak performance improvement from the 3D implementation. Thermal characteristics of 3D stacks differ from 2D processors in various ways including: the nature of heat dissipation throughout the stack, thermal conductivity of the 3D structures such as micro-C4 layers, and hotspot interactions among layers. The intensity of the corresponding thermal problems is highly dependent on the 3D technology, processor and stack parameters. In this study we focus on spatial and temporal thermal characteristics of 3D multicore architectures using high-fidelity technology and processor models. Our experimental results highlight the need for integrating detailed thermal models in the design flow, starting with the early design stages. In addition, the reduced time constants and elevated on-chip temperatures indicate faster response time requirements for dynamic thermal management in processor stacking options.

Increased variability affects the efficiency of dynamic power and thermal management. Existing on-chip sensor infrastructure can be used to improve the inherent thermal imbalances among cores in a multicore architecture. Experimental analysis based on live measurements on a special test chip shows reduced on-chip heating with no performance loss.

Fast and effective exploration at the early stages of the design flow can yield significant improvement in the quality of the design and substantial reduction in design time. In this paper, we present an efficient technique to evaluate the power dissipation of scheduled Data Flow Graphs (DFGs). Scheduling dictates the compatibility of operations with respect to their assignments to functional units. Generally for scheduled DFGs, this relation is captured in the form of a comparability graph. As a consequence, the topology of the comparability graph determines the solution space available to the subsequent binding stage. In this work, our main contribution is a technique to assess the inherent flexibility of the schedules we start with. We developed early evaluation metrics in order to assess the degree of flexibility inherent in an initial schedule that will eventually affect the quality of the binding solution. Every schedule is associated with a compatibility graph that represents the conflicts and compatibilities among operations with respect to possible binding decisions. Our metric based evaluation technique is based on several properties (such as edge connectivity, edge weight distribution, etc.) of these compatibility graphs. These metrics essentially reflect the amount of freedom that is provided to the binding stage, which enables early assessment and relative comparison of different possible schedules without actually performing the resource-binding step. Our experimental framework integrates scheduling, early metric-based power evaluation, low power binding and power driven iterative rescheduling stages. The correlation between early evaluation and the power measurements after binding is as high as 0.95 and greater than 0.75 for majority of test cases. Experimental results on DFGs from MediaBench suite demonstrate the fact that metric evaluation is on average 42.6 times faster than performing optimal binding and iterative power improvement. Our results show that low power schedule selection is fast and effective. On average, the schedules selected by metric evaluation have 43% less power dissipation than schedules with iterative power improvement, based on a study set of 320 schedules. We also examined the thermal profile of the corresponding solutions. We observed that schedules selected with our metric evaluation technique have on average 12 C lower temperature, and the maximum on-chip temperatures are lower by 18 C compared to the overall average of all schedules. These thermal profiles are obtained using a functional unit-level thermal simulator after block-level floorplanning.

The primary objective of this paper is to provide an initial impetus to predictability driven design flow. Predictability is the quantified form of accuracy. The novelty lies in defining and using the idea of predictability. In order to illustrate the basic concepts we focus on the power estimation problem in RT-Level designs. Our experiments showed that predictability at RT-Level could be improved by making the resource delay constraints more stringent. This procedure may come with increased power dissipation. We present an optimal pseudo-polynomial time algorithm to optimize predictability while keeping the increase in power dissipation within a budget. We further extend this algorithm to generate an ∊-approximate solution in polynomial time where ∊ is a user defined parameter. The algorithm probably generates solutions that differ at-most ∊C max from the optimal. The future work would include extending the concept of predictability to other levels of design flow and other cost function. We envision a design automation system which does effective tradeoff between predictability and cost hence enabling efficient design exploration.

Full-chip thermal monitoring is an important and challenging issue in today's microprocessor design. In this paper, we propose a new information-theoretic framework to quantitatively model the uncertainty of on-chip temperature variation by differential entropy. Based on this framework, an efficient optimization scheme is developed to find the optimal spatial locations for temperature sensors such that the full-chip thermal map can be accurately captured with a minimum number of on-chip sensors. In addition, several efficient numerical algorithms are proposed to minimize the computational cost of the proposed entropy calculation and optimization. As will be demonstrated by our experimental examples, the proposed entropy-based method achieves superior accuracy (1.4× error reduction) for full-chip thermal monitoring over prior art.

Spin-transfer Torque Random Access Memory (STT-RAM) emerges for on-chip memory in microprocessor architectures. Thanks to the magnetic field based storage STT-RAM cells have immunity to radiation induced soft errors that affect electrical charge based data storage, which is a major challenge in SRAM based caches in current microprocessors. In this study we explore the soft error resilience benefits and design trade offs of 3D-stacked STT-RAM for multi-core architectures. We use 3D stacking as an enabler for modular integration of STT-RAM caches with minimum disruption in the baseline processor design flow, while providing further interconnectivity and capacity advantages. We take an in-depth look at alternative replacement schemes in terms of performance, power, temperature, and reliability trade-offs to capture the multi-variable optimization challenges microprocessor architectures face. We analyze and compare the characteristics of STT-RAM, SRAM, and DRAM alternatives for various levels of the cache hierarchy in terms of reliability.