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This article presents a mm-Wave concurrent dual-band (28 and 39 GHz) dual-beam phased array multiple-input multiple-output (MIMO) receiver (RX) front-end with mid-band rejection in the 22-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. This phased array RX front-end has four inputs and two output streams with fully connected (FC) configuration where it takes advantage of sharing low-noise amplifier (LNA) and quadrature network (QN) and using a unique phase shifter (PS) structure which allows power and area saving. The measured 3-dB gain bandwidth is from 23 to 30 GHz for the lower bandwidth with a peak gain of 21 dB at 29 GHz, and from 36 to 40 GHz for the upper bandwidth with a peak gain of 18 dB at 38.5 GHz, and a noise figure (NF) of a minimum of 6 and 7 dB at 28 and 37 GHz, respectively. The 21-dB mid-band rejection at 33.5 GHz is provided by the LNA to attenuate the out-of-band unwanted interference helping relaxing the linearity requirement. The entire single-channel RX front-end achieves third order intercept point (IIP3) varying from -18 to -11 dBm, and input 1-dB compression point varying from -25 to -18 dBm. The front-end has 5-bit phase control and 7-dB gain control achieving the rms phase and gain errors less than 6° and 1.2 dB, respectively, enabling orthogonality. This array demonstrates the concurrent functionality and carrier aggregation (CA) for over-the-air (OTA) beam-steering and error vector magnitude (EVM) measurements. The chip has a length of $2738~ \mu \text{m}$ , a width of $1808~ \mu \text{m}$ , and an area of 4.95 mm2 including all dc, radio frequency (RF) pads, and decoupling capacitors.

Analog photonic links require linear drive of electrooptic modulators at high frequency to support emerging millimeter wave (mm-wave) communication standards. However, this is challenging due to the nonlinear distortion of commonly used Mach–Zehnder modulators (MZMs). This article presents the first CMOS MZM driver capable of operating over a wide 20–35-GHz frequency range with a programmable linearizer. A broadband design is achieved with a magnetically coupled resonator (MCR) technique that provides wideband impedance matching for the interstage and output-stage matching networks. Linearization is achieved with a topology consisting of inverter-based amplifier segments that provide programmable predistortion gains over the input signal regions. Fabricated in 28-nm CMOS, the driver delivers 2.5-Vpp swing to an external MZM. Operating the majority of the circuitry at 0.9 V, except for the 1.6-V output stage, allows for a power consumption of only 180 mW. The proposed programmable linearizer is able to compensate the amplitude-to-amplitude modulation (AM–AM) compression of the amplifier stages and the external MZM, extending output power 1-dB compression point ( $\text {OP}_{1~\text {dB}}$ ) of the whole radio-over-fiber (RoF) link by 3 dB and achieving 4.8-dBm third-order input intercept point (IIP3) at 25 GHz.

This article presents a concurrent dual-band low-noise amplifier (LNA) in a 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS process. This three-stage cascode LNA is designed to operate concurrently between 23.3 and 30.3 GHz and 38 and 44.7 GHz ( $K$ -/ $Ka$ -band) for 5G mm-wave bands. To achieve a high rejection in the stopband between the two passbands, a notch circuit is designed using a cross-coupled pair (XCP) to mitigate the limited inductor/capacitor quality factors, thus enhancing notch depth in the second stage. The gain of the LNA can be digitally controlled in the third stage by over eight steps of 1 dB. The input matching network also acts like a high-pass filter to generate a sufficient rejection for frequencies below 13 GHz. The measured gain is 22 dB at 24 GHz and 16 dB at 40.5 GHz, with a 3-dB bandwidth of 23.3–30.3 GHz for low passband and 38–44.7 GHz for high passband. The LNA achieves a noise figure (NF) of 2.55/4.75 dB at 28/40 GHz, a rejection of 19.2 dB at 34.1 GHz, and a power consumption of 18 mW with supply voltages of 0.8 V for the first stage, and 1.0 V for the rest. The chip has a length of $1035 ~\mu \text{m}$ , a width of $885 ~\mu \text{m}$ , and an area of $0.916 mm^{2}$ including all pads and decoupling capacitors.

This article presents a 20–43.5-GHz mm-wave silicon photonic reconfigurable receiver (RX) front-end (FE) for wideband mm-wave 5G systems. The wideband front-end consists of an input electro-optic (E/O) converter, a silicon photonic integrated circuit (PIC), and an output opto-electric (O/E) converter. The silicon PIC is programmable either as a mm-wave band-pass filter (BPF) for channel selection and jammer rejection or as a mm-wave notch filter for jammer rejection in adjacent and alternate channels. Both the BPF and notch filter center frequencies are continuously tunable over a 20- and 43.5-GHz range, with the BPF bandwidth also configurable between 4.7-6-GHz. In order to show the effect of in-band jammer rejection on improving system linearity and overall received signal quality, a 4-channel system is demonstrated with the BPF configured with 5-GHz 3-dB bandwidth. The whole mm-wave system is optimized for minimum noise figure ($NF$), maximum linearity (third-order input intercept point ($IIP_{3}$) and input 1-dB compression power ($IP_{\text{1}\,\text{dB}}$), and maximum signal to noise ratio (SNR) through modulator bias control and optical amplification. An IM$_{3}$ reduction, and thus IIP$_{3}$ improvement, of 22.5-$\text{dB}$ is achieved. This yields an average error vector magnitude (EVM) improvement of 4.5-$\text{dB}$ at 20-GHz and 50-$\text{Msps}$ 16-quadrature amplitude modulation (16-QAM), with an overall EVM of −25.5-$\text{dB}$. To the best of the authors' knowledge, this is the first silicon photonic implementation of a wideband reconfigurable mm-wave RX that covers the entire mm-wave sub-45-GHz band.