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146 results on '"Enrico Mezzetti"'

4. SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI.

Author

Jaume Abella 0001, Jon Pérez 0001, Cristofer Englund, Bahram Zonooz, Gabriele Giordana, Carlo Donzella, Francisco J. Cazorla, Enrico Mezzetti, Isabel Serra, Axel Brando, Irune Agirre, Fernando Eizaguirre, Thanh Hai Bui, Elahe Arani, Fahad Sarfraz, Ajay Balasubramaniam, Ahmed Badar, Ilaria Bloise, Lorenzo Feruglio, Ilaria Cinelli, Davide Brighenti, and Davide Cunial

Published
2023
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24. Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems

Author

Jordi Cardona, Carles Hernández, Jaume Abella, Enrico Mezzetti, and Francisco J. Cazorla

Subjects
Electrical and Electronic Engineering, Computer Graphics and Computer-Aided Design, Computer Science Applications
Abstract

The computing capacity demanded by embedded systems is on the rise as software implements more functionalities, ranging from best-effort entertainment functions to performance-guaranteed safety-related functions. Heterogeneous manycore processors, using wormhole mesh (wmesh) Network-on-Chips (NoCs) as the main communication means, and contention block among applications, are increasingly considered to deliver the required computing performance. Most research efforts on software timing analysis have focused on deriving bounds (estimates) to the contention that tasks can suffer when accessing wmesh NoCs. However, less effort has been devoted to an equally important problem, namely, accurately measuring the actual contention tasks generate each other on the wmesh which is instrumental during system validation to diagnose any software timing misbehavior and determine which tasks are particularly affected by contention on specific wmesh routers. In this article, we work on the foundations of contention measuring in wmesh NoCs and propose and explain the rationale of a golden metric , called task PairWise Contention (PWC). PWC allows ascribing the actual share of the contention a given task suffers in the wmesh to each of its co-runner tasks at packet level. We also introduce and formalize a Golden Reference Value (GRV) for PWC that specifically defines a criterion to fairly break down the contention suffered by a task among its co-runner tasks in the wmesh. Our evaluation shows that GRV effectively captures how contention occurs by identifying the actual core (task) causing contention and whether contention is caused by local or remote interference in the wmesh.

Published
2023

29. PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis.

Author

Francisco J. Cazorla, Jaume Abella 0001, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoit Triquet, Carles Hernández 0001, Code Lo, Cristian Maxim, David Morales, Eduardo Quiñones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernández, Mladen Slijepcevic, Philippa Conmy, and Walid Talaboulma

Published
2016
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40. Quasi Isolation QoS Setups to Control MPSoC Contention in Integrated Software Architectures

Author

Sergio Garcia-Esteban and Alejandro Serrano-Cases and Jaume Abella and Enrico Mezzetti and Francisco J. Cazorla, Garcia-Esteban, Sergio, Serrano-Cases, Alejandro, Abella, Jaume, Mezzetti, Enrico, Cazorla, Francisco J., Sergio Garcia-Esteban and Alejandro Serrano-Cases and Jaume Abella and Enrico Mezzetti and Francisco J. Cazorla, Garcia-Esteban, Sergio, Serrano-Cases, Alejandro, Abella, Jaume, Mezzetti, Enrico, and Cazorla, Francisco J.

Abstract

The use of integrated architectures, such as integrated modular avionics (IMA) in avionics, IMA-SP in space, and AUTOSAR in automotive, running on Multi-Processor System-on-Chip (MPSoC) is on the rise. Timing isolation among the different software partitions or applications thereof in an integrated architecture is key to simplifying software integration and its timing validation by ensuring the performance of each partition has no or very limited impact on others despite they share MPSoC’s hardware resources. In this work, we contend that the increasing hardware support for Quality of Service (QoS) guarantees in modern MPSoCs can be leveraged via specific setups to provide strong, albeit not full, isolation among different software partitions. We introduce the concept of Quasi Isolation QoS (QIQoS) setups and instantiate it in the Xilinx Zynq UltraScale+. To that end, out of the millions of setups offered by the different QoS mechanisms, we identify specific QoS configurations that isolate the traffic of time-critical software partitions executing in the core cluster from that generated by contender partitions in the programmable logic. Our results show that the selected isolation setup results in performance variations of the partitions run in the computing cores that are below 6 percentage points, even under scenarios with extremely high traffic coming from the programmable logic.

Published
2023
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41. On Neural Networks Redundancy and Diversity for Their Use in Safety-Critical Systems

Author

Axel Brando, Isabel Serra, Enrico Mezzetti, Francisco J. Cazorla, Jon Perez-Cerrolaza, Jaume Abella, and Barcelona Supercomputing Center

Subjects
Neural networks (Computer science), Redundancy, General Computer Science, Deep learning (Machine learning), Embedded systems, Intel·ligència artificial, Informàtica::Intel·ligència artificial [Àrees temàtiques de la UPC], Deep learning, Safety, Contingency management, Neural networks
Abstract

An increasing number of critical functionalities integrated in embedded critical systems rely on deep learning (DL) technology. This article summarizes certain key aspects of DL’s intrinsic stochastic and training-data-dependent nature that are at odds with current domain-specific functional safety standards. We exemplify how redundancy and diversity of neural networks can help to reconcile DL technology and functional safety requirements. The research leading to these results has received funding from the European Research Council (ERC) grant agreement No. 772773 (SuPerCom), the Horizon Europe Programme under the SAFEXPLAIN Project (www.safexplain.eu), grant agreement num.101069595, and the Spanish Ministry of Science and Innovation under grant PID2019-107255GBC21/AEI/10.13039/501100011033.

Published
2023

42. Vector extensions in COTS processors to increase guaranteed performance in real-time systems

Author

Roger Pujol, Josep Jorba, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco Cazorla, Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors, and Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions

Subjects
Hardware and Architecture, Embedded systems, Vector extensions, Real-time data processing, Parallel programming (Computer science), Programació en paral·lel (Informàtica), Ordinadors immersos, Sistemes d', Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], Embedded computer systems, Real-time, Temps real (Informàtica), Software
Abstract

The need for increased application performance in high-integrity systems like those in avionics is on the rise as software continues to implement more complex functionalities. The prevalent computing solution for future high-integrity embedded products are multi-processors systems-on-chip (MPSoC) processors. MPSoCs include CPU multicores that enable improving performance via thread-level parallelism. MPSoCs also include generic accelerators (GPUs) and application-specific accelerators. However, the data processing approach (DPA) required to exploit each of these underlying parallel hardware blocks carries several open challenges to enable the safe deployment in high-integrity domains. The main challenges include the qualification of its associated runtime system and the difficulties in analyzing programs deploying the DPA with out-of-the-box timing analysis and code coverage tools. In this work, we perform a thorough analysis of vector extensions (VExt) in current COTS processors for high-integrity systems. We show that VExt prevent many of the challenges arising with parallel programming models and GPUs. Unlike other DPAs, VExt require no runtime support, prevent by design race conditions that might arise with parallel programming models, and have minimum impact on the software ecosystem enabling the use of existing code coverage and timing analysis tools. We develop vectorized versions of neural network kernels and show that the NVIDIA Xavier VExt provide a reasonable increase in guaranteed application performance of up to 2.7x. Our analysis contends that VExt are the DPA approach with arguably the fastest path for adoption in high-integrity systems. This work has received funding from the the European Research Council (ERC) grant agreement No. 772773 (SuPerCom) and the Spanish Ministry of Science and Innovation (AEI/10.13039/501100011033) under grants PID2019-107255GB-C21 and IJC2020-045931-I.

Published
2023

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