Search

We propose non-volatile memory (NVM) designs based on Piezoelectric Strain FET (PeFET) utilizing a piezoelectric/ferroelectric (PE/FE such as PZT) coupled with 2D Transition Metal Dichalcogenide (2D-TMD such as MoS2) transistor. The proposed NVMs store bit information in the form of polarization (P) of the FE/PE, use electric-field driven P-switching for write and employ piezoelectricity induced dynamic bandgap modulation of 2D-TMD channel for bit sensing. We analyze PeFET with COMSOL based 3D modeling showing that the circuit-driven optimization of PeFET geometry is essential to achieve effective hammer-and-nail effect and adequate bandgap modulation for NVM read. Our results show that distinguishability of binary states to up to 11X is achieved in PeFETs.We propose various flavors of PeFET NVMs, namely (a) high density (HD) NVM featuring a compact access-transistor-less bit-cell, (b) 1T-1PeFET NVM with segmented architecture, targeted for optimized write energy and latency and (c) cross-coupled (CC) NVM offering a trade-off between area and latency.PeFET NVMs offer up to 7X smaller cell area, 66% lower write energy, 87% lower read energy and 44% faster read compared to 2D-FET SRAM. This comes at the cost of high write latency in PeFET NVMs, which can be minimized by virtue of optimized PE geometry., 8 pages, 13 figures In the peer review process of the journal of IEEE Transactions on Electron Devices

Quantum Approximate Optimization Algorithm (QAOA) is a promising hybrid quantum-classical algorithm for solving combinatorial optimization problems. However, it cannot overcome qubit limitation for large-scale problems. Furthermore, the execution time of QAOA scales exponentially with the problem size. We propose a Divide-and-Conquer QAOA (DC-QAOA) to address the above challenges for graph maximum cut (MaxCut) problem. The algorithm works by recursively partitioning a larger graph into smaller ones whose MaxCut solutions are obtained with small-size NISQ computers. The overall solution is retrieved from the sub-solutions by applying the combination policy of quantum state reconstruction. Multiple partitioning and reconstruction methods are proposed/ compared. DC-QAOA achieves 97.14% approximation ratio (20.32% higher than classical counterpart), and 94.79% expectation value (15.80% higher than quantum annealing). DC-QAOA also reduces the time complexity of conventional QAOA from exponential to quadratic.

Quantum(-inspired) annealers show promise in solving combinatorial optimisation problems in practice. There has been extensive researches demonstrating the utility of D-Wave quantum annealer and quantum-inspired annealer, i.e., Fujitsu Digital Annealer on various applications, but few works are comparing these platforms. In this paper, we benchmark quantum(-inspired) annealers with three combinatorial optimisation problems ranging from generic scientific problems to complex problems in practical use. In the case where the problem size goes beyond the capacity of a quantum(-inspired) computer, we evaluate them in the context of decomposition. Experiments suggest that both annealers are effective on problems with small size and simple settings, but lose their utility when facing problems in practical size and settings. Decomposition methods extend the scalability of annealers, but they are still far away from practical use. Based on the experiments and comparison, we discuss the advantages and limitations of quantum(-inspired) annealers, as well as the research directions that may improve the utility and scalability of the these emerging computing technologies.

Quantum processing units (QPUs) executing annealing algorithms have shown promise in optimization and simulation applications. Hybrid algorithms are a natural bridge to additional applications of larger scale. We present a straightforward and effective method for solving larger-than-QPU lattice-structured Ising optimization problems. Performance is compared against simulated annealing with promising results, and improvement is shown as a function of the generation of D-Wave QPU used., 21 pages, 15 figures, supplementary code attachment

Approximate computing is known for enhancing deep neural network accelerators' energy efficiency by introducing inexactness with a tolerable accuracy loss. However, small accuracy variations may increase the sensitivity of these accelerators towards undesired subtle disturbances, such as permanent faults. The impact of permanent faults in accurate deep neural network (AccDNN) accelerators has been thoroughly investigated in the literature. Conversely, the impact of permanent faults and their mitigation in approximate DNN (AxDNN) accelerators is vastly under-explored. Towards this, we first present an extensive fault resilience analysis of approximate multi-layer perceptrons (MLPs) and convolutional neural networks (CNNs) using the state-of-the-art Evoapprox8b multipliers in GPU and TPU accelerators. Then, we propose a novel fault mitigation method, i.e., fault-aware retuning of weights (Fal-reTune). Fal-reTune retunes the weights using a weight mapping function in the presence of faults for improved classification accuracy. To evaluate the fault resilience and the effectiveness of our proposed mitigation method, we used the most widely used MNIST, Fashion-MNIST, and CIFAR10 datasets. Our results demonstrate that the permanent faults exacerbate the accuracy loss in AxDNNs compared to the AccDNN accelerators. For instance, a permanent fault in AxDNNs can lead to 56\% accuracy loss, whereas the same faulty bit can lead to only 4\% accuracy loss in AccDNN accelerators. We empirically show that our proposed Fal-reTune mitigation method improves the performance of AxDNNs up to 98%, even with fault rates of up to 50%. Furthermore, we observe that the fault resilience in AxDNNs is orthogonal to their energy efficiency., Comment: Accepted for publication in the IEEE Transactions on Very Large Scale Integration Systems (TVLSI) journal

Integrated photonic neural networks (IPNNs) are emerging as promising successors to conventional electronic AI accelerators as they offer substantial improvements in computing speed and energy efficiency. In particular, coherent IPNNs use arrays of Mach-Zehnder interferometers (MZIs) for unitary transformations to perform energy-efficient matrix-vector multiplication. However, the underlying MZI devices in IPNNs are susceptible to uncertainties stemming from optical lithographic variations and thermal crosstalk and can experience imprecisions due to non-uniform MZI insertion loss and quantization errors due to low-precision encoding in the tuned phase angles. In this paper, we, for the first time, systematically characterize the impact of such uncertainties and imprecisions (together referred to as imperfections) in IPNNs using a bottom-up approach. We show that their impact on IPNN accuracy can vary widely based on the tuned parameters (e.g., phase angles) of the affected components, their physical location, and the nature and distribution of the imperfections. To improve reliability measures, we identify critical IPNN building blocks that, under imperfections, can lead to catastrophic degradation in the classification accuracy. We show that under multiple simultaneous imperfections, the IPNN inferencing accuracy can degrade by up to 46%, even when the imperfection parameters are restricted within a small range. Our results also indicate that the inferencing accuracy is sensitive to imperfections affecting the MZIs in the linear layers next to the input layer of the IPNN., This paper has been accepted for publication in the IEEE Journal of Lightwave Technology (JLT)

The joint communication and sensing (JCAS) technique has drawn great attention due to its high spectrum efficiency by using the same transmit signal for both communication and sensing. Exploiting the correlation between the uplink (UL) channel and the sensing results, we propose a sensing-aided Kalman filter (SAKF)-based channel state information (CSI) estimation method for UL JCAS, which exploits the angle-of-arrival (AoA) estimation to improve the CSI estimation accuracy. A Kalman filter (KF)-based CSI enhancement method is proposed to refine the least-square CSI estimation by exploiting the estimated AoA as the prior information. Simulation results show that the bit error rates (BER) of UL communication using the proposed SAKF-based CSI estimation method approach those using the minimum mean square error (MMSE) method, while at significantly reduced complexity., 4 pages, 5 figures, IEEE letter

Vertical-Cavity Surface-Emitting Lasers (VCSELs) are highly promising devices for the construction of neuromorphic photonic information processing systems, due to their numerous desirable properties such as low power consumption, high modulation speed, compactness, and ease of manufacturing. Of particular interest is the ability of VCSELs to exhibit neural-like spiking responses, much like biological neurons, but at ultrafast sub-nanosecond rates; thus offering great prospects for high-speed light-enabled neuromorphic (spike-based) processors. Recent works have shown the use the spiking dynamics in VCSELs for pattern recognition and image processing problems such as image data encoding and edge-feature detection. Additionally, VCSELs have also been used recently as nonlinear elements in photonic reservoir computing (RC) implementations, yielding excellent state of the art operation. This work introduces and experimentally demonstrates for the first time the new concept of a Ghz-rate photonic spiking neural network (SNN) built with a single VCSEL neuron. The reported system effectively implements a photonic VCSEL-based spiking reservoir computer, and demonstrates its successful application to a complex nonlinear classification task. Importantly, the proposed system benefits from a highly hardware-friendly, inexpensive realization (built with a single VCSEL and off-the-shelf fibre-optic components), for high-speed (GHz-rate inputs) and low-power (sub-mW optical input power) photonic operation. These results open new pathways towards future neuromorphic photonic spike-based information processing systems based upon VCSELs (or other laser types) for novel ultrafast machine learning and AI hardware., 10 pages, 10 figures. Intended for submission to IEEE Journal of Selected Topics in Quantum Electronics

Data-driven modeling approaches such as jump tables are promising techniques to model populations of resistive random-access memory (ReRAM) or other emerging memory devices for hardware neural network simulations. As these tables rely on data interpolation, this work explores the open questions about their fidelity in relation to the stochastic device behavior they model. We study how various jump table device models impact the attained network performance estimates, a concept we define as modeling bias. Two methods of jump table device modeling, binning and Optuna-optimized binning, are explored using synthetic data with known distributions for benchmarking purposes, as well as experimental data obtained from TiOx ReRAM devices. Results on a multi-layer perceptron trained on MNIST show that device models based on binning can behave unpredictably particularly at low number of points in the device dataset, sometimes over-promising, sometimes under-promising target network accuracy. This paper also proposes device level metrics that indicate similar trends with the modeling bias metric at the network level. The proposed approach opens the possibility for future investigations into statistical device models with better performance, as well as experimentally verified modeling bias in different in-memory computing and neural network architectures.

This paper investigates the channel impulse response (CIR), i.e., the molecule hitting rate, of a molecular communication (MC) system employing an absorbing receiver (RX) covered by multiple non overlapping receptors. In this system, receptors are heterogeneous, i.e., they may have different sizes and arbitrary locations. Furthermore, we consider two types of transmitter (TX), namely a point TX and a membrane fusion (MF)-based spherical TX. We assume the point TX or the center of the MF-based TX has a fixed distance to the center of the RX. Given this fixed distance, the TX can be at different locations and the CIR of the RX depends on the exact location of the TX. By averaging over all possible TX locations, we analyze the expected molecule hitting rate at the RX as a function of the sizes and locations of the receptors, where we assume molecule degradation may occur during the propagation of the signaling molecules. Notably, our analysis is valid for different numbers, a wide range of sizes, and arbitrary locations of the receptors, and its accuracy is confirmed via particle-based simulations. Exploiting our numerical results, we show that the expected number of absorbed molecules at the RX increases with the number of receptors, when the total area on the RX surface covered by receptors is fixed. Based on the derived analytical expressions, we compare different geometric receptor distributions by examining the expected number of absorbed molecules at the RX. We show that evenly distributed receptors result in a larger number of absorbed molecules than other distributions. We further compare three models that combine different types of TXs and RXs., This paper has been submitted to IEEE journals for possible publication. This paper was accepted for presentation in part at the 2022 IEEE International Conference on Communication (ICC). arXiv:2111.02020v2. arXiv admin note: text overlap with arXiv:2111.02020

The explosion of artificial intelligence and machine-learning algorithms, connected to the exponential growth of the exchanged data, is driving a search for novel application-specific hardware accelerators. Among the many, the photonics field appears to be in the perfect spotlight for this global data explosion, thanks to its almost infinite bandwidth capacity associated with limited energy consumption. In this review, we will overview the major advantages that photonics has over electronics for hardware accelerators, followed by a comparison between the major architectures implemented on Photonics Integrated Circuits (PIC) for both the linear and nonlinear parts of Neural Networks. By the end, we will highlight the main driving forces for the next generation of photonic accelerators, as well as the main limits that must be overcome.

This paper presents a multi-bit reconfigurable intelligent surface (RIS) with a high phase resolution, capable of beam-steering in the azimuthal plane at sub-6 Gigahertz (GHz). Field trials in realistic indoor deployments have been carried out, with coverage enhancement performance ascertained for three common wireless communication scenarios. Namely, serving users in an open lobby with mixed line of sight and non-line of sight conditions, communication via a junction between long corridors, and a multi-floor scenario with propagation via windows. This work explores the potential for reconfigurable intelligent surface (RIS) deployment to mitigate non-line of sight effects in indoor wireless communications. In a single transmitter, single receiver non-line of sight link, received power improvement of as much as 40 dB is shown to be achievable by suitable placement of a RIS, with an instantaneous bandwidth of at least 100 MHz possible over a 3 to 4.5 GHz range. In addition, the effects of phase resolution on the optimal power reception for the multi-bit RIS have been experimentally verified, with a 2.65 dB improvement compared to a 1-bit case.

Low energy barrier magnet (LBM) technology has recently been proposed as a candidate for accelerating algorithms based on energy minimization and probabilistic graphs because their physical characteristics have a one-to-one mapping onto the primitives of these algorithms. Many of these algorithms have a much higher tolerance for error compared to high-accuracy numerical computation. LBM, however, is a nascent technology, and devices show high sample-to-sample variability. In this work, we take a deep dive into the overall fidelity afforded by this technology in providing computational primitives for these algorithms. We show that while the compute results show finite deviations from zero variability devices, the margin of error is almost always certifiable to a certain percentage. This suggests that LBM technology could be a viable candidate as an accelerator for popular emerging paradigms of computing., Comment: 5 pages, 8 figures

Analog computing is attractive compared to digital computing due to its potential for achieving higher computational density and higher energy efficiency. However, unlike digital circuits, conventional analog computing circuits cannot be easily mapped across different process nodes due to differences in transistor biasing regimes, temperature variations and limited dynamic range. In this work, we generalize the previously reported margin-propagation-based analog computing framework for designing novel \textit{shape-based analog computing} (S-AC) circuits that can be easily cross-mapped across different process nodes. Similar to digital designs S-AC designs can also be scaled for precision, speed, and power. As a proof-of-concept, we show several examples of S-AC circuits implementing mathematical functions that are commonly used in machine learning (ML) architectures. Using circuit simulations we demonstrate that the circuit input/output characteristics remain robust when mapped from a planar CMOS 180nm process to a FinFET 7nm process. Also, using benchmark datasets we demonstrate that the classification accuracy of a S-AC based neural network remains robust when mapped across the two processes and to changes in temperature., Comment: 14 Pages, 15 Figures, 5 Tables. This work has been accepted in IEEE for publication. Copyright may be transferred without notice, after which this version may no longer be accessible

Memristor-based neuromorphic computing could overcome the limitations of traditional von Neumann computing architectures -- in which data are shuffled between separate memory and processing units -- and improve the performance of deep neural networks. However, this will require accurate synaptic-like device performance, and memristors typically suffer from poor yield and a limited number of reliable conductance states. Here we report floating gate memristive synaptic devices that are fabricated in a commercial complementary metal-oxide-semiconductor (CMOS) process. These silicon synapses offer analogue tunability, high endurance, long retention times, predictable cycling degradation, moderate device-to-device variations, and high yield. They also provide two orders of magnitude higher energy efficiency for multiply-accumulate operations than graphics processing units. We use two 12-by-8 arrays of the memristive devices for in-situ training of a 19-by-8 memristive restricted Boltzmann machine for pattern recognition via a gradient descent algorithm based on contrastive divergence. We then create a memristive deep belief neural network consisting of three memristive restricted Boltzmann machines. We test this on the modified National Institute of Standards and Technology (MNIST) dataset, demonstrating recognition accuracy up to 97.05%.

The Single Flux Quantum (SFQ) logic family is a novel digital logic as it provides ultra-fast and energy-efficient circuits. For large-scale SFQ circuit design, specialized electronic design automation (EDA) tools are required due to the differences in logic type, timing constraints and circuit architecture, in contrast to the CMOS logic. In order to improve the overall performance of an SFQ circuit, an efficient routing algorithm should be applied during the layout design to perform accurate timing adjustment for fixing hold violations and optimizing critical paths. Thus, a hybrid Josephson transmission line and passive transmission line routing framework is proposed. It consists of four main modules and an exploration of the potential timing performance based on the given layout placement. The proposed routing tool is demonstrated on seven testbench circuits. The obtained results demonstrate that the operating frequency is greatly improved, and all the hold violations are eliminated for each circuit.

Hyperdimensional computing (HDC) is an emerging computational framework inspired by the brain that operates on vectors with thousands of dimensions to emulate cognition. Unlike conventional computational frameworks that operate on numbers, HDC, like the brain, uses high dimensional random vectors and is capable of one-shot learning. HDC is based on a well-defined set of arithmetic operations and is highly error-resilient. The core operations of HDC manipulate HD vectors in bulk bit-wise fashion, offering many opportunities to leverage parallelism. Unfortunately, on conventional Von-Neuman architectures, the continuous movement of HD vectors among the processor and the memory can make the cognition task prohibitively slow and energy-intensive. Hardware accelerators only marginally improve related metrics. On the contrary, only partial implementation of an HDC framework inside memory, using emerging memristive devices, has reported considerable performance/energy gains. This paper presents an architecture based on racetrack memory (RTM) to conduct and accelerate the entire HDC framework within the memory. The proposed solution requires minimal additional CMOS circuitry and uses a read operation across multiple domains in RTMs called transverse read (TR) to realize exclusive-or (XOR) and addition operations. To minimize the overhead the CMOS circuitry, we propose an RTM nanowires-based counting mechanism that leverages the TR operation and the standard RTM operations. Using language recognition as the use case demonstrates 7.8x and 5.3x reduction in the overall runtime and energy consumption compared to the FPGA design, respectively. Compared to the state-of-the-art in-memory implementation, the proposed HDC system reduces the energy consumption by 8.6x., Preprint, accepted for publication, ACM Transactions on Embedded Computing Systems. ACM Trans. Embed. Comput. Syst. (March 2022)

In conventional molecular communication (MC) systems, the signaling molecules used for information transmission are stored, released, and then replenished by a transmitter (TX). However, the replenishment of signaling molecules at the TX is challenging in practice. Furthermore, in most envisioned MC applications, e.g., in the medical field, it is not desirable to insert the TX into the MC system, as this might impair natural biological processes. In this paper, we propose the concept of media modulation based MC where the TX is placed outside the channel and utilizes signaling molecules already present inside the system. The signaling molecules can assume different states which can be switched by external stimuli. Hence, in media modulation based MC, the TX modulates information into the state of the signaling molecules. In particular, we exploit the group of photochromic molecules, which undergo light-induced reversible state transitions, for media modulation. We study the usage of these molecules for information transmission in a three-dimensional duct system, which contains an eraser, a TX, and a receiver for erasing, writing, and reading of information via external light, respectively. We develop a statistical model for the received signal. We adopt a maximum likelihood detector and show that it can be reduced to a threshold based detector. Furthermore, we derive analytical expressions for the optimal threshold value and the resulting bit error rate (BER), respectively. Finally, we investigate the impact of various system parameters on the BER of media modulation based MC. Both the statistical model and BER results are verified by computer simulations. Our results reveal that media modulation enables reliable information transmission, validating it as a promising alternative to MC based on molecule emitting TXs., 30 pages, 9 figures, 1 table. This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible

Reconfigurable intelligent surface (RIS) based reflection modulation has been considered as a promising information delivery mechanism, and has the potential to realize passive information transfer of a RIS without consuming any additional radio frequency chain and time/frequency/energy resources. The existing on-off reflection modulation (ORM) schemes are based on manipulating the "on/off" states of RIS elements, which may lead to the degradation of RIS reflection efficiency. This paper proposes a frequency reflection modulation (FRM) method for RIS-aided OFDM systems. The FRM-OFDM scheme modulates the frequency of the incident electromagnetic waves, and the RIS information is embedded in the frequency-hoping states of RIS elements. Unlike the ORM-OFDM scheme, the FRM-OFDM scheme can achieve higher reflection efficiency, since the latter does not turn off any reflection element in reflection modulation. We propose a block coordinate descent (BCD) algorithm to maximize the user achievable rate for the FRM-OFDM system by jointly optimizing the phase shift of the RIS and the power allocation at the transmitter. Further, we design a bilinear message passing (BMP) algorithm for the bilinear recovery of both the user symbols and the RIS data. Numerical simulations have verified the efficiency of the designed BCD algorithm for system optimization and the BMP algorithm for signal detection, as well as the superiority of the proposed FRM-OFDM scheme over the ORM-OFDM scheme., Comment: 30 pages, 12 figures

Based on the connection between the categorical derivation of classical programs from specifications and the category-theoretic approach to quantum physics, this paper contributes to extending the laws of classical program algebra to quantum programming. This aims at building correct-by-construction quantum circuits to be deployed on quantum devices such as those available at the IBM Q Experience. Quantum circuit reversibility is ensured by minimal complements, extended recursively. Measurements are postponed to the end of such recursive computations, termed "quantamorphisms", thus maximising the quantum effect. Quantamorphisms are classical catamorphisms which, extended to ensure quantum reversibility, implement quantum cycles (vulg. for-loops) and quantum folds on lists. By Kleisli correspondence, quantamorphisms can be written as monadic functional programs with quantum parameters. This enables the use of Haskell, a monadic functional programming language, to perform the experimental work. Such calculated quantum programs prepared in Haskell are pushed through Quipper to the Qiskit interface to IBM Q quantum devices. The generated quantum circuits - often quite large - exhibit the predicted behaviour. However, running them on real quantum devices incurs into a significant amount of errors. As quantum devices are constantly evolving, an increase in reliability is likely in the near future, allowing for our programs to run more accurately., 18 pages

Advances in deep neural networks (DNNs) are transforming science and technology. However, the increasing computational demands of the most powerful DNNs limit deployment on low-power devices, such as smartphones and sensors – and this trend is accelerated by the simultaneous move towards Internet-of-Things (IoT) devices. Numerous efforts are underway to lower power consumption, but a fundamental bottleneck remains due to energy consumption in matrix algebra, even for analog approaches including neuromorphic, analog memory and photonic meshes. Here we introduce and demonstrate a new approach that sharply reduces energy required for matrix algebra by doing away with weight memory access on edge devices, enabling orders of magnitude energy and latency reduction. At the core of our approach is a new concept that decentralizes the DNN for delocalized, optically accelerated matrix algebra on edge devices. Using a silicon photonic smart transceiver, we demonstrate experimentally that this scheme, termed Netcast, dramatically reduces energy consumption. We demonstrate operation in a photon-starved environment with 40 aJ/multiply of optical energy for 98.8% accurate image recognition and

Networks of nanowires are currently being explored for a range of applications in brain-like (or neuromorphic) computing, and especially in reservoir computing (RC). Fabrication of real-world computing devices requires that the nanowires are deposited sequentially, leading to stacking of the wires on top of each other. However, most simulations of computational tasks using these systems treat the nanowires as 1D objects lying in a perfectly 2D plane - the effect of stacking on RC performance has not yet been established. Here we use detailed simulations to compare the performance of perfectly 2D and quasi-3D (stacked) networks of nanowires in two tasks: memory capacity and nonlinear transformation. We also show that our model of the junctions between nanowires is general enough to describe a wide range of memristive networks, and consider the impact of physically realistic electrode configurations on performance. We show that the various networks and configurations have a strikingly similar performance in RC tasks, which is surprising given their radically different topologies. Our results show that networks with an experimentally achievable number of electrodes perform close to the upper bounds achievable when using the information from every wire. However, we also show important differences, in particular that the quasi-3D networks are more resilient to changes in the input parameters, generalizing better to noisy training data. Since previous literature suggests that topology plays an important role in computing performance, these results may have important implications for future applications of nanowire networks in neuromorphic computing.

As state-of-the-art quantum computers are capable of running increasingly complex algorithms, the need for automated methods to design and test potential applications rises. Equivalence checking of quantum circuits is an important, yet hardly automated, task in the development of the quantum software stack. Recently, new methods have been proposed that tackle this problem from widely different perspectives. One of them is based on the ZX-calculus, a graphical rewriting system for quantum computing. However, the power and capability of this equivalence checking method has barely been explored. The aim of this work is to evaluate the ZX-calculus as a tool for equivalence checking of quantum circuits. To this end, it is demonstrated how the ZX-calculus based approach for equivalence checking can be expanded in order to verify the results of compilation flows and optimizations on quantum circuits. It is also shown that the ZX-calculus based method is not complete$\unicode{x2014}$especially for quantum circuits with ancillary qubits. In order to properly evaluate the proposed method, we conduct a detailed case study by comparing it to two other state-of-the-art methods for equivalence checking: one based on path-sums and another based on decision diagrams. The proposed methods have been integrated into the publicly available QCEC tool (https://github.com/cda-tum/qcec) which is part of the Munich Quantum Toolkit (MQT)., Comment: 15 pages, 12 figures, to be published in IEEE Journal on Emerging and Selected Topics in Circuits and Systems

As LEO/VLEO satellites offer many attractive features, such as low transmission delay, they are expected to be an integral part of 6G. Global entanglement distribution over LEO and VLEO satellites network must reckon with satellite movement over time. Current studies do not fully capture the dynamic nature of satellite constellations. We model a dynamic LEO/VLEO satellite network as a time-varying graph and construct a sequence of static graphs to represent a dynamic network. We study the entanglement distribution problem between a set of source-destination node pairs in this dynamic network utilizing Multi-commodity Flow (MCF). Solving MCF over a sequence of graphs independently for each graph may produce a completely different set of paths. Changing the set of paths every time the graph topology changes may involve a significant amount of overhead, as an established set of paths must be taken down and a new set of paths established. We propose a technique that will avoid this overhead by computing only one set of paths P to be used over all the graphs in the sequence. The degraded performance offered by P may be viewed as the cost of using P. The benefit of using P is the overhead cost of path switching that can be avoided. We provide a cost-benefit analysis in a LEO/VLEO constellation for entanglement distribution between multiple source-destination pairs. Our extensive experimentation shows that a significant amount of savings in overhead can be achieved if one is willing to accept a slightly degraded performance.

Neural decoders for quantum error correction (QEC) rely on neural networks to classify syndromes extracted from error correction codes and find appropriate recovery operators to protect logical information against errors. Despite the good performance of neural decoders, important practical requirements remain to be achieved, such as minimizing the decoding time to meet typical rates of syndrome generation in repeated error correction schemes, and ensuring the scalability of the decoding approach as the code distance increases. Designing a dedicated integrated circuit to perform the decoding task in co-integration with a quantum processor appears necessary to reach these decoding time and scalability requirements, as routing signals in and out of a cryogenic environment to be processed externally leads to unnecessary delays and an eventual wiring bottleneck. In this work, we report the design and performance analysis of a neural decoder inference accelerator based on an in-memory computing (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the decoder neural network and perform analog matrix-vector multiplications during inference. In proof-of-concept numerical experiments supported by experimental measurements, we investigate the impact of TiO$_\textrm{x}$-based memristive devices' non-idealities on decoding accuracy. Hardware-aware training methods are developed to mitigate the loss in accuracy, allowing the memristive neural decoders to achieve a pseudo-threshold of $9.23\times 10^{-4}$ for the distance-three surface code, whereas the equivalent digital neural decoder achieves a pseudo-threshold of $1.01\times 10^{-3}$. This work provides a pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated QEC.

Analog In-Memory Computing (AIMC) is a promising approach to reduce the latency and energy consumption of Deep Neural Network (DNN) inference and training. However, the noisy and non-linear device characteristics, and the non-ideal peripheral circuitry in AIMC chips, require adapting DNNs to be deployed on such hardware to achieve equivalent accuracy to digital computing. In this tutorial, we provide a deep dive into how such adaptations can be achieved and evaluated using the recently released IBM Analog Hardware Acceleration Kit (AIHWKit), freely available at https://github.com/IBM/aihwkit. The AIHWKit is a Python library that simulates inference and training of DNNs using AIMC. We present an in-depth description of the AIHWKit design, functionality, and best practices to properly perform inference and training. We also present an overview of the Analog AI Cloud Composer, that provides the benefits of using the AIHWKit simulation platform in a fully managed cloud setting. Finally, we show examples on how users can expand and customize AIHWKit for their own needs. This tutorial is accompanied by comprehensive Jupyter Notebook code examples that can be run using AIHWKit, which can be downloaded from https://github.com/IBM/aihwkit/tree/master/notebooks/tutorial.

Deep learning has fundamentally transformed artificial intelligence, but the ever-increasing complexity in deep learning models calls for specialized hardware accelerators. Optical accelerators can potentially offer enhanced performance, scalability, and energy efficiency. However, achieving nonlinear mapping, a critical component of neural networks, remains challenging optically. Here, we introduce a design that leverages multiple scattering in a reverberating cavity to passively induce optical nonlinear random mapping, without the need for additional laser power. A key advantage emerging from our work is that we show we can perform optical data compression, facilitated by multiple scattering in the cavity, to efficiently compress and retain vital information while also decreasing data dimensionality. This allows rapid optical information processing and generation of low dimensional mixtures of highly nonlinear features. These are particularly useful for applications demanding high-speed analysis and responses such as in edge computing devices. Utilizing rapid optical information processing capabilities, our optical platforms could potentially offer more efficient and real-time processing solutions for a broad range of applications. We demonstrate the efficacy of our design in improving computational performance across tasks, including classification, image reconstruction, key-point detection, and object detection, all achieved through optical data compression combined with a digital decoder. Notably, we observed high performance, at an extreme compression ratio, for real-time pedestrian detection. Our findings pave the way for novel algorithms and architectural designs for optical computing., 16 pages, 7 figures

This paper investigates the relationship between mapping style and device roadmap in Resistive Random Access Memory (ReRAM) architectures for neuromorphic computing. The study leverages simulations using DNN+NeuroSim to evaluate the impact of different parameters on chip performance, including latency, energy consumption, and overall system efficiency. The results demonstrate that novel mapping techniques and a high-performance (HP) device roadmap are optimal if energy and speed considerations are weighted equally. This is because as the study demonstrates, HP devices provide a latency cut that outsizes the energy cost. Additionally, adopting novel mapping in the device cuts latency by nearly 30% while being slightly more energy efficient. The findings highlight the importance of considering mapping style and device roadmap in optimizing ReRAM architectures for neuromorphic computing, which may contribute to advancing the practical implementation of ReRAM in computational systems.

Quantum neural networks (QNNs) succeed in object recognition, natural language processing, and financial analysis. To maximize the accuracy of a QNN on a Noisy Intermediate Scale Quantum (NISQ) computer, approximate synthesis modifies the QNN circuit by reducing error-prone 2-qubit quantum gates. The success of QNNs motivates adversaries to attack QNNs via backdoors. However, na\"ively transplanting backdoors designed for classical neural networks to QNNs yields only low attack success rate, due to the noises and approximate synthesis on NISQ computers. Prior quantum circuit-based backdoors cannot selectively attack some inputs or work with all types of encoding layers of a QNN circuit. Moreover, it is easy to detect both transplanted and circuit-based backdoors in a QNN. In this paper, we propose a novel and stealthy backdoor attack, QDoor, to achieve high attack success rate in approximately-synthesized QNN circuits by weaponizing unitary differences between uncompiled QNNs and their synthesized counterparts. QDoor trains a QNN behaving normally for all inputs with and without a trigger. However, after approximate synthesis, the QNN circuit always predicts any inputs with a trigger to a predefined class while still acts normally for benign inputs. Compared to prior backdoor attacks, QDoor improves the attack success rate by $13\times$ and the clean data accuracy by $65\%$ on average. Furthermore, prior backdoor detection techniques cannot find QDoor attacks in uncompiled QNN circuits.

Financial portfolio construction problems are often formulated as quadratic and discrete (combinatorial) optimization that belong to the nondeterministic polynomial time (NP)-hard class in computational complexity theory. Ising machines are hardware devices that work in quantum-mechanical/quantum-inspired principles for quickly solving NP-hard optimization problems, which potentially enable making trading decisions based on NP-hard optimization in the time constraints for high-speed trading strategies. Here we report a real-time stock trading system that determines long(buying)/short(selling) positions through NP-hard portfolio optimization for improving the Sharpe ratio using an embedded Ising machine based on a quantum-inspired algorithm called simulated bifurcation. The Ising machine selects a balanced (delta-neutral) group of stocks from an $N$-stock universe according to an objective function involving maximizing instantaneous expected returns defined as deviations from volume-weighted average prices and minimizing the summation of statistical correlation factors (for diversification). It has been demonstrated in the Tokyo Stock Exchange that the trading strategy based on NP-hard portfolio optimization for $N$=128 is executable with the FPGA (field-programmable gate array)-based trading system with a response latency of 164 $\mu$s., Comment: 12 pages, 5 figures. arXiv admin note: text overlap with arXiv:2307.05923

Training deep neural networks (DNNs) is computationally intensive but arrays of non-volatile memories like Charge Trap Flash (CTF) can accelerate DNN operations using in-memory computing. Specifically, the Resistive Processing Unit (RPU) architecture uses the voltage-threshold program by stochastic encoded pulse trains and analog memory features to accelerate vector-vector outer product and weight update for the gradient descent algorithms. Although CTF, offering high precision, has been regarded as an excellent choice for implementing RPU, the accumulation of charge due to the applied stochastic pulse trains is ultimately of critical significance in determining the final weight update. In this paper, we report the non-ideal program-time conservation in CTF through pulsing input measurements. We experimentally measure the effect of pulse width and pulse gap, keeping the total ON-time of the input pulse train constant, and report three non-idealities: (1) Cumulative V_T shift reduces when total ON-time is fragmented into a larger number of shorter pulses, (2) Cumulative V_T shift drops abruptly for pulse widths < 2 {\mu}s, (3) Cumulative V_T shift depends on the gap between consecutive pulses and the V_T shift reduction gets recovered for smaller gaps. We present an explanation based on a transient tunneling field enhancement due to blocking oxide trap-charge dynamics to explain these non-idealities. Identifying and modeling the responsible mechanisms and predicting their system-level effects during learning is critical. This non-ideal accumulation is expected to affect algorithms and architectures relying on devices for implementing mathematically equivalent functions for in-memory computing-based acceleration.

Pairs-trading is a trading strategy that involves matching a long position with a short position in two stocks aiming at market-neutral profits. While a typical pairs-trading system monitors the prices of two statistically correlated stocks for detecting a temporary divergence, monitoring and analyzing the prices of more stocks would potentially lead to finding more trading opportunities. Here we report a stock pairs-trading system that finds trading opportunities for any two stocks in an $N$-stock universe using a combinatorial optimization accelerator based on a quantum-inspired algorithm called simulated bifurcation. The trading opportunities are detected through solving an optimal path search problem in an $N$-node directed graph with edge weights corresponding to the products of instantaneous price differences and statistical correlation factors between two stocks. The accelerator is one of Ising machines and operates consecutively to find multiple opportunities in a market situation with avoiding duplicate detections by a tabu search technique. It has been demonstrated in the Tokyo Stock Exchange that the FPGA (field-programmable gate array)-based trading system has a sufficiently low latency (33 $\mu$s for $N$=15 or 210 pairs) to execute the pairs-trading strategy based on optimal path search in market graphs., Comment: 11 pages, 8 figures

In-memory computing (IMC) utilizing synaptic crossbar arrays is promising for deep neural networks to attain high energy efficiency and integration density. Towards that end, various CMOS and post-CMOS technologies have been explored as promising synaptic device candidates which include SRAM, ReRAM, FeFET, SOT-MRAM, etc. However, each of these technologies has its own pros and cons, which need to be comparatively evaluated in the context of synaptic array designs. For a fair comparison, such an analysis must carefully optimize each technology, specifically for synaptic crossbar design accounting for device and circuit non-idealities in crossbar arrays such as variations, wire resistance, driver/sink resistance, etc. In this work, we perform a comprehensive design space exploration and comparative evaluation of different technologies at 7nm technology node for synaptic crossbar arrays, in the context of IMC robustness and system accuracy. Firstly, we integrate different technologies into a cross-layer simulation flow based on physics-based models of synaptic devices and interconnects. Secondly, we optimize both technology-agnostic design knobs such as input encoding and ON-resistance as well as technology-specific design parameters including ferroelectric thickness in FeFET and MgO thickness in SOT-MRAM. Our optimization methodology accounts for the implications of device- and circuit-level non-idealities on the system-level accuracy for each technology. Finally, based on the optimized designs, we obtain inference results for ResNet-20 on CIFAR-10 dataset and show that FeFET-based crossbar arrays achieve the highest accuracy due to their compactness, low leakage and high ON/OFF current ratio.

Stochastic computing is a paradigm in which logical operations are performed on randomly generated bit streams. Complex arithmetic operations can be executed by simple logic circuits, resulting in a much smaller area footprint compared to conventional binary counterparts. However, the random or pseudorandom sources required for generating the bit streams are costly in terms of area and offset the advantages. Additionally, due to the inherent randomness, the computation lacks precision, limiting the applicability of this paradigm. Importantly, achieving reasonable accuracy in stochastic computing involves high latency. Recently, deterministic approaches to stochastic computing have been proposed, demonstrating that randomness is not a requirement. By structuring the computation deterministically, exact results can be obtained, and the latency greatly reduced. The bit stream generated adheres to a "unary" encoding, retaining the non-positional nature of the bits while discarding the random bit generation of traditional stochastic computing. This deterministic approach overcomes many drawbacks of stochastic computing, although the latency increases quadratically with each level of logic, becoming unmanageable beyond a few levels. In this paper, we present a method for approximating the results of the deterministic method while maintaining low latency at each level. This improvement comes at the cost of additional logic, but we demonstrate that the increase in area scales with the square root of n, where n represents the equivalent number of binary bits of precision. Our new approach is general, efficient, composable, and applicable to all arithmetic operations performed with stochastic logic. We show that this approach outperforms other stochastic designs for matrix multiplication (dot-product), which is an integral step in nearly all machine learning algorithms., 25 pages, 8 figures

In this paper, a hybrid non-orthogonal multiple access (NOMA) framework for the simultaneous transmitting and reflecting reconfigurable intelligent surface (STAR-RIS) enhanced cell-edge communication is investigated. Specifically, one transmitted user and one reflected user are paired as one NOMA-pair, while multiple NOMA-pairs are served via time division multiple access (TDMA). The objective is to maximize the minimum downlink rate by jointly optimizing the user pairing, decoding order, passive beamforming, power and time allocation. A novel two-layer iterative algorithm is proposed to solve the highly coupled problem. Simulation results show that: 1) the proposed framework outperforms the conventional reflecting-only-RIS-based and the OMA-based frameworks; 2) the beamforming design and power allocation dominate the achieved performance; 3) increasing the number of passive elements and shortening the distance between BS and STAR-RIS are two effective ways to further improve the performance.

Graph neural networks (GNNs) have emerged as a powerful approach for modelling and learning from graph-structured data. Multiple fields have since benefitted enormously from the capabilities of GNNs, such as recommendation systems, social network analysis, drug discovery, and robotics. However, accelerating and efficiently processing GNNs require a unique approach that goes beyond conventional artificial neural network accelerators, due to the substantial computational and memory requirements of GNNs. The slowdown of scaling in CMOS platforms also motivates a search for alternative implementation substrates. In this paper, we present GHOST, the first silicon-photonic hardware accelerator for GNNs. GHOST efficiently alleviates the costs associated with both vertex-centric and edge-centric operations. It implements separately the three main stages involved in running GNNs in the optical domain, allowing it to be used for the inference of various widely used GNN models and architectures, such as graph convolution networks and graph attention networks. Our simulation studies indicate that GHOST exhibits at least 10.2x better throughput and 3.8x better energy efficiency when compared to GPU, TPU, CPU and multiple state-of-the-art GNN hardware accelerators.

Crossbar-based PIM DNN accelerators can provide massively parallel in-situ operations. A specifically designed compiler is important to achieve high performance for a wide variety of DNN workloads. However, some key compilation issues such as parallelism considerations, weight replication selection, and array mapping methods have not been solved. In this work, we propose PIMCOMP - a universal compilation framework for NVM crossbar-based PIM DNN accelerators. PIMCOMP is built on an abstract PIM accelerator architecture, which is compatible with the widely used Crossbar/IMA/Tile/Chip hierarchy. On this basis, we propose four general compilation stages for crossbar-based PIM accelerators: node partitioning, weight replicating, core mapping, and dataflow scheduling. We design two compilation modes with different inter-layer pipeline granularities to support high-throughput and low-latency application scenarios, respectively. Our experimental results show that PIMCMOP yields improvements of 1.6$\times$ and 2.4$\times$ in throughput and latency, respectively, relative to PUMA.

Discrete chemical reaction networks formalize the interactions of molecular species in a well-mixed solution as stochastic events. Given their basic mathematical and physical role, the computational power of chemical reaction networks has been widely studied in the molecular programming and distributed computing communities. While for Turing-universal systems there is a universal measure of optimal information encoding based on Kolmogorov complexity, chemical reaction networks are not Turing universal unless error and unbounded molecular counts are permitted. Nonetheless, here we show that the optimal number of reactions to generate a specific count $x \in \mathbb{N}$ with probability $1$ is asymptotically equal to a ``space-aware'' version of the Kolmogorov complexity of $x$, defined as $\mathrm{\widetilde{K}s}(x) = \min_p\left\{\lvert p \rvert / \log \lvert p \rvert + \log(\texttt{space}(\mathcal{U}(p))) : \mathcal{U}(p) = x \right\}$, where $p$ is a program for universal Turing machine $\mathcal{U}$. This version of Kolmogorov complexity incorporates not just the length of the shortest program for generating $x$, but also the space usage of that program. Probability $1$ computation is captured by the standard notion of stable computation from distributed computing, but we limit our consideration to chemical reaction networks obeying a stronger constraint: they ``know when they are done'' in the sense that they produce a special species to indicate completion. As part of our results, we develop a module for encoding and unpacking any $b$ bits of information via $O(b/\log{b})$ reactions, which is information-theoretically optimal for incompressible information. Our work provides one answer to the question of how succinctly chemical self-organization can be encoded -- in the sense of generating precise molecular counts of species as the desired state.

Alternative computing paradigms open the door to exploiting recent innovations in computational hardware. Dynamical computing is one such paradigm that synthesizes momentum computing -- an extremely energy-efficient design framework -- with nanoscale thermodynamic computing. This synthesis can be implemented with Josephson junction technology, giving a testbed with tunable coupling to a thermal environment. Investigating the dynamics and thermodynamics of these superconducting quantum interference devices (SQUIDs), though, requires (i) constructing physically-realizable superconducting circuits, (ii) thoroughly understanding circuit energetics, and (iii) designing sufficiently complex circuits that support a suite of useful operations. First-principle circuit design leads to prohibitive algebraic complications that to-date precluded achieving these goals quickly and efficiently. We circumvent these complications by (i) specializing our class of circuits and operating regime, (ii) synthesizing existing methods to suit these specializations, and (iii) implementing solution-finding optimizations that facilitate physically interpreting circuit degrees of freedom and that respect physically-grounded constraints. Practically, this leads to efficient circuit prototyping and analysis and access to scalable circuit architectures. The analytical efficiency is demonstrated by directly reproducing the thermodynamic potential induced by the variable $\beta$ rf (v$\beta$-rf) SQUID. We then show how inductively couple two v$\beta$-rf SQUIDs yielding a device capable of performing 2-bit computations. The methods detailed here provide a basis to construct universal logic gates and investigate their thermodynamic performance., Comment: 8 pages, 3 figures; https://csc.ucdavis.edu/~cmg/compmech/pubs/nds.htm

As the number of devices being interconnected increases, so does also the demand for (lightweight) security. To this end, Physical Unclonable Functions (PUFs) have been proposed as hardware primitives that can act as roots of trust and security. Recently, a new type of PUF based on Carbon NanoTubes (CNTs) has been proposed. At the same time, attacks and testing based on direct electrical probing appear to be moving towards non-invasive techniques. In this context, this work attempts to examine the potential for practical non-invasive probing attacks against the CNT-PUF, a novel PUF based on CNTs. Our results indicate that direct probing might potentially compromise the security of this PUF. Nevertheless, we note that this holds true only in the case that the attacker can directly probe the wire corresponding to the secret value of each CNT-PUF cell. Thus, we can conclude that the examined CNT-PUFs are rather resilient to direct probing attacks, that non-invasive probing methods appear to be promising for testing such PUFs, and that, in order for the attacker to gain the full-length value of the secret, all the relevant channels would need to be probed. Nevertheless, as our work proves, practical non-invasive attacks against the CNT-PUF are feasible and adequate countermeasures need to be employed in order to address this issue.

DNA has been discussed as a potential medium for data storage. Potentially it could be denser, could consume less energy, and could be more durable than conventional storage media such as hard drives, solid-state storage, and optical media. However, computing on data stored in DNA is a largely unexplored challenge. This paper proposes an integrated circuit (IC) based on microfluidics that can perform complex operations such as artificial neural network (ANN) computation on data stored in DNA. It computes entirely in the molecular domain without converting data to electrical form, making it a form of in-memory computing on DNA. The computation is achieved by topologically modifying DNA strands through the use of enzymes called nickases. A novel scheme is proposed for representing data stochastically through the concentration of the DNA molecules that are nicked at specific sites. The paper provides details of the biochemical design, as well as the design, layout, and operation of the microfluidics device. Benchmarks are reported on the performance of neural network computation., 24 pages, 11 figures

We demonstrate non-volatile optical functionality by embedding multi-layer $HfO_2/Al_2O_3$ memristors with III-V/Si photonics. The wafer-bonded III-V/Si memristor facilitates non-volatile optical functionality for a variety of devices such as Mach-Zehnder Interferometers (MZIs), and (de-)interleaver filters. The MZI optical memristor exhibits non-volatile optical phase shifts $> \pi (\Delta n_{g} > 2.70 \times 10^{-3}$) with ~ 30 dB extinction ratio while consuming 0 electrical power consumption in a true "set-and-forget" operation. We demonstrate 6 non-volatile states with each state capable of 4 Gbps modulation. III-V/Si (de-)interleavers were also demonstrated to exhibit memristive non-volatile passband transformation with full set/reset states. Time duration tests were performed on all devices and indicated non-volatility up to 24 hours and most likely beyond. To the best of our knowledge, we have demonstrated for the first time, non-volatile III-V/Si optical memristors with the largest electric-field driven phase shifts and reconfigurable filters with the lowest power consumption., Comment: arXiv admin note: substantial text overlap with arXiv:2305.17578

Recent trends in deep learning (DL) imposed hardware accelerators as the most viable solution for several classes of high-performance computing (HPC) applications such as image classification, computer vision, and speech recognition. This survey summarizes and classifies the most recent advances in designing DL accelerators suitable to reach the performance requirements of HPC applications. In particular, it highlights the most advanced approaches to support deep learning accelerations including not only GPU and TPU-based accelerators but also design-specific hardware accelerators such as FPGA-based and ASIC-based accelerators, Neural Processing Units, open hardware RISC-V-based accelerators and co-processors. The survey also describes accelerators based on emerging memory technologies and computing paradigms, such as 3D-stacked Processor-In-Memory, non-volatile memories (mainly, Resistive RAM and Phase Change Memories) to implement in-memory computing, Neuromorphic Processing Units, and accelerators based on Multi-Chip Modules. The survey classifies the most influential architectures and technologies proposed in the last years, with the purpose of offering the reader a comprehensive perspective in the rapidly evolving field of deep learning. Finally, it provides some insights into future challenges in DL accelerators such as quantum accelerators and photonics., Preprint version of our manuscript submitted to the journal @ ACM CSUR (35 pages plus Appendix) on June 22nd, 2023

The fidelity of quantum programs in the NISQ era is limited by high levels of device noise. To increase the fidelity of quantum programs running on NISQ devices, a variety of optimizations have been proposed. These include mapping passes, routing passes, scheduling methods and standalone optimisations which are usually incorporated into a transpiler as passes. Popular transpilers such as those proposed by Qiskit, Cirq and Cambridge Quantum Computing make use of these extensively. However, choosing the right set of transpiler passes and the right configuration for each pass is a challenging problem. Transpilers often make critical decisions using heuristics since the ideal choices are impossible to identify without knowing the target application outcome. Further, the transpiler also makes simplifying assumptions about device noise that often do not hold in the real world. As a result, we often see effects where the fidelity of a target application decreases despite using state-of-the-art optimisations. To overcome this challenge, we propose OPTRAN, a framework for Choosing an Optimal Pass Set for Quantum Transpilation. OPTRAN uses classically simulable quantum circuits composed entirely of Clifford gates, that resemble the target application, to estimate how different passes interact with each other in the context of the target application. OPTRAN then uses this information to choose the optimal combination of passes that maximizes the target application's fidelity when run on the actual device. Our experiments on IBM machines show that OPTRAN improves fidelity by 87.66% of the maximum possible limit over the baseline used by IBM Qiskit. We also propose low-cost variants of OPTRAN, called OPTRAN-E-3 and OPTRAN-E-1 that improve fidelity by 78.33% and 76.66% of the maximum permissible limit over the baseline at a 58.33% and 69.44% reduction in cost compared to OPTRAN respectively.

Monolithic 3D integration has become a promising solution for future computing needs. The metal inter-layer via (MIV) forms interconnects between substrate layers in Monolithic 3D integration. Despite small size of MIV, the area overhead can become a major limitation for efficient M3D integration and, thus needs to be addressed. Previous works focused on the utilization of the substrate area around MIV to reduce this area overhead significantly but suffers from increased leakage and scaling factors. In this work, we discuss MIV-transistor realization that addresses both leakage and scaling issue along with similar area overhead reduction compared with previous works and, thus can be utilized efficiently. Our simulation results suggest that the leakage current $(I_{D,leak})$ has reduced by $14K\times$ and, the maximum current $(I_{D,max})$ increased by $58\%$ for the proposed MIV-transistor compared with the previous implementation. In addition, performance metrics of the inverter realization with our proposed MIV-transistor specifically the delay, slew time and power consumption reduced by $11.6\%$, $17.9\%$ and, $4.5\%$ respectively compared with the previous implementation with same MIV area overhead reduction., The paper has been accepted to MWSCAS 2023

Synapse is a key element of any neuromorphic computing system which is mostly constructed with memristor devices. A memristor is a two-terminal analog memory device. Memristive synapse suffers from various challenges such as forming at high voltage, SET, RESET failure, and READ margin or resolution issue between two weights. Enhanced READ resolution is very important to make a memristive synapse functionally reliable. Usually, the READ resolution is very small for a memristive synapse with 4-bit data precision. This work considers a step-by-step analysis to enhance the READ current resolution for a current-controlled memristor-based synapse. An empirical model is used to characterize the HfO2-based memristive device. 1st and 2nd stage device of our proposed synapse can be scaled to enhance the READ current margin up to ~ 4.3x and ~ 21% respectively. Moreover, READ current resolution can be enhanced with run-time adaptation features such as READ voltage scaling and body biasing. The READ voltage scaling and body biasing can improve the READ current resolution by about 46% and 15% respectively. TENNLabs' neuromorphic computing framework is leveraged to evaluate the effect of READ current resolution on classification applications. Higher READ current resolution shows better accuracy than lower resolution with different percentages of read noise scenarios.

In recent times, neural networks have been gaining increasing importance in fields such as pattern recognition and computer vision. However, their usage entails significant energy and hardware costs, limiting the domains in which this technology can be employed. In this context, the feasibility of utilizing analog circuits based on memristors as efficient alternatives in neural network inference is being considered. Memristors stand out for their configurability and low power consumption. To study the feasibility of using these circuits, a physical model has been adapted to accurately simulate the behavior of commercial memristors from KNOWM. Using this model, multiple neural networks have been designed and simulated, yielding highly satisfactory results.

Convolutional neural networks (CNNs) are representative models of artificial neural networks (ANNs), that form the backbone of modern computer vision. However, the considerable power consumption and limited computing speed of electrical computing platforms restrict further development of CNNs. Optical neural networks are considered the next-generation physical implementations of ANNs to break the bottleneck. This study proposes a spectral convolutional neural network (SCNN) with the function of matter meta-imaging, namely identifying the composition of matter and mapping its distribution in space. This SCNN includes an optical convolutional layer (OCL) and a reconfigurable electrical backend. The OCL is implemented by integrating very large-scale, pixel-aligned metasurfaces on a CMOS image sensor, which accepts 3D raw datacubes of natural images, containing two-spatial and one-spectral dimensions, at megapixels directly as input to realize the matter meta-imaging. This unique optoelectronic framework empowers in-sensor optical analog computing at extremely high energy efficiency eliminating the need for coherent light sources and greatly reducing the computing load of the electrical backend. We employed the SCNN framework on several real-world complex tasks. It achieved accuracies of 96.4% and 100% for pathological diagnosis and real-time face anti-spoofing at video rate, respectively. The SCNN framework, with an unprecedented new function of substance identification, provides a feasible optoelectronic and integrated optical CNN implementation for edge devices or cellphones with limited computing capabilities, facilitating diverse applications, such as intelligent robotics, industrial automation, medical diagnosis, and astronomy.

Gradient descent-based backpropagation training is widely used in many neural network systems. However, photonic implementation of such method is not straightforward mainly since having both the nonlinear activation function and its gradient using standard integrated photonic components is challenging. Here, we demonstrate the realization of two commonly used neural nonlinear activation functions and their gradients on a silicon photonic platform. Our method leverages the nonlinear electro-optic response of a micro-disk modulator. As a proof of concept, the experimental results are incorporated into a neural network simulation platform to classify MNIST handwritten digits dataset where we classification accuracies of more than 97\% are achieved that are on par with those of ideal nonlinearities and gradients.

Superconducting electronics are among the most promising alternatives to conventional CMOS technology thanks to the ultra-fast speed and ultra-high energy efficiency of the superconducting devices. Having a cryogenic control processor is also a crucial requirement for scaling the existing quantum computers up to thousands of qubits. Despite showing outstanding speed and energy efficiency, Josephson junction-based circuits suffer from several challenges such as flux trapping leading to limited scalability, difficulty in driving high impedances, and so on. Three-terminal cryotron devices have been proposed to solve these issues which can drive high impedances (>100 k{\Omega}) and are free from any flux trapping issue. In this work, we develop a reconfigurable logic circuit using a heater cryotron (hTron). In conventional approaches, the number of devices to perform a logic operation typically increases with the number of inputs. However, here, we demonstrate a single hTron device-based logic circuit that can be reconfigured to perform 1-input copy and NOT, 2-input AND and OR, and 3-input majority logic operations by choosing suitable biasing conditions. Consequently, we can perform any processing task with a much smaller number of devices. Also, since we can perform different logic operations with the same circuit (same layout), we can develop a camouflaged system where all the logic gates will have the same layout. Therefore, this proposed circuit will ensure enhanced hardware security against reverse engineering attacks., Comment: 12 pages, 5 figures