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Increasingly, durable goods have embedded software and are technologically tethered to the vendor's server through this software, be it digital products such as smartphones or predominantly non-digital products such as automobiles and tractors. Tethering can enable the vendor to change the product's performance or features through software updates, with implications for optimal product policy. We study a monopolist technology vendor's decision to partially degrade or fully retire their installed base of tethered goods when they release their newer version. Our work presents several novel theoretical contributions with practical implications for industry. Installed base degradation can emerge in equilibrium. To obsolete the previous version, it is no longer necessary for the seller to produce an improved version. Firms may engage in economically suboptimal partial degradation for technical reasons. Firms sometimes engage in suboptimal product obsolescence despite it harming their profit, due to their inability to commit to a no-obsolescence policy. Under some conditions the seller's commitment problem could cause them to offer excessive durability. Our work suggests important policy guidelines: when releasing new models, firms should consider releasing updated versions of their older operating systems, and allow existing customers to opt out of significant software upgrades, other than essential security patches. [ABSTRACT FROM AUTHOR]

Copyright of e & i Elektrotechnik und Informationstechnik is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The cybertronics challenges evolve around the complexity of systems and increase in detail and data involved. Existing methods and tools can master some of the rising challenges, but a method being able to handle the challenges was not introduced yet. MBSE is a potential approach to solve these problems, but the available methods were developed for modeling physical systems and software, not cybertronics. Because of the diversity of implementation domains participating in cybertronics systems, the modeling methodology must support the holistic management of requirements, properties, and design data. This paper introduces some promising emerging technologies like Arcadia, SysML V2, SysMD and PMM, that have the potential to interact with other methods and tools, closing the gaps in requirements tracing, system modeling, documentation, and verification. One potential methodology is introduced through a design example from requirements to implementation interface. [ABSTRACT FROM AUTHOR]

The procedures used to create modern cars require extensive thought in various relevant scientific domains. Arguably, the most challenging obstacle facing the automobile sector is the management of production facilities by integrating software production lines, continuous integration, and continuous delivery/continuous deployment (CI/CD). All this is determined by market demands, the engine of a vehicle, and the complexity of assembling the entire car and installing its corresponding embedded software. As a result, concerns about various types of global change have grown, as has the lack of the ability to use fossil fuels, creating a substantial impact on the purchase and sale of modern automobiles. The research foundation is reflected in covering strategies for the deployment and administration of software, as well as opportunities for business improvement in particular production processes. This article strives to provide a summary of a scientific investigation of original equipment manufacturers, market segmentation, and the effects of global market changes on automotive manufacturing by examining the correlation between certain changes in the purchase of a specific brand and the powertrain of a vehicle. The research examines numerous datasets from the United States of America and Washington State, based on which we estimate possible future changes in the automotive industry's sales. [ABSTRACT FROM AUTHOR]

Machine learning models play a crucial role in sports monitoring by effectively identifying various activities and tracking the number of repetitions during repetitive movements. However, creating models that accurately detect different types of exercises and provide feedback on movement adjustments for wearable devices remains a challenge. In this letter, we propose an alternative approach that addresses this issue by using the restricted Boltzmann machine (RBM) algorithm to learn, evaluate, and provide adjustment feedback based on inertial sensor data in real-time. Our experimental results show that by evaluating body segments individually, highly specialized models can be generated from a small set of movement repetitions. Moreover, these models have the capability to offer users precise recommendations on how to fine-tune the intensity, acceleration, and amplitude of the monitored segment. By using our proposed method, there is a great potential to enhance the accuracy and effectiveness of wearable devices used for sports monitoring. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Hardware faults are a known source of security vulnerabilities. Fault injection in secure embedded systems leads to information leakage and privilege escalation, and countless fault attacks have been demonstrated both in simulation and in practice. However, there is a significant gap between simulated fault attacks and physical fault attacks. Simulations use idealized fault models such as single-bit flips with uniform distribution. These ideal fault models may not hold in practice. On the other hand, practical experiments lack the white-box visibility necessary to determine the true nature of the fault, leading to probabilistic vulnerability assessments and unexplained results. In embedded software, this problem is further exacerbated by the layered abstractions between the hardware (where the fault originates) and the application software (where the fault effect is observed). We present FaultDetective, a method to investigate the root-cause of fault injection from fault detection in software. Our main insight is that fault detection in software is only the end-point of a chain of events that starts with a fault manifestation in hardware and propagates through the micro-architecture and architecture before reaching the software level. To understand the fault effects at the hardware level, we use a scan chain, a low-level hardware test structure. We then use white-box simulation to propagate and observe hardware faults in the embedded software. We efficiently visualize the fault propagation across abstraction levels using a hash-tree representation of the scan chain. We implement this concept in a multi-core MSP430 micro-controller that redundantly executes an application in lock-step. With this setup, we observe the fault effects for several different stressors, including clock glitching and thermal laser stimulation, and explain the root-cause in each case.

Embedded software quality is a critical concern in modern engineering, impacting a broad range of applications from spacecraft to complex control systems. Requirements engineering and software maintenance play pivotal roles in ensuring the high reliability and efficiency of embedded systems. This study contributes to the field by presenting a systematic literature review that comprehensively explores existing research on embedded software requirements engineering and maintenance methods. Through the established systematic review process, a thorough analysis of the research trends of methods used for different requirements engineering and maintenance activities was conducted on 79 primary studies. Moreover, the review emphasizes the significance of research on automation techniques and discusses the current status of the application of artificial intelligence and machine learning techniques for both domains. This review serves as a valuable resource for researchers and practitioners by addressing the challenges of limited research in certain domains and pointing to future research directions. Overall, this systematic literature review provides insights into future research prospects in the embedded software requirements engineering and maintenance domain for improved reliability.

Modern means of information exchange are mostly built as systems with. The process of functioning of such systems consists in the interaction of software and hardware components. The architecture of such systems corresponds to the Open System Interconnection Basic Reference Model (OSI), which defines certain levels in networks, gives them standard names and indicates what functions each level should perform. Violations of the functioning of such systems can be caused by random failures and defects of the hardware component, errors and failures of the software, or as a result of external influence. The complexity of assessing the technical condition (technical diagnosis) is due to the significant territorial diversity of the system elements, the variety of functional nodes and specifications of the equipment, as well as the use of dual-purpose equipment in the systems. Given the complexity of the selected object, the task of automating control is entrusted to computer-measurement systems. Analysis of the architecture of the selected object of control (availability of formalized - standardized levels) allows to offer solutions to technical diagnostics tasks (or physical integrity control tasks) through step-by-step (step-by-step) testing of individual levels of hardware and technical means. The presented verification technique is based on organizational measures (availability of daily monitoring of functioning) and the use of standardized sets of protocols of each level of the OSI model. At the same time, at each stage of the check, two components of the diagnostic parameter (time and energy) are registered. The availability of mathematical models of the aging processes of the hardware part and the physical data transmission environment made it possible to obtain reference values for the diagnostic parameter at any time of the operation of the control object, or to determine the change of the main parameters when modeling the behavior of the system for a certain time. The set of numerical values of both components of the diagnostic parameter allows to determine the technical condition of not only the hardware part of the control object and the correct functioning of the software part at different levels of the OSI model, but also the presence (or absence) of unauthorized influence (software or hardware) in the system. [ABSTRACT FROM AUTHOR]

In real-time systems, it is essential to verify the end-to-end constraints that regulate the external input/output (I/O) semantics of the head and tail tasks in each effect chain during the design phase and preserve them during implementation. The logical execution time (LET) model has been adopted by the industry due to the predictability and composability of its timed behavior. However, during the execution of LET-based effect chains, there are ineffective jobs whose outputs are redundant or unused and do not contribute to the external I/O behavior. This letter proposes an offline optimization method for deriving multiframe tasks that achieve the external timed I/O semantics of the LET-based effect chains with reduced utilization. The method first removes ineffective jobs from each effect chain and further explores the benefits of removing jobs for single and crossing effect chains by loosening the LET interval. The method is evaluated using synthetic benchmarks that mimic real-world automotive applications. [ABSTRACT FROM AUTHOR]

Typical training procedures involve read and write operations for weight updates during backpropagation. However, on-device training on microcontroller units (MCUs) presents two challenges. First, the on-chip SRAM has insufficient capacity to store the weight. Second, the large flash memory, which has a constraint on write access, becomes necessary to accommodate the network for on-device training on MCUs. To tackle these memory constraints, we propose a partial weight update technique based on gradient delta computation. The weights are stored in flash memory, and a part of the weight to be updated is selectively copied to the SRAM from the flash memory. We implemented this approach for training a fully connected network on an on-device MNIST digit classification task using only 20-kB SRAM and 1912-kB flash memory on an MCU. The proposed technique achieves reasonable accuracy with only 18.52% partial weight updates, which is comparable to state-of-the-art results. Furthermore, we achieved a reduction of up to 46.9% in the area-power-delay product compared to a commercially available high-performance MCU capable of embedding the entire model parameter, taking into account the area scale factor. [ABSTRACT FROM AUTHOR]

There are various tools for real-time data acquisition and analysis of high-frequency signals. Usually, the tools for data acquisition and analysis are incompatible with each other, expensive, or require the utilization of various technologies. Designing a unique toolset for real-time data acquisition and analysis of high-frequency signals presents a large challenge, both in terms of hardware and software design. Some of the main challenges include fulfilling strict real-time performance requirements, using cost-effective hardware components, and designing a software architecture with minimal software latency for data sampling on an embedded platform and data analysis on a PC machine. This paper presents a software architecture design methodology for embedded platforms, including an RTOS and an Ethernet interface, along with the application architecture on the host side. To demonstrate the advantages of the proposed methodology, a prototype consisting of the STM32H747 microcontroller, FreeRTOS operating system, and a GUI application based on the Qt framework has been created. It has been shown that using the proposed architecture design methodology makes it possible to preserve the maximal hardware sampling rate utilizing a 100 Mbps Ethernet link. In the experiments, sampling rates up to 4.57 MSps for 10-bit resolution and real-time transfer of data over Ethernet link and visualization on host PC have been achieved with this specific MCU. [ABSTRACT FROM AUTHOR]

Scade is a domain-specific synchronous functional language used to implement safety-critical real-time software for more than twenty years. Two main approaches have been considered for its semantics: (i) an indirect collapsing semantics based on a source-to-source translation of high-level constructs into a data-flow core language whose semantics is precisely specified and is the entry for code generation; a relational synchronous semantics, akin to Esterel, that applies directly to the source. It defines what is a valid synchronous reaction but hides, on purpose, if a semantics exists, is unique and can be computed; hence, it is not executable. This paper presents, for the first time, an executable, state-based semantics for a language that has the key constructs of Scade all together, in particular the arbitrary combination of data-flow equations and hierarchical state machines. It can apply directly to the source language before static checks and compilation steps. It is constructive in the sense that the language in which the semantics is defined is a statically typed functional language with call-by-value and strong normalization, e.g., it is expressible in a proof-assistant where all functions terminate. It leads to a reference, purely functional, interpreter. This semantics is modular and can account for possible errors, allowing to establish what property is ensured by each static verification performed by the compiler. It also clarifies how causality is treated in Scade compared with Esterel. This semantics can serve as an oracle for compiler testing and validation; to prototype novel language constructs before they are implemented, to execute possibly unfinishedmodels or that are correct but rejected by the compiler; to prove the correctness of compilation steps. The semantics given in the paper is implemented as an interpreter in a purely functional style, in OCaml. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Hearing loss is a common problem affecting the quality of life for thousands of people. However, many individuals with hearing loss are dissatisfied with the quality of modern hearing aids. Amplification is the main method of compensating for hearing loss in modern hearing aids. One common amplification technique is dynamic range compression, which maps audio signals onto a person's hearing range using an amplification curve. However, due to the frequency dependent nature of the human cochlea, compression is often performed independently in different frequency bands. This paper presents a real-time multirate multiband amplification system for hearing aids, which includes a multirate channelizer for separating an audio signal into eleven standard audiometric frequency bands, and an automatic gain control system for accurate control of the steady state and dynamic behavior of audio compression as specified by ANSI standards. The spectral channelizer offers high frequency resolution with low latency of 5.4 ms and about 14× improvement in complexity over a baseline design. Our automatic gain control includes a closed-form solution for satisfying any designated attack and release times for any desired compression parameters. The increased frequency resolution and precise gain adjustment allow our system to more accurately fulfill audiometric hearing aid prescriptions.

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

We present WEARDA, the open source WEARable sensor Data Acquisition software package. WEARDA facilitates the acquisition of human activity data with smartwatches and is primarily aimed at researchers who require transparency, full control, and access to raw sensor data. It provides functionality to simultaneously record raw data from four sensors--tri-axis accelerometer, tri-axis gyroscope, barometer, and GPS--which should enable researchers to, for example, estimate energy expenditure and mine movement trajectories. A Samsung smartwatch running the Tizen OS was chosen because of 1) the required functionalities of the smartwatch software API, 2) the availability of software development tools and accessible documentation, 3) having the required sensors, and 4) the requirements on case design for acceptance by the target user group. WEARDA addresses five practical challenges concerning preparation, measurement, logistics, privacy preservation, and reproducibility to ensure efficient and errorless data collection. The software package was initially created for the project "Dementia back at the heart of the community",2 and has been successfully used in that context. [ABSTRACT FROM AUTHOR]

We present WEARDA,1 the open source WEARable sensor Data Acquisition software package. WEARDA facilitates the acquisition of human activity data with smartwatches and is primarily aimed at researchers who require transparency, full control, and access to raw sensor data. It provides functionality to simultaneously record raw data from four sensors—tri-axis accelerometer, tri-axis gyroscope, barometer, and GPS—which should enable researchers to, for example, estimate energy expenditure and mine movement trajectories. A Samsung smartwatch running the Tizen OS was chosen because of 1) the required functionalities of the smartwatch software API, 2) the availability of software development tools and accessible documentation, 3) having the required sensors, and 4) the requirements on case design for acceptance by the target user group. WEARDA addresses five practical challenges concerning preparation, measurement, logistics, privacy preservation, and reproducibility to ensure efficient and errorless data collection. The software package was initially created for the project “Dementia back at the heart of the community”,2 and has been successfully used in that context.

Hearing loss is one of the most common conditions affecting older adults worldwide. Frequent complaints from the users of modern hearing aids include poor speech intelligibility in noisy environments and high cost, among other issues. However, the signal processing and audiological research needed to address these problems has long been hampered by proprietary development systems, underpowered embedded processors, and the difficulty of performing tests in real-world acoustical environments. To facilitate existing research in hearing healthcare and enable new investigations beyond what is currently possible, we have developed a modern, open-source hearing research platform, Open Speech Platform (OSP). This paper presents the system design of the complete OSP wearable platform, from hardware through firmware and software to user applications. The platform provides a complete suite of basic and advanced hearing aid features which can be adapted by researchers. It serves web apps directly from a hotspot on the wearable hardware, enabling users and researchers to control the system in real time. In addition, it can simultaneously acquire high-quality electroencephalography (EEG) or other electrophysiological signals closely synchronized to the audio. All of these features are provided in a wearable form factor with enough battery life for hours of operation in the field.

Internet of things (IoT) devices are mostly ubiquitous in this day and age, and it is hard to imagine a life without them, especially in the productive sectors (industry, agriculture, and automotive) and in our daily life activities (consumer electronics, home automation, and intelligent buildings). The high demand for these devices has created significant competition to provide them at the best price, at the right time, and with the best features. The trend in which these devices have increased their product features has resulted in their embedded software being more complex, leading to extended development and testing times. Consequently, as the types of advanced IoT products keep diversifying, the field maintenance of all the different models deployed grows more complicated. This paper proposes an embedded software development framework for IoT devices independent of the microcontroller architecture, the compiler, and the development environment. This framework allows having a common software baseline between different projects, which shortens the learning curve, development time, and module validation while allowing code reuse for embedded software professionals. A proof-of-concept evaluation is also presented to demonstrate the efficiency and reliability of the obtained embedded software code for a simple but representative IoT application. [ABSTRACT FROM AUTHOR]

Energy harvesting is increasingly used as a long-term energy supply for the Internet of Things, wireless sensor networks, and cyber-physical systems. However, the challenge of mitigating the variability of energy harvesting sources needs to be addressed before ubiquitous adoption can happen. Otherwise, an unreliable operation of devices with frequent shutdowns during times of energy scarcity would be encountered. One finds probabilistic performance metrics helpful in designing power management solutions for the long-term operation of energy harvesting nodes. These metrics include the probability of battery depletion, expected energy consumption, expected battery level, and similar. This article proposes a stochastic modeling technique and corresponding analysis which can provide such metrics. Our advanced analysis is based on Markov chains. By modeling harvested energy with random variables, new and existing energy management policies are analyzed and compared. We propose an adaptive energy management strategy inspired by mixed-criticality systems. In the proposed strategy, the system can degrade or drop less essential tasks in real time to ensure a graceful degradation of service in adverse harvesting conditions. We compare the proposed energy management approach to several existing alternatives. To this end, we conduct extensive simulations for indoor and outdoor environments, where our strategy matches or outperforms the state of the art. Initial results also validate the high precision of our stochastic model and analysis in comparison to simulations using real-world data. [ABSTRACT FROM AUTHOR]

Simulink is a widely used model-driven design environment for supporting the simulation and code generation of embedded applications. To improve the quality of the code generated from Simulink models, state-of-the-art code generators employ various high-level optimizations, like eliminating local variables. However, they overlook the compatibility between code and the low-level processor architecture, especially the instruction pipeline. Consequently, instruction pipeline stalls occur frequently, leading to additional delays in instruction execution, as well as limited efficiency for deployed the embedded software. In this article, we propose Mercury, an instruction pipeline aware code generator for Simulink models which utilizes data dependencies between actors to decrease the instruction pipeline stalls of the generated code. First, Mercury collects data dependencies through model dataflow traversal and records the property of each actor. Then, Mercury approximately estimates the execution latency of required instructions fetched from corresponding actors and uses a topology-based method to obtain candidate actors for code synthesis. Finally, Mercury adopts the least penalty priority to iteratively select the most suitable actor for code synthesis and releases data dependencies with its subsequent actors. We implemented and evaluated Mercury on benchmark Simulink models (Su et al., 2021) as well as a real industrial model. Compared to the official tool Simulink Embedded Coder and the state-of-the-art academic tool DFSynth, Mercury outperformed them by 9.7%–33.4% and 9.2%–59.4% in terms of the execution time of the generated code across different architectures, respectively. The statistics also demonstrate that the generated code of Mercury increases utilization of pipeline slots by 11.0%–37.1% and 10.6%–50.0%, respectively. [ABSTRACT FROM AUTHOR]

Recent research showcased several cyber-attacks against unmodified licensed vehicles, demonstrating the vulnerability of their internal networks. Many solutions have already been proposed by industry and academia, aiming to detect and prevent cyber-attacks targeting in-vehicle networks. The majority of these proposals borrow security algorithms and techniques from the classical ICT domain, and in many cases they do not consider the inherent limitations of legacy automotive protocols and resource-constrained microcontrollers. This paper proposes DAGA, an anomaly detection algorithm for in-vehicle networks exploiting $n-$ gram analysis. DAGA only uses sequences of CAN message IDs for the definition of the $n-$ grams used in the detection process, without requiring the content of the payload or other CAN message fields. The DAGA framework allows the creation of detection models characterized by different memory footprints, allowing their deployment on microcontrollers with different hardware constraints. Experimental results based on three prototype implementations of DAGA showcase the trade off between hardware requirements and detection performance. DAGA outperforms the state-of-the-art detectors on the most performing microcontrollers, and can execute with lower performance on simple microcontrollers that cannot support the vast majority of IDS approaches proposed in literature. As additional contributions, we publicly release the full dataset and our reference DAGA implementations. [ABSTRACT FROM AUTHOR]

In recent years, since edge computing has become more and more popular, its security issues have become apparent and have received unprecedented attention. Thus, the current research concentrates on security not only regarding devices such as PCs, smartphones, tablets, and IoTs, but also the automobile industry. However, since attack vectors have become more sophisticated than ever, we cannot just protect the zone above the system software layer in a certain operating system, such as Linux, for example. In addition, the challenges in IoT devices, such as power consumption, performance efficiency, and authentication management, still need to be solved. Since most IoT devices are controlled remotely, the security regarding system maintenance and upgrades has become a big issue. Therefore, a mechanism that can maintain IoT devices within a trusted environment based on localhost or over-the-air (OTA) will be a viable solution. We propose a mechanism called STBEAT, integrating an open-source project with ARM TrustZone to solve the challenges of upgrading the IoT system and updating system files more safely. This paper focuses on the ARMv7 architecture and utilizes the security stack from TrustZone to OP-TEE under the STM32 board package, and finally obtains the security key from the trusted application, which is used to conduct the cryptographic operations and then install the newer image on the MMC interface. To sum up, we propose a novel software update strategy and integrated ARM TrustZone security extension to beef up the embedded ecosystem. [ABSTRACT FROM AUTHOR]

LiDAR sensors are extensively used in autonomous vehicles and their optimal use is a critical concern. In this paper, we propose an embedded software architecture for multiple LiDAR sensors, i.e., a fusion system that acts as an embedded system for processing data from multiple LiDAR sensors. The fusion system software comprises multiple clients and a single server. The client and server are connected through inter-process communication. Multiple clients create processes to process the data from each LiDAR sensor via a multiprocessing method. Our approach involves a scheduling method for efficient multiprocessing. The server uses multithreading to optimize the internal functions. For internal communication within the fusion system, multiple clients and a single server are connected using the socket method. In sequential processing, the response time increases in proportion to the number of connected LiDAR sensors. By contrast, in the proposed software architecture, the response time decreases in inverse proportion to the number of LiDAR sensors. As LiDAR sensors become increasingly popular in the field of autonomous driving, the results of this study can be expected to make a substantial contribution to technology development in this domain. [ABSTRACT FROM AUTHOR]

Tiny embedded devices are cost and energy-sensitive, and high-density emerging non-volatile memory (NVM) can help reduce energy consumption at a fraction of the cost. However, high-density NVM has low write endurance compared to volatile memory, so it is vulnerable to write concentration. Most NVM lifetime improvement studies in the existing embedded environment have distributed writes by modifying the mapping relationship between physical and logical addresses. However, applying the existing wear leveling techniques in low-end MCUs such as ARM Cortex M3/M4 that use only physical addresses is hard. Therefore, we wear-level the write-heavy stack area to improve the NVM lifetime in low-end MCUs. However, since the stack of bare metal applications is difficult to move during runtime, we implement the migration function targeting the task stack of FreeRTOS. The task stack moves based on time, and to avoid the pointer validation problem caused by the movement of the task stack, we migrate the stack under safe conditions. In addition, FreeRTOS uses a single heap to preferentially allocate to low free space, which reduces the degree of freedom where the stack moves, reducing the effect of distributing the writes. To alleviate this problem, we add another heap for the stack migration and introduce circular dynamic allocation in the heap. Through our experiments, the proposed method was about 19.6% larger than the ideal case of maximum write, and the computational overhead was about 0.2%.

In autonomous navigation technologies, the Multi-State Constraint Kalman Filter (MSCKF) is one of the most accurate and robust tightly-coupled fusion frameworks for Visual-Inertial Navigation (VIN). However, the adoption of the MSCKF VIN system in real-time embedded applications depends heavily on an efficient implementation of its tangled pipeline. This work initially proposes a novel parallel multi-thread implementation of the MSCKF VIN pipeline on an embedded CPU-enabled hardware that has speeded up the per-epoch processing time of the pipeline by 41% compared to the conventional sequential implementation. The heart of the MSCKF pipeline’s visual backend is an inertially-aided 3D localization of visual feature points that are reduced to a set of nonlinear optimization problems which were conventionally solved in a serial fashion using the single-objective Gauss-Newton optimization algorithm. This work leveraged the parallel architecture of an embedded GPU and further proposes an efficient parallel implementation of a multi-objective Gauss-Newton algorithm. Integration of the proposed GPU-accelerated feature localization technique in the MSCKF parallel pipeline has resulted in 33% faster per-epoch processing time and consequently, the satisfaction of strict real-time constraints. The proposed parallel MSCKF VIN pipelines have been developed using C++ and CUDA on the NVIDIA Jetson TX2 embedded board. Experimental evaluations on a real visual-inertial odometry dataset have been provided to validate the efficacy and real-time performance enhancement of the proposed parallel implementation.

An increasing number of embedded systems include dedicated neural hardware. To benefit from this specialized hardware, deep learning techniques to discover malware on embedded systems are needed. This effort evaluated candidate machine learning detection techniques for distinguishing exploited from non-exploited RISC-V program behavior using execution traces. We first developed a dataset of execution traces containing Return Oriented Programming (ROP) exploitation on the RISC-V Instruction Set Architecture (ISA) and then developed several deep learning bidirectional Long Short-Term Memory (LSTM) models capable of distinguishing exploited traces from non-exploited traces, each using subsets of features from the execution traces. An objective of this effort was to evaluate which features (instruction addresses and immediate values) from an execution trace are application-specific, which features (opcodes and operands) are application-agnostic, and how these subsets of features affect model performance. Application-agnostic features allow a model to generalize its detection capability to detecting ROP in previously unseen applications. The model using opcode and operand sequences obtained 98.21% cross validation accuracy and 97.94% test accuracy. In contrast, a model using address values obtained 92.79% cross validation accuracy with 99.59% test set accuracy. This research also analyzed whether ROPs exploitation significantly affects branch prediction; experimental evidence suggests that it does. Thus, branch prediction behavior could be a valuable feature in detecting ROPs exploits.

Embedded systems for critical applications are often based on resource-constrained devices to meet the requirements like performance predictability and energy consumption. To deal with the increased software complexity, many of these systems have adopted reliable RTOSes (Real-Time Operating Systems) with advanced protection functionalities. Meanwhile, the concept of IoT (Internet of Things) is gaining momentum. Many IoT OSes, specialized to provide the large software stack required by IoT applications, have been released. Nevertheless, neither reliable RTOS nor IoT OS can satisfy all the requirements of IoT-enabled reliable systems. Dual-OS configuration (i.e. the coexistence of reliable RTOS and IoT OS) is a promising approach to achieve high reliability and productivity simultaneously. Existing dual-OS solutions, however, depend on additional hardware features (e.g. virtualization extensions, ARM TrustZone), which are unavailable in most resource-constrained devices. This paper presents iSotEE (iSolated Execution Environment), a middleware allowing IoT OS to run inside an isolated environment on top of a reliable RTOS without special hardware. Open-source implementations of iSotEE for Renesas RX (with TOPPERS/HRP3 as reliable RTOS, Amazon FreeRTOS as IoT OS) and ARMv7-M (with two configurations of Zephyr as reliable RTOS and IoT OS) architectures are provided and evaluated. The results show that iSotEE can create reliable systems with a small footprint for resource-constrained devices, high real-time performance for critical applications, and high productivity and throughput for IoT applications.

Current limitation is crucial to protect DC motors from overheating in overload situations. This consideration is more critical in applications that involve the movement of variable loads, such as exoskeleton applications, where there exists dynamic human-robot interaction. This work presents a software current limitation method based on a continuous DC motor model predictor. By predicting, according to the motor model, the voltages that would make the current match a threshold, the proposed method dynamically saturates the maximum voltages applicable to the motor to maintain the current under the predefined threshold. Using this method, a full-time current limitation can be obtained, but if desired, it also allows current peaks of configurable duration. Only motor parameters need to be known for the application of this algorithm, and it is easily adjustable to different DC motor models. Stand-alone motor tests show an effective limitation of current, achieving up to a 98.04% of maximum current when limited. The method has also been successfully validated in a rehabilitation exoskeleton application with four participants, obtaining an average current of 92.34% of current threshold when limited.

Developing software-intensive embedded systems is a significant challenge as embedded systems have become more complex and dynamic for integrating various constraints (e.g., real-time performance, design, and functional safety). In general, software practitioners reuse code to reduce development time for implementing required functionalities. However, embedded software development still lacks code reuse on a large scale due to its intricate constraints. This paper presents an approach to identifying reusable functions and their relationships from the legacy embedded software for faster development reducing functionality testing time. A python tool is developed to automatically extract the reusable functions and present them in a feature model. The search time for finding reusable functions speeds up when they are placed as features in a feature model. We conducted experiments on three GitHub embedded software projects (elevator, infotainment, and health monitoring systems). The experimental results find that our proposed approach reduces the feature search time by 59.0%, 49.8%, and 74.5%, respectively, compared to the manual searching approach for 50 features.

Deep Neural Networks (DNNs) have gained widespread popularity in different domain applications due to their dominant performance. Despite the prevalence of massively parallel multi-core processor architectures, adopting large DNN models in embedded systems remains challenging, as most embedded applications are designed with single-core processors in mind. This limits DNN adoption in embedded systems due to inefficient leveraging of model parallelization and workload partitioning. Prior solutions attempt to address these challenges using data and model parallelism. However, they lack in finding optimal DNN model partitions and distributing them efficiently to achieve improved performance. This paper proposes a DNN model parallelism framework to accelerate model training by finding the optimal number of model partitions and resource provisions. The proposed framework combines data and model parallelism techniques to optimize the parallel processing of DNNs for embedded applications. In addition, it implements the pipeline execution of the partitioned models and integrates a task controller to manage the computing resources. The experimental results for image object detection demonstrate the applicability of our proposed framework in estimating the latest execution time and reducing overall model training time by almost 44.87% compared to the baseline AlexNet convolutional neural network (CNN) model. • Parallel Computing. • Machine Learning. • DNN Model Partitioning. • Embedded Systems. • Embedded Software. [ABSTRACT FROM AUTHOR]

Nowadays, deep learning has become one of the most popular solutions for computer vision, and it has also included the Edge. It has influenced the System-on-Chip (SoC) vendors to integrate accelerators for inference tasks into their SoCs, including NVIDIA, NXP, and Texas Instruments embedded systems. This work explores the performance of the NXP i.MX8M Plus Neural Processing Unit (NPU) as one of the solutions for inference tasks. For measuring the performance, we propose an experiment that uses a GStreamer pipeline for inferring license plates, which is composed of two stages: license plate detection and character inference. The benchmark takes execution time and CPU usage samples within the metrics when running the inference serially and parallel. The results show that the key benefit of using the NPU is the CPU freeing for other tasks. After offloading the license plate detection to NPU, we lowered the overall CPU consumption by 10x. The performance obtained has an inference rate of 1 Hz, limited by the character inference.

This paper describes a study on the power and energy consumption estimation models that have been defined to facilitate the development of ultra-low power embedded applications. During the study, various measurements have been carried out on the instruction and application level to challenge the models against empirical data. The study has been performed on the multicore heterogeneous hardware platform developed for ultra-low power Digital Signal Processors (DSP) applications. The final goal was to develop a tool that can provide insight into power dissipation during the execution of embedded applications, so that one can refactor the source code in an energy-efficient manner, or ideally to develop an energy-aware C compiler. The side effect of the research presents interesting insight into how the custom hardware architecture influences power dissipation. The selected platform has been chosen simply because it represents R&D state of the art ultra-low power hardware used in hearing aids. The presented solution has been developed and tested in an Eclipse environment using Java programming language. [ABSTRACT FROM AUTHOR]

Face recognition payment is a new type of payment method, with AI face recognition technology as the core, and its speed and convenience are more in line with the users' payment habits. However, the face is a biological feature with weak privacy, and the protection of user information security is particularly important. At present, face payment technology still has security risks, and the data transmitted during the transaction process are vulnerable to attacks. Aiming at the security problems in the payment process, a payment system that is jointly encrypted by the SM4 algorithm and the face liveness detection algorithm was proposed in this paper, which supports a variety of communication methods. The hardware platform adopts an octa-core 64-bit ARM processor with a main frequency of 1.8 GHz, which has powerful computing and processing capabilities. Based on the Android intelligent operating system, the development environment is more secure and convenient. It is also equipped with a liveness detection 3D structured light camera, which dynamically collects face information and accurately analyzes the characteristics of living bodies. Through the data encryption and decryption test and face performance index detection, the expected effect of the system was achieved, which greatly improved the performance of the face payment system currently studied. The SM4 encryption algorithm improved the running rate of encrypted data and the security of face transaction data transmission, the face detection algorithm improved the accuracy of living body feature recognition, and the payment system effectively improved the accuracy and security of face payment. [ABSTRACT FROM AUTHOR]