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The emergence of Virtual Prototypes (VPs) at the Electronic System Level (ESL) has played a major role in modernizing the System-on-Chips (SoCs) design process to raise design productivity and reduce time-to-market. A VP is an abstract and executable software model implemented typically using SystemC and its Transaction Level Modeling (TLM) framework. However, this modern VP-based design process still has weaknesses, in particular, due to the significant manual effort involved for design understanding, analysis and modeling tasks which is both time consuming and error-prone. This paper introduces an automated and fast design understanding approach that enables designers to trace detailed information of the VPs’ structure and behavior. Experimental results including a real-world VP-based SoC show the advantages of our approach such as its accuracy, applicability, and scalability.

System-architecture design optimization of flow-based microfluidic biochips has been extensively investigated over the past decade. Most of the prior work, however, is still based on chip architectures with dedicated storage units and this, not only limits the performance of biochips, but also increases their fabrication cost. To overcome this limitation, a distributed channel-storage architecture can be implemented, where fluid samples can be cached temporarily in flow channels instead of using a dedicated storage. This new concept of fluid storage, however, requires a careful arrangement of fluid samples to enable the channels to fulfill their dual functions. Moreover, to avoid cross-contamination between fluidic flows, wash operations are necessary to remove the residue left in flow channels. In this paper, we formulate the first system level design and wash optimization problem for microfluidic biochips with distributed channel storage, considering high-level synthesis, physical design, and wash optimization simultaneously. Given the protocol of a biochemical application and the corresponding design requirements, our goal is to generate a chip architecture with minimized cost. Meanwhile the bioassay can be executed efficiently with an optimized wash scheme. Experimental results confirm that our approach leads to short completion time of bioassays, low chip cost, and high wash efficiency.

In multi-drive electrified powertrains, the control strategy strongly influences the component load collectives. Due to this interdependency, the component sizing becomes a difficult task. This paper comprehensively analyses different electric drive system sizing methods for multi-drive systems in the literature. Based on this analysis, a new data-enhanced sizing approach is proposed. While the characteristic is depicted with a physics-based polynomial model, a data-enhanced limiting function ensures the parameter variation stays within a physically feasible range. Its beneficial value is demonstrated by applying the new model to a powertrain system optimization. The new approach enables a detailed investigation of the correlations between the characteristic of electric drive systems and the overall vehicle energy consumption for varying topologies. The application results demonstrate the accuracy and benefit of the proposed model.

All modern low power system on a chip (SoC) architectures are equipped with an in-built power management system. Every new system is expected to have more features and lower power consumption, resulting in a continuous demand to improve energy efficiency. To cope up with the ever increasing demand, an active power-aware management verification architecture is necessary to minimize the power consumption. Power reduction techniques include clock-gating, power-gating, multi-voltage, and voltage-frequency scaling. The proposed verification architecture utilizes the Unified Power Format (UPF) 2.1 libraries to achieve early design verification at the Electronic System-Level (ESL) of abstraction. The proposed testbench can verify several designs of different power management schemes. The presented work offers a reduction in power states, CPU time and simulation time as compared to existing techniques. The interactive formal and simulation-based verification methods are used in this paper to remove the simulation artifacts during functional and power co-simulation. Additionally, this paper incorporates functional correctness and power-aware checks for different modules of Design Under Verification (DUV) at Transaction-Level Modeling (TLM).

The increasing complexity of the cryptographic modeling and security simulation of the Advanced Encryption Standard (AES) necessitate fast modeling and simulation security environment. The SystemC language is used in Electronic System Level (ESL) that allows cryptographic models to achieve high security and modeling simulation speed. Yet, the use of SystemC in the security simulation requires modifications of the original code which increases the modeling complexity. The Aspect-Oriented Programming (AOP) can be used in the cryptographic modeling and security simulations without any code modification. In this paper, a new AES SystemC model using the AOP technique is presented. A functional verification environment is proposed to test the functionality of the AES SystemC AOP model, the impact of AOP on simulation time, and the size of the executable files. The design of the AES model is developed with the weaving of all modules by AspectC++ which is an AOP language. The Simulation results show the efficiency of the proposed AES model and the uses of the AOP technique do not have a significant impact on simulation time or on the size of the executable file.

Time plays a major role in the specification of Cyber-physical Systems (CPS) behavior with concurrency, timeliness, asynchrony, and resource limits as their main characteristics. In addition to timeliness , the specification of CPS needs to assess and unambiguously define its behavior with respect to the other Quality-of-Information (QoI) properties: (1) Correctness, (2) Completeness, (3) Consistency, and (4) Accuracy. Very often, CPS need to handle these QoI properties, and any combination thereof, multiple times when performing computation and communication processes. However, a model-driven and systematic approach to specify CPS behavior that jointly considers combined QoI aspects is possible but missing in existing methodologies. As the first contribution of this work, we provide an extension to an established model of computation (MoC) based on “Functions driven by Finite State Machine” (FunState) to enable a model-driven composition mechanism to create CPS behavior specifications from reusable components. Second, we present a novel set of design patterns to illustrate the modeling of QoI-aware CPS specifications that can be applied in several state-of-the-art Electronic System Level (ESL) methodologies. The time semantics of the MoC are formalized using the tagged-signal-model, and the presented model-driven approach enables the composition of multiple design patterns. The main benefits of the presented model-driven approach and design patterns to create CPS specifications are as follows: (a) reduce modeling effort, errors, and time through the reuse of known recipes to re-incurring tasks and allow to automatically generate repetitive control flows based on extended Finite State Machines; (b) increase system robustness and facilitate the creation of holistic QoI management allowing to unambiguously define system behavior for scenarios with single/multiple QoI requirement violations in different models of computation; (c) dynamically validate timing behavior of system implementations to enable a multi-objective optimization of nonfunctional properties that influence CPS timing. We demonstrate the aforementioned benefits through the modeling and evaluation of an infrastructure-assisted automated driving case study using Infrastructure-to-Vehicle (I2V) communications to distribute QoI critical road environment information.

The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.

This paper presents a new Property-Driven Design (PDD) method that starts from an abstract system model and integrates formal property checking early into a top-down design methodology for register transfer level (RTL) hardware. In PDD the role of formal verification is not limited to “bug hunting” alone. Instead, the formal techniques are applied in such a way that a formal relationship is provided between the abstract system model and its concrete implementation at the RTL. In order to avoid the high efforts associated with verification by property checking the proposed PDD approach automatically generates abstract properties from a system-level description and later refines them along the design process. The advantage of this methodology is to obtain a formally verified design at lower costs when compared to conventional design flows with property checking. The main benefit of the proposed approach results from the fact that a formally sound system model is available together with the RTL design. Specifically, LTL properties proven on the abstract model also hold on the concrete implementation. This facilitates many complex analysis and verification tasks in today’s design flows and contributes to emancipating system-level models from prototypes to golden design models. Several open-source and industrial case studies are reported that demonstrate the high potential of a PDD-based design paradigm.

A digital microfluidic biochip (DMB) is an attractive platform for automating laboratory procedures in microbiology. To overcome the problem of cross-contamination due to fouling of the electrode surface in traditional DMBs, a contactless liquid-handling biochip technology, referred to as acoustofluidics, has recently been proposed. A major challenge in operating this platform is the need for a control signal of frequency 24 MHz and voltage range $\pm 10/\pm 20$ V to activate the IDT units in the biochip. In this paper, we present a hardware design that can efficiently activate/de-activated each IDT, and can fully automate an bio-protocol. We also present a fault-tolerant synthesis technique that allows us to automatically map biomolecular protocols to acoustofluidic biochips. We develop and experimentally validate a velocity model, and use it to guide co-optimization for operation scheduling, module placement, and droplet routing in the presence of IDT faults. Simulation results demonstrate the effectiveness of the proposed synthesis method. Our results are expected to open new research directions on design automation of digital acoustofluidic biochips.

Security critical hardware devices in CPS must experience security testing including side-channel leakage detection, which aims to provide earlier assessment before coming into service. Due to the exponential nature of ESLS, performing fast and efficient leakage detection is a critical task in the context of security evaluation for DSE. However, the traditional method of leakage detection is always time-consuming and costly. To overcome this limitation, this article investigates the strategies of leveraging the emerging ML techniques to achieve faster and more effective leakage detection. A clustering-based methodology is proposed as an alternative method for first-order leakage detection. We further confirm the effectiveness and rapidity of the proposed method by launching clustering-based analysis on seven different benchmarks. The proposed method provides almost the same quality of results as the non-specific t-test while substantially reducing the efforts on security evaluation in CPS.

The emergence of cyber-physical-social systems (CPSS) as a novel paradigm has revolutionized the relationship between humans, computers and the physical environment. In this paper, we survey the advancement of CPSS through cyber-physical systems (CPS), cyber-social ​systems (CSS) and CPSS, as well as related techniques. CPSS are still at their infancy, most recent studies are application-specific and lack of systematic design methodology. To exploit the design methodology for CPSS, we review the existing system-level design methodologies in multiple application domains and further compare their performance characteristics and applicability for CPSS. Finally, we introduce our latest research advancement on system-level design methodology for CPSS and summarize future challenges for designing CPSS.

Due to the ever increasing complexity of hardware systems, designers strive for higher levels of abstractions in the early stages of the design process. Modeling hardware at the electronic system level (ESL) is one way to address this demand, with the C++-based system modeling framework SystemC and its abstract communication library transaction level modeling (TLM) having become de-facto standards for ESL system design. While the C++ compiler is sufficient to compile and simulate a given ESL design, for tasks of design understanding, debugging, or validation (where access to the details of design’s structure and behavior is necessarily required), design needs to be processed by an appropriate tool. This problem is often solved by adding instrumentation code to either the design or the library, usually resulting in incomplete logs, work overhead and/or incompatibilities. This paper introduces an approach that automatically extracts information about both, structure and behavior of SystemC designs and TLM transactions, nonintrusively. The information is retrieved from a given design by running it in debug mode while being connected to a preprogrammed debugger, thus leaving the existing sources and workflows untouched while collecting a vast amount of data without user intervention. Illustrating use cases, value change dump files of the SystemC models’ behavior and unified modeling language activity diagrams of transaction protocols are created automatically from simulation runs.

The development of large-scale multi- and many-core platforms and the rising complexity of embedded applications have led to a significant increase in the number of implementation possibilities for a single application. Furthermore, rising demands on safe, energy-efficient, or real-time capable application execution make the problem of determining feasible implementations that are optimal with respect to such design objectives even more of a challenge. State-of-the-art Design Space Exploration (DSE) techniques for this problem demonstrably suffer from the vast and sparse search spaces posed by modern embedded systems, emphasizing the need for novel design methodologies in this field. Based on the idea of reducing problem complexity by a suitable decomposition of the system specification—in particular, by a reduction of target architecture or task mapping options—the work at hand proposes a portfolio of dynamic decomposition mechanisms that automatically decompose any system specification based on a short pre-exploration of the complete system. We present a two-phase approach consisting of (a) a set of novel data extraction and representation techniques combined with (b) a selection of filtering operations that automatically extract a decomposed system specification based on information gathered during pre-exploration. In particular, we employ heat map data structures and threshold as well as graph-partitioning filters to reduce problem complexity. The proposed decomposition procedure can seamlessly be integrated in any DSE flow, constituting a flexible extension for existing DSE approaches. Furthermore, it improves existing static decomposition techniques and other heuristics relying on information about the problem instance, since systems with irregular architectural topology or distribution of resource types can now be decomposed based on an automatic, problem-independent pre-exploration phase. We illustrate the efficiency of the proposed decomposition portfolio applied to state-of-the-art DSEs for many-core systems as well as networked embedded systems from the automotive domain. Experimental results show significant increases in optimization quality of up to 87% within constant DSE time compared to existing approaches.

Wearable devices have the potential to transform multiple facets of human life, including healthcare, activity monitoring, and interaction with computers. At the same time, a number of technical and adaption challenges hinder widespread and daily usage of wearable devices. Recent research efforts have focused on identifying these challenges and solving them such that the potential of wearable devices can be realized. In this monograph, the authors guide the reader through the state-of-the-art of wearable devices, detailing the challenges that researchers and designers face in achieving wide-adoption of the technology throughout society. The authors also identify the application areas where these devices are most likely to gain acceptance. They point the way to overcoming these challenges by detailing the recent advances in providing physically flexible designs, the energy management for such designs and finally consider some of the security and privacy aspects of wearable devices such that user compliance can be improved. This monograph serves as a comprehensive resource for challenges and solutions towards self-powered wearable devices for health and activity monitoring.

This paper aims to reduce the power consumption of electrocardiography based wearable healthcare devices, by introducing power reduction approaches and considerations at system level design, where we have the highest potential to influence power. It focuses, in particular, on algorithm design and implementation, data acquisition, and transmission under constrained resources. A thorough investigation of the suitability of nine existing algorithms for on-sensor QRS feature detection is conducted, with respect to metrics such as sensitivity, positive predictivity, power consumption, parameter choice and time delay. Optimisation of data acquisition on CPU-based IoT systems is performed, and the current consumption is reduced by a factor of 3 using a combination of direct memory access (DMA) list approach and low-level register manipulations for task delegation. The acquisition data rate, sampling rate, buffer and batch size are also optimised. To reduce the power consumption by data transmission, the effect of on-sensor versus off-sensor processing is investigated. While focusing on CPU-based systems with experiments performed on a generic low-power wearable platform, the design optimisation and considerations proposed in this work could be extended to custom designs and allow further investigation into QRS detection algorithm optimisation for wearable devices.

Against the background of the big environmental and societal challenges as formulated for example in Flightpath 2050, current developments in aircraft design are aiming at further emission reduction through integrated, unconventional propulsion, systems and airframe innovations. This requires the further integration of methods for multidisciplinary modelling, analysis and optimization for aircraft design, but also for propulsion and system level designs. Moreover, experimental validation of the methods and physical testing of critical unconventional propulsion and system designs are prerequisites for industrially relevant development processes. This paper presents some key technologies for computationally efficient collaborative MDO (multidisciplinary design and optimization) frameworks for multidisciplinary design and validation of advanced aeronautic products like aircraft and propulsion systems.

Manufacturing organizations faces many changes along with the occurrence of environmental changes, it comes from internal and external sources. Innovation become one of the keywords to help the organizations be more competitive, such as doing product development. First, digging through from the survey, the customer’s needs as the initial planning phase, concept development, system level design, detail design, test and reparation details among the beginning of production. During the product development process, the Organization has not identified the potential waste in detail yet at each stage of product development. Moreover, the repair process becomes less effective. By using this concept, it will help in potential waste identify. The results showed that the stage of concept development had the highest frequency, for instance the common of lacking information related to the customers need products information which will be developed. Then, frequency is happened on the stage of the testing, and refinement, detail design, system level design and planning. Through the concept of lean VSM can be known by using a value of VA 53%, NVA 29% and 18% Waste, time to market can be shortened 18% or 47 days from early 262 days be 215 days.

A systematic left to right process variation is observed across a 20 nm technology chip. Consequently, reference generators and amplifiers which are scattered around the chip undergo severe performance fluctuations. In this paper, we present a design methodology that is used to scale down the influence of systematic variation on circuit performance. The physical centre of the die is tapped and routed to the voltage generators as a feedback to minimize the left and right performance deviation. Optional connection cells are implemented in order to program and tap the feedback path whichever is closest to the physical centre accordingly.

System-level design for low-power and energy efficiency in embedded systems using Heterogeneous Multi-Processor System-on-Chip (HMPSoC) is a challenging task due to the large design space. The related Design Space Exploration (DSE) suffers from scaling due to various degrees of freedom across multiple layers of the compute stack. Traditional multi-objective metaheuristic approaches work well for unconstrained system-level design, but do not scale well with the additional system and user constraints. Using a SATisfiablity problem (SAT) solver as a decoder for the meta-heuristics has been explored in related research as a better solution for a discrete constrained multi-objective optimization problem. This approach restricts the problem to the feasible space, hence improving the quality of the results. In this paper, we explore the ways in which constrained decoding such as the SAT decoding approach can be leveraged for cross-layer design space exploration. Low-power methodologies such as Dynamic Voltage and Frequncy Scaling (DVFS) and application-specific implementations are integrated, thus scaling the design space. Additionally, we demonstrate how user constraints on the system synthesis problem can be learned by our proposed approach to prune the meta-heuristic design space and improve the quality of the solutions. As the constraints on the problem increase and the design space scales, the constrained decoding approach outperforms a typical meta-heuristic approach.

The emergence of Virtual Prototypes (VPs) at the Electronic System Level (ESL) has played a major role in modernizing the System-on-Chips (SoCs) design flow to raise design productivity and reduce time-to-market constraint. Leveraging VPs and extending their use-cases for early security validation are shown as a promising direction. As the cost of fixing any security flaws increases with the stage of development, VP-based security validation can significantly avoid costly iterations. In this paper, we propose VIP-VP, a novel VP-based dynamic information flow analysis approach at the ESL.VIP-VP enables designers to validate the information flow policies of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experimental results including a real-world VP-based SoC demonstrate the scalability and applicability of the proposed approach.

High-level Synthesis (HLS) using system-level modeling language SystemC at the Electronic System Level (ESL) is being increasingly adopted by the semiconductor industry to raise design productivity. However, errors in the high-level design can propagate down to the low-level implementation and become very costly to fix. Thus, SystemC HLS verification and debugging are necessary and important. While monitoring simulation behavior is a straightforward solution to debug a given design in the case of an error (results of verification), it can become a very time-consuming process as a large amount of data that is not necessarily relevant to the source of error is analyzed.In this paper, we propose a fast and automated debugging-aware visualization approach, enabling designers to monitor the portion of a given SystemC HLS design’s simulation behavior that is related to the erroneous output(s). Experimental results including an extensive set of standard SystemC HLS designs show the effectiveness of our approach in localizing the designs’ simulation behavior in terms of the number of visualized variables. In comparison to traditional visualization methods, our proposed approach obtains up to 96% and 91% reduction in the search space for single and multiple faulty outputs, respectively.

The next-generation instruments for millimeter-wave astronomy will require large arrays of detectors to surpass current performance [see (Hui, 2016) and (Ade, 2018)]. On account of integration challenges, focal planes relying on transition edge sensor (TES) bolometers will not scale gracefully. Thermal Kinetic Inductance Detectors (TKIDs) are highly scalable and have the design flexibility to solve this problem. We present an update on our detector development and systems engineering in preparation for a 2022 TKIDs camera deployment that includes noise performance, optical characterization, and a calibration strategy.

This paper presents a system level design of a reconfigurable multi-mode continuous-time low-pass sigma delta modulator for 5G applications. The proposed modulator can support multiple channel bandwidths in the 5G standard which are 80, 40, 20, and 10 MHz. The proposed modulator can be reconfigured easily for each channel bandwidth so that it can achieve the optimum performance in each mode. Moreover, the proposed modulator has a signal transfer function with a very slight peaking. The system level design and Simulink simulation results of the proposed modulator are presented. Furthermore, a circuit behavioral model that includes most of the circuit non-idealities is implemented and simulated in Cadence environment. The results show that the signal to noise and distortion ratio is 75.2 dB, 76.6 dB, 76.7 dB, and 77.6 dB for the channel bandwidths 80, 40, 20, and 10 MHz respectively.

The majority of existing frameworks for automated synthesis of Approximate Circuits (AxCs) employ a search-based Design Space Exploration (DSE) approach. This includes an iterative process where approximate circuit instances are created and evaluated in terms of quality and performance metrics. The quality evaluation of each instance via either verification or testing results in extremely long computation times, imposing a practical limit on the number of nodes that can be explored in the design space. To overcome this problem, we exploit Random Forests (RFs) to develop extremely fast estimators to evaluate the quality and performance of AxC instances while avoiding time-consuming computations. Utilizing these estimators we build LDAX, an efficient design space exploration framework that attempts to improve the runtime of the AxCs synthesis process. LDAX is based on the fact that, in an iterative search space exploration, a large number of validations can be skipped by leveraging a high-accuracy predictor. To efficiently explore the design space, which is usually represented by a tree and each node denotes an AxC, we propose a learning-based search technique that can quickly analyze a large set of nodes even very deep nodes in the tree. Our experimental results reveal that LDAX can achieve average speed-up of 41 × on a set of practical benchmarks from different application domains in comparison with the most competitive state-of-the-art framework.

The demand for high performing, lightweight, reliable inverters, increased the scope of wide bandgap and high-switching frequency based solutions. To achieve such high efficiency inverters, it is vital to focus on the system level design considerations to maximize the benefits of these advanced technologies. This paper presents an improved design based on considerations to further reap the benefits of choosing the right inverter topology; increased capabilities through paralleling devices, with reduced total number of switches; and designing a planarized inverter with PCB based busbar. Appropriate thermal analysis and heatsink design has aided in increased system power density along with the overall efficiency. Demonstration of a SOkW 3-phase 3-level paralleled T-type SiC inverter operating at 40kHz switching frequency for aircraft applications is shown to evaluate the benefits of proposed design methodology. The prototype achieves a high power density of 11kW/L.

Machine learning has emerged as the dominant tool for implementing complex cognitive tasks that require supervised, unsupervised, and reinforcement learning. While the resulting machines have demonstrated in some cases even superhuman performance, their energy consumption has often proved to be prohibitive in the absence of costly supercomputers. Most state-of-the-art machine-learning solutions are based on memoryless models of neurons. This is unlike the neurons in the human brain that encode and process information using temporal information in spike events. The different computing principles underlying biological neurons and how they combine together to efficiently process information is believed to be a key factor behind their superior efficiency compared to current machine-learning systems.

Embedded systems are built for specific purposes and are optimized to meet different kind of constraints, such as performance, timing, power and cost. The design process therefore involves different optimization activities. In this paper, we discuss the use of constraint programming (CP) technology for these optimization problems. The main advantages and disadvantages of applying CP to embedded system design problems are discussed on two examples, scheduling and mapping. Based on these examples modelling capabilities of CP and basic solving methods are discussed. We have identified CP modelling capability as an important factor for problem formalization and their uniform representation. We have also, using several experiments, show efficiency of the models and solving process. Finally, we have also pointed out difficulties with CP technology that are mostly related to search methods that, for more realistic problems, must be carefully selected or even new methods must be developed.

Medical implant devices have found widespread application in recent years. The Super-Regenerative Receiver has been one preferred architecture due to its power advantage over other architectures. We present a detailed analysis of the circuits and their equivalent models to be used in system level design of a Super-Regenerative Receiver in this paper. The design procedure is also demonstrated with a receiver design example. Designs were carried out in UMC 180 nm process with a center frequency of 416 MHz for MedRadio band. Errors between the simulation results of the proposed model and actual circuits are less than 1.6% for LNA characteristics and 7% for receiver output amplitude. 10 Mbps data rate was achieved with 432 pJ/bit energy consumption over 1.8 V power supply. The study is concluded with the simulation results of the circuits and the equivalent models.

International audience; High performance streaming applications require hardware platforms featuring complex, multi-level interconnects. These applications often resemble a task-farm, where many identical tasks listen to the same input channel. Usual embedded system design tools are not well adapted to capture these applications. In particular, the non-uniform memory access (NUMA) nature of the platforms induces latencies that must be carefully examined. The paper proposes a multi-level modeling methodology and tools (TTool, SoCLib) that have been extended to model the characteristics of streaming applications (multiple tasks, non deter-ministic behavior, I/O devices) in UML/SysML, and to automatically generate a virtual prototype that can be simulated with high precision. The paper uses a typical streaming application to show how latencies can be estimated and fed back to diagrams.

This work presents a method to optimally distribute the block specifications in an RF receiver in order to reduce power consumption. The parameters are Gain (G), Noise Figure (NF) and Input Third Order Intercept Point (IIP3). The method is based on setting the signal quality per block at the output; Signal to Noise Ratio (SNR) for noise and Signal to Noise plus Distortion Ration (SNDR) for linearity. Both are limited in order to fulfill the sensitivity and intermodulation tests of a given standard. Non linear power models can be used as the method is based on heuristics associated with non linear optimization. First, random valid sets are tested "A" times, while the best candidate is chosen as starting point for a non linear optimization with bounds based on interior point algorithm. The process is repeated "B" times, and the best candidate is chosen. To validate the method, a direct-conversion receiver was dimensioned for the Long Term Evolution (LTE) and Bluetooth Low Energy (B-LE) standards. Two power models were used, labeled PM1 and PM2. First the LTE is considered. When compared to predetermined signal quality distributions, the method reduced the power consumption by 65% and 41%, considering PM1 and PM2, respectively. Then the B-LE is chosen with power PM2. This model is linear and has an analytical minimum derived in the literature. The optimization achieved a precision of 0.2% to the analytical minimum using A=1000 and B=15.

Due to the slow scaling of board and package technology, on-chip inductor has shown promising potential to enable more compact design and smaller parasitics for inductor-based designs, such as voltage regulator, resonant clocking, filter, etc. On the other hand, conventional on-chip 2D spiral inductor must be placed on the top metal layers, thereby consuming significant routing resources for global interconnects. Moreover, it may need more dedicated shielding to prevent unnecessary coupling, which further increases its occupied area. With the popularity of 2.5D and 3D chip architecture, Through-Silicon-Via (TSV) has been widely used, a significant portion of which are placed for thermal/manufacturability/reliability purposes. Thus, those redundant TSVs can be utilized to form the on-chip inductor for 2.5D/3D chips, with lower footprint and higher inductance density compared from the conventional spiral inductor. Unlike prior works focusing on the inductor itself, this paper discusses the optimization and application of such TSV-inductor from system perspective, including the optimization options and its design considerations. The possible design options including physical parameters, architecture and materials, to optimize the TSV-inductor are thoroughly investigated. Based on that, we further study a few key design scenarios to evaluate the design impact with use of such TSV-inductor and provide the design guidelines for its application in actual system designs.

In system-on-chip design, resources for verification is limited by time-to-market and cost. In order to allocate verification resources effectively, managers need to rely on their experience backed by design related metrics. However, often there are also other aspects of development process, such as bug history and developer information that can improve the effectiveness of verification. Software bug prediction is a machine learning (ML)-based technique which predicts whether a given software module is bug-prone by using product and process metrics of the module. Therefore, it can help direct verification effort, reduce costs, and improve the quality of software. Although there is a plethora of work in software bug prediction, no such work exists for SystemC. We propose an ML-based software bug prediction solution for verification of SystemC models used in virtual prototypes that takes into account system level design metrics and demonstrate its effectiveness on several open source system level designs. We find that 96% of modules could be correctly predicted as buggy or clean.

This paper presents a novel approach for the verification of multisensor data fusion algorithms in complex automotive sensor networks. Multisensor fusion plays a central role in enhancing the interpretation of traffic situations, facilitating inferences and decision making. It has therefore been instrumental in the ongoing innovation of Advanced Driver Assistance Systems (ADAS) which paves the way to autonomous driving. We introduce a real-time framework which can benchmark the performance of the fusion algorithms at the electronic system level using a Hardware-in-the-Loop (HiL) co-simulation. The presented research provides a quantitative approach for a trade-off between physical realism and computational efforts of the real-time synthetic simulation. The proposed framework illustrates a generic architecture of ADAS sensor error injection for robustness testing of the System under Test (SuT). We construct a lemniscate model for errors to find multivariate outliers with the Mahalanobis distance. A critical driving scenario considering road users in urban traffic describes the dynamic behaviour testability of the fusion algorithms. The industry-proven framework facilitates a functional verification of multisensor-fusion-based object detection precisely and more efficiently on the target electronic control unit (ECU) in the laboratory.

Design of ultralightweight but secure encryption engine is a key challenge for Internet-of-Things edge devices. This paper explores the system level design space for an ultralow power image sensor node for secure communication and proposes an optimized datapath architecture for 128-bit SIMON (SIMON128), a lightweight block cipher, for minimal performance, power, and area overheads with increased level of side-channel security. Various datapath architectures for SIMON are explored for simultaneously increasing energy-efficiency and resistance to power-based side-channel analysis (PSCA) attacks. Alternative datapath architectures are implemented on ASIC (15 nm CMOS) and field programmable gate array (FPGA) (Spartan-6, 45 nm) to perform power, performance, and area analysis. We show that, although a bitserial datapath minimizes area and power, a round unrolled datapath provides $80{\times }$ higher energy-efficiency and $143{\times }$ higher performance, compared to the baseline bitserial design. Moreover, the PSCA measurements performed using Sakura-G board with Spartan-6 FPGA, demonstrate that a 6-round unrolled datapath improves minimum-traces-to-disclosure for correlation power analysis (CPA) by at least $384{\times }$ over baseline bitserial design with no successful CPA even with 500 000 measurements. Finally, application to the image-sensor node demonstrates that optimized unrolled SIMON128 can provide equivalent performance to AES128 at lower area, higher energy efficiency, and improved side channel security.

Early application timing estimation is essential in decision making during design space exploration of heterogeneous embedded systems in terms of hardware platform dimensioning and component selection. The decisions which have the impact on project duration and cost must be made before a platform prototype is available and software code is ready to be linked and thus timing estimation must be done using high-level models and simulators. Because of the ever increasing need to shorten the time to market, reducing the amount of time required to obtain the results is as important as achieving high estimation accuracy. In this paper, we propose a novel approach to source-level timing estimation with the aim to close the speed-accuracy gap by raising the level of abstraction and improving result reusability. We introduce a concept – elementary operations as distinct parts of source code which enable capturing platform behaviour without having the exact model of the processor pipeline, cache etc. We also present a timing estimation method which relies on elementary operations to craft hardware profiling benchmark and to build application and platform profiles. Experiments show an average estimation error of 5%, with maximum below 16%.

The advancement of communication technologies and the change of the global economic landscape has paved the way for connected, smart manufacturing industries. Cyber-physical systems sit at the core of the development endeavor of the modern manufacturing industries. However, a cyber-physical system integrated weldability certification is still an unmet need. This paper presents a conceptual cyber-physical system framework for Resistance Spot Welding (RSW) weldability certification that integrates the physical welding machine and sensor data with analytics and prediction modules. We develop a system level design of the CPS framework and determine the requirements for developing a CPS for RSW. In this framework, machine learning algorithms and modern distributed computation frameworks are used to predict RSW weld quality.

High level Synthesis (HLS) or Electronic System Level (ESL) synthesis requires scheduling algorithms that have strong capability to reach optimal/near-optimal solutions with significant rapidity and greater accuracy. A novel power efficient scheduling approach using ‘PI’ method has been presented in this thesis that reduces the final power consumption of the solution at the expenditure of minimal latency clock cycles. The proposed scheduling approach is based on ‘Priority indicator (PI)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Application of the proposed approach results in even distribution of allocated hardware functional units thereby yielding power efficient scheduling solutions. The two main novel and significant aspects of the thesis are: a) Introduction of ‘Intersect Matrix’ topology with its associated algorithm which is used to check for precedence violation during scheduling b) Introduction of PI method using Priority indicator metric that assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach has been done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q- metric)’. This Q-metric is a combination of latency and power consumption values for the solution found, which dictates the quality of the final solutions found in terms of cost for both the proposed and existing approaches. An average improvement of approximately 12 % in quality of final solution and average reduction of 59 % in runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.

We propose a safety-oriented design process for IP-based safety-critical system-on-chip (SoC). The proposed safety process can facilitate the measurement of the robustness based on the safety-related metrics and scales of failure-induced risks in a system that can be employed to locate the critical components for protection to effectively diminish the influence of failures on the system. The risk reduction phase is activated to enhance the robustness of critical components identified by vulnerability analysis if the measured robustness is insufficient. An SoC-level safety design platform was built on the SystemC Synopsys Platform Architect MCO to demonstrate the core idea of the safety process. The safety-oriented design process for an ARM-embedded SoC modeled at the TLM level was conducted to demonstrate the feasibility of our safety approach.

Biological mechanisms are embraced in mobile robots to interact with their environments. Although existing biologically inspired robots perform well, their performance is limited due to the lack of a flexible spine. A vertebrate spine provides agility, a wide range of motion, balance, and efficiency. This paper proposes a system-level design methodology for a distributed and scalable actuator that mimics a robotic spine in the vertical plane. A modified limb design is introduced that significantly improves the torque capability of the distributed actuator.

This paper presents an architectural framework and an evaluation model for Static Random Access Memory (SRAM)-based Computing-in-Memory (CIM) edge Convolutional Neural Network (CNN) accelerators. To provide a baseline for system-level design perspectives, an architectural framework for SRAM-CIM design concerning the key design points in state-of-the-art works is proposed. Furthermore, a configurable evaluation model featuring top-down design flow based on the proposed framework is established to investigate design space explorations. Case studies validated the framework and evaluation model using LeNet-5, AlexNet and VGG-16 to achieve energy-aware optimizations. The optimized memory scale for LeNet-5 is "16 PEs and 120 tiles" with the minimal estimated inference energy of 0.0018J, while for AlexNet and VGG-16, "16 PEs and 120 tiles" is better achieving minimal energy consumption of 0.1733mJ and 0.6825mJ respectively. Estimation results highlight tradeoffs among data represent- tation parameters and memory partitioning parameters. This work provides specific SRAM-CIM design guidelines from a system-level perspective.

High Quality Mobile Virtual Reality (VR) is what the incoming graphics technology era demands: users around the world, regardless of their hardware and network conditions, can all enjoy the immersive virtual experience. However, the state-of-the-art software-based mobile VR designs cannot fully satisfy the realtime performance requirements due to the highly interactive nature of user's actions and complex environmental constraints during VR execution. Inspired by the unique human visual system effects and the strong correlation between VR motion features and realtime hardware-level information, we propose Q-VR, a novel dynamic collaborative rendering solution via software-hardware co-design for enabling future low-latency high-quality mobile VR. At software-level, Q-VR provides flexible high-level tuning interface to reduce network latency while maintaining user perception. At hardware-level, Q-VR accommodates a wide spectrum of hardware and network conditions across users by effectively leveraging the computing capability of the increasingly powerful VR hardware. Extensive evaluation on real-world games demonstrates that Q-VR can achieve an average end-to-end performance speedup of 3.4x (up to 6.7x) over the traditional local rendering design in commercial VR devices, and a 4.1x frame rate improvement over the state-of-the-art static collaborative rendering.

In the network applications domain, different network environments and scenarios demand various line rates, and restrain the design of the network processor by several constraints such as power and area. Additionally, new network services and applications with different processing requirements are increasingly emerging day by day. In this regard, having a multi-objective and flexible performance model that can be used to minimize the cost and time of designing network processors is an inevitable need. In this paper, we propose an accurate and fast prediction model that exploits just a few numbers of system-level parameters to estimate the performance and power of a commercial network processor, Intel IXP2800. The proposed design methodology uses a non-linear learning algorithm - a combination of the polynomial transformation of design parameters and higher-order spline functions - which in the face of newly introduced applications needs only a small training set, i.e. a small number of simulations, to train the model. Our experimental results show the proposed models can achieve a median error rate as low as 8.7 percent for performance and 2.6 percent for power metric.

Computing-in-memory (CIM) is an attractive approach for energy-efficient neural network (NN) processors, especially for low-power edge devices. Previous CIM chips [1] –[5] have demonstrated macro and system-level design enabling multi-bit operations and sparsity support. However, several challenges exist, as shown in Fig. 15.2.1. First, though a previously proposed block-wise sparsity strategy [5] can power off ADCs, zeros still contributed to storage requirements, and power gating was not applied to computing resources. Second, on-chip SRAM CIM macros are not large enough to hold all weights. Updating weights between computing operations leads to significant performance loss. Finally, the limited sensing margin incurs poor accuracy for large NN models on practical datasets, such as ImageNet. The precision and power of the ADCs should be optimized and adjusted.

Synchoros VLSI design style has been proposed as an alternative to the standard cell-based design style; the word synchoros is derived from the Greek word choros for space. Synchoricity discretises space with a virtual grid, the way synchronicity discretises time with clock ticks. SiLago (Silicon Lego) blocks are atomic synchoros building blocks like Lego bricks. SiLago blocks absorb all metal layer details, i.e., all wires, to enable composition by abutment of valid; valid in the sense of being technology design rules compliant, timing clean and OCV ruggedized. Effectively, composition by abutment eliminates logic and physical synthesis for the end user. Like Lego system, synchoricity does need a finite number of SiLago block types to cater to different types of designs. Global NoCs are important system level design components. In this paper, we show, how with a small library of SiLago blocks for global NoCs, it is possible to automatically synthesize arbitrary global NoCs of different types, dimensions, and topology. The synthesized global NoCs are not only valid VLSI designs, but their cost metrics (area, latency, and energy) are known with post-layout accuracy in linear time. We argue that this is essential to be able to do chip-level design space exploration. We show how the abstract timing model of such global NoC SiLago blocks can be built and used to analyse the timing of global NoC links with post layout accuracy and in linear time. We validate this claim by subjecting the same VLSI designs of global NoC to commercial EDA's static timing analysis and show that the abstract timing analysis enabled by synchoros VLSI design gives the same results as the commercial EDA tools.

During the dimensioning process of hybrid electric propulsion systems, engineers are confronted with a large variety of possible components. A key influence on overall system efficiency is the electric drive system (EDS). Usually, the comparison of different EDS is limited to comparing loss maps and visualizing their differences. Since loss maps are not easy to handle, a simple model of the efficiency characteristics can be helpful to identify the best component for the specific application. This paper proposes a simplified physics-based approach to model the loss characteristics of an EDS based on polynomial functions. The EDS consists of a permanent magnet synchronous machine (PMSM) and an inverter (INV). The developed model achieves good accuracy for both, the base-speed region and the field-weakening region. The modeled losses are dependent on DC-bus voltage in motor as well as in generator mode. The proposed method allows the description of the EDS efficiency characteristic by only few scalar coefficients and increases thereby the comparability of different EDS.

5G brings innovation challenges for the spectra of computing and connectivity technology. Cellular modems, in particular, have to support various services and applications requiring low to high data rates. Therefore, the co-optimization of power and performance for architecture along circuit design is inevitable. In order to meet this challenge, this work presents a modular and distributed setup. It first separates functionality from architecture, and second, the way a power database is attached and integrated makes it practical. A simple use-case presented for the network processor demonstrates the effectiveness of the setup/methodology.

This paper presents the implementation of an ideal battery model using Pspice behavioral-dependent sources, which considering cycle life and rate of discharge effects. The proposed circuit topology models the battery behaviors (e.g., runtime) with low complexity to design portable electronic devices at a system level. The proposed model was simulated in OrCAD PSpice Designer® software using three study cases assuming three battery technologies (i.e., ideal Battery, Li-Ion, Lead-Acid) with constant and pulse (with duty cycle 50%) discharge current under five different discharge average values (i.e., 1C, 2C, 3C, 4C, and 5C). The runtime results present a good agreement between the simulated and theoretical values, with a mean absolute percentage error of 0.554%.

The system-on-chip is the dominant architecture in the age of heterogeneous computing, but its energy-efficient performance comes at the cost of higher design complexity. The open-source hardware movement responds to this challenge by promoting design reuse and collaboration. ESP is an open-source research platform for heterogeneous SoC design that combines a scalable tile-based architecture and a flexible system-level design methodology. Conceived as a heterogeneous integration platform, ESP is naturally suited to foster collaborative engineering of SoC designs across the open-source community.

This paper discusses about Mixed Signal Design Verification Methodology (MSDV) which has been adopted for verifying Ambient Light Sensor (ALS) Interface. Analog sub blocks used within the system are modelled using SystemVerilog. Block level verification is done by performing equivalence checks between Analog schematics and behavioral models with the help of self-checking testbenches. The entire process of block level verification is well automated by means of script-based regressions. System level design constitutes of both analog as well as digital blocks. Traditional mixed mode simulations are time consuming which is mainly due to the huge netlist generated. This limits the number of test scenarios that can be verified. In system level simulations, the above-mentioned drawback can be resolved by choosing between transistor level schematic view or behavioral model view for the analog sub blocks based on the test case targeted. Automation of analog block level verification using regressions reduces the total debug time by 99% which ensures that more test scenarios are covered. Assertions in system level verification are used to check the integrity of analog to digital interface signals. The MSDV methodology adopted here thus offers a faster verification approach and guarantees a bug free and reliable system.

In order to meet time-to-market constraints and to raise the design productivity, High-level Synthesis (HLS) is being increasingly adopted by the semiconductor industry. HLS designs, which can be automatically translated into Register Transfer Level (RTL), are typically written in SystemC at the Electronic System Level (ESL). However, this modern design flow still has weaknesses, in particular, due to the significant manual effort involved for verification and the subsequent debugging process which are both time-consuming and error-prone. In this paper, we propose ASCHyRO, a fully automated semiformal fault localization approach for SystemC HLS designs. ASCHyRO takes advantage of a hybrid rank ordering technique to derive a reduced ordered set of potential fault locations. The reduced order set is obtained by calculating a Confidence Score (CS) for each fault candidate based on a combination of static and dynamic fault probability analysis. Experimental results including an extensive set of standard SystemC HLS designs show the effectiveness of our approach in localizing even multiple faults with high confidence in a short execution time.