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A three-dimensional numerical model is developed to simulate the mold filling behavior in the plastic encapsulation of microchips. The conventional Hele--Shaw approximation is inadequate to analyze a complex molding compound flow behavior with multiple microchips in a single cavity. The developed numerical algorithm is based on the finite difference method combined with the robustness of volume of fluid volume-tracking method to solve the two-phase flow field in complex mold and die geometries. Twelve dies are arranged in a matrix-array in a single mold cavity. Short-shot experimental data are used to validate the numerical results for the melt flow front at different flow times. Close agreement between the experimental data and the numerical results demonstrates the applicability of the present computational model for the simulation of practical epoxy molding compound encapsulation. [DOI: 10.1115/1.4000719] Keywords: epoxy molding compound, Kawamura and Kuwahara technique, Cross model, finite difference method (FDM)

The transverse shear effect has been frequently ignored in determining the debonding-related energy release rate and the phase angle in the blister test, resulting in underestimated values. This study aims to study the effect of shear force on the energy release rate and phase angle prediction in the blister test. A generalized approach is proposed to predict them under the effect of shear force. The predictions show that when the ratio of the film thickness to the debonded film window radius is large (such as 0.05), the transverse shear effect cannot be ignored in determining the energy release rate and the phase angle. The study also further illustrates the importance of including the shear force contribution in estimation and how this importance depends on the film thickness to debonded radius ratio, as well as the elastic mismatch. [DOI: 10.1115/1.4000717] Keywords: delamination, blister test, energy release rate, phase angle, shear effect

The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package. [DOI: 10.1115/1.4001145] Keywords: flip chip BGA package, CTE, chemical cure shrinkage, MVCCM, interface delamination

Stress-induced changes in the electrical characteristics of a semiconductor device become a major concern in the production of semiconductor packages because the electrical characteristics are adversely affected by packaging (residual) stresses. The objective of our project is to evaluate the effects of stress on semiconductor devices. In this study, the shift of the DC characteristics of nMOSFETs during the resin-molding process was investigated experimentally. After a silicon chip including the n-type metal oxide semiconductor field effect transistors (nMOSFETs) was encapsulated in a quad flat package, the drain current variations and the transconductance shifts were measured. The drain current decreased during the resin-molding process while no significant shift in threshold voltage was observed. The experimental results were estimated adequately from the residual stress predicted by numerical and experimental analyses and from the stress-sensitivity of the nMOSFETs measured by the four-point bending method. Also, we tested the validity of an electron-mobility model that included the effect of stress. The electron-mobility model takes into account the variation in the relative occupancy of the electrons in each conduction-band energy valley. It was found that the effect of biaxial stress on the variation in electron-mobility can be qualitatively evaluated by the electron-mobility model but are quantitatively different from the experimental results. Several needed improvements to the electron-mobility model are proposed in this article. [DOI: 10.1115/1.4000718] Keywords: residual stress, piezoresistive gauge, nMOSFET, DC characteristics, electron-mobility

Nonconductive film (NCF) interconnection technology is now being used for the ultrafine pitch interconnections in chip-on-glass (COG) packaging. In comparison to traditional anisotropic conductive film (ACF) technology, NCF can reach less than 10 [micro]m ultrafine pitch interconnection, while ACF just reaches the limit of 30 [micro]m. For NCF interconnection technology used in COG bonding, it needs a higher bonding pressure and temperature than those in ACF bonding, so the warpage is very important for the reliability of the package. In this paper, an exploring study investigated the effects of the structure design and bonding process on the warpage in a COG module. The warpage increased linearly with the increase in bonding head temperature and bonding force, but it decreased with the increase in substrate temperature, substrate thickness, and chip thickness. The large temperature difference between the substrate and chip produced a high thermal stress, and the large bonding force generated a high mechanical stress. The thermal and mechanical stresses were the reasons for warpage in a COG module. For the high reliability, the design and bonding process to the COG module with NCF should adopt a thick substrate, an appropriate bonding force, and a low temperature difference. [DOI: 10.1115/1.4000361] Keywords: nonconductive film (NCF), chip on glass (COG), warpage, the thermocompression bonding

The power dissipation for chip-scale atomic clocks (CSAC) is one of the major design considerations. 12 mW of the 30 mW power budget is for temperature control of the vertical-cavity-surface-emitting laser (VCSEL) and the alkali-metal vapor cell. Each of these must be maintained at 70 +/-0.1[degrees]C even over large ambient temperature variations of 0-50[degrees]C. Thus the physics package of a CSAC device, which contains the vapor cell VCSEL, and optical components, must have a very high thermal resistance, greater than 5.83[degrees]C/m W, to operate in O[degrees]C ambient temperatures while dissipating less than 12 mW of power for heating. To create such a high level of insulation, the physics package is enclosed in a gold coated vacuum package and is suspended on a specially designed structure made from Cirlex, a type of polyimide. The thermal performance of the suspended physics package has been evaluated by measuring the total thermal resistance from a mockup package with and without an enclosure. Without an enclosure, the thermal resistance was found to be 1.07[degrees]C/m W. With the enclosure, the resistance increases to 1.71[degrees]C/m W. These two cases were modeled using finite element analysis (FEA), the results of which were found to match well with experimental measurements. A FEA model of the real design of the enclosed and suspended physics package was then modeled and was found to have a thermal resistance of 6.28[degrees]C/m W, which meets the project requirements of greater than 5.83[degrees]C/m W. The structural performance of the physics package was measured by shock-testing, a physics package mockup and recording the response with a high-speed video camera. The shock tests were modeled using dynamic FEA and were found to match well with the displacement measurements. A FEA model of the final design, not the mockup, of the physics package was created and was used to predict that the physics package will survive a 1800 g shock of any duration in any direction without exceeding the Cirlex yield stress of 49 MPa. In addition, the package will survive a 10,000 g shock of any duration in any direction without exceeding the Cirlex tensile stress of 229 MPa. [DOI: 10.1115/1.4000211]

This paper presents novel modeling methods for accurate and efficient analysis of coupling of multiple vias in finite-sized multilayered parallel-plate structures. The new modeling methods address two open problems related to the modal expansion with the T-matrix method for the analysis of via coupling. First, a novel boundary modeling method, called the frequency-dependent cylinder layer (FDCL), is proposed to resolve the open problem of boundary modeling. In the FDCL, virtual cylinders with dynamic radii are postulated to approximate the original finite-sized boundary of parallel-plate structures. Second, a generalized T-matrix model, which is derived by the mode-matching technique, is created to characterize the coupling effect for vias penetrating more than one layer in a multilayered structure. With the two open problems successfully solved, the modal expansion with the T-matrix method incorporating the FDCL boundary modeling method and the generalized T-matrix model can now be fully utilized for efficient and accurate analysis of finite-sized multilayered parallel-plate structures with a large number of vias. Both numerical and experimental verifications are presented to validate the new modeling methods. Index Terms--Boundary modeling, generalized T-matrix, high-speed electronic package modeling, modal expansion, signal and power integrity, via coupling.

A system in package (SIP) that integrates high-side and low-side MOSFETs and their driver IC has been developed for voltage regulators. Compared with the conventional discrete package, the SiP offers 25% lower power loss because it has low parasitic inductances. The peak drain voltage of the low-side MOSFET during turn-ON of the high-side MOSFET is 45% lower than that of the discrete package, and this improves switching noise characteristics and lowers MOSFET conduction losses because it decreases the MOSFET breakdown voltage. A mixed-mode simulation was performed that indicated the common-source parasitic inductance should be reduced in order to attain low switching loss. To reduce this common-source parasitic inductance, the source pad of the high-side MOSFET is bonded directly to the driver IC with a wire. Index Terms--Low parasitic inductance, packaging, power FETs, voltage regulator (VR).

The design and implementation of package-level electromagnetic-bandgap (EBG) structures is presented. By using spiral-based inductance-enhanced electromagnetic-bandgap structures (IE-EBGs), the relative periodicity for achieving bandgap at extremely low frequencies is substantially reduced in comparison to traditional EBGs. Using both full-wave electromagnetic simulation and experimental characterization, it is demonstrated that this type of structure can exhibit multiple bandgaps, which are individually tunable through variation of the inductance per unit area and/or the unit cell periodicity. Sample structures with dimensions compatible with today's microprocessor packaging technology are designed and fabricated in a multilayer organic flip-chip ball-grid array package substrate. These package-embedded IE-EBGs have unit cell dimensions less than 750 [micro]m and exhibit the first forbidden bandgaps for electromagnetic wave propagation below 10 GHz, which is a frequency band of interest for commercial wireless communication systems. Index Terms--Artificial magnetic conductor, electromagnetic-bandgap (EBG) structures, multichip packaging, multilayer organic package substrate, signal isolation.

A conceptual topology for the integration of antennas in chip packages is proposed. First, the complete topology is presented and discussed. Then, a full antenna design is described, including fabrication and measurement of a scale model of the basic radiating structure. Finally, a numerical study of the shielding capabilities of the conceptual structure is given. Index Terms--Chip packaging, integrated antennas, shielding, small antennas.

This paper presents a thermal design methodology for an integrated power electronic module (IPEM) using embedded, single-phase, and laminar-flow rectangular microchannels. Three-dimensional packaging of electronic components in a small and compact volume makes thermal management more challenging, but IPEMs also offer the opportunity to extract heat from both the top and the bottom side of the module, enabling double-sided cooling. Although double-sided cooling of IPEMs can be implemented using traditional aluminum heat sinks, microchannels offer much higher heat transfer coefficients and a compact cooling approach that is compatible with the shrinking footprint of electronic packages. The overall goal of this work was to find the optimal microchannel configuration for the IPEM using double-sided cooling by evaluating the effect of channel placement, channel dimensions, and coolant flow rate. It was found that the high thermal conductivity copper of the direct bonded copper (DBC) layer is the most feasible location for the channels. Based on a new analytical heat transfer model developed for microchannels in IPEM structures, several design configurations were proposed in this study that employ the microchannels in the copper layers of the top and bottom DBCs. The designs included multiple parallel channels in copper as well as a single wide microchannel. The analytical model was verified using a finite element model and the competing design configurations were compared against a commercial cooler. For a typical IPEM structure dissipating on the order of 100 W of heat, it was concluded that a single microchannel DBC heat sink is preferable to multiple parallel channels under a double-sided cooling configuration, considering thermal performance, pressure drop and fabrication trade-offs. [DOI: 10.1115/1.2957320]

In this letter, the authors present an approach for designing discrete packaging of a bidirectional power switch used in matrix converter applications. The study is based on computing the magnetic field inside a specific resonant switching cell in order to incorporate low-voltage control circuits inside the compact space volume of the power module. The novelty of the proposed configuration is the creation of an oriented magnetic field area, which has very low impact on the low-level control signals of the power devices. Numerical analyses as well as experimental results are presented to demonstrate the validity of the proposed approach. Index Terms--Electromagnetic interference (EMI), power conversion.

The demand for higher clock speed and larger current magnitude in high-performance flip chip packaging configurations of small footprint has raised the concern over rapid thermal transients and large thermal spatial gradients that could severely compromise package performance. This paper explores coupled electrical-thermal-mechanical multi-physics to evaluate the concern and to establish the knowledge base necessary for improving flip chip reliability. It is found that within the first few hundreds of nanoseconds after power-on, there are fast-attenuating, dispersive stress waves of extremely high frequency propagating in the package. The concepts of high cycle fatigue, power density, and joint time-frequency analysis are employed to characterize the waves along with the various damage modes resulting from the propagation of these short-lived dynamical disturbances in bulk materials and along bimaterial interfaces. A qualitative measure for failure is developed to evaluate the extent of damage inflicted by short-time wave motion. Damages identified in this study are in agreement with physical failure modes commonly seen in industry, thus implying that micron scale cracks or interfacial adhesion flaws initiated at the short-time scale would be further propagated by the coefficient of thermal expansion induced thermal stresses at the long-time scale and result in eventual electrical disruptions. [DOI: 10.1115/1.2912188]

The physics explored in this investigation enables short-time scale dynamic phenomenon to be correlated with package failure modes such as solder ball cracking and interlayer debond. It is found that although epoxy-based underfills with nanofillers are shown to be effective in alleviating thermal stresses and improving solder joint fatigue performance in thermal cycling tests of long-time scale, underfill material viscoelasticity, is ineffective in attenuating short-time scale propagating shock waves. In addition, the inclusion of Cu interconnecting layers in flip chip area arrays is found to perform significantly better than Al layers in suppressing short-time scale effects. Results reported herein suggest that, if improved flip chip reliability is to be achieved, the compositions of all packaging constituent materials need be formulated to have well-defined short-time scale and long-time scale properties. Chip level circuit design layout also needs be optimized to either discourage or negate short-time wave propagation. The knowledge base established is generally applicable to high performance package configurations of small footprint and high clock speed. The approach along with the numerical procedures developed for the investigation can be a practical tool for realizing better device reliability and thus high manufacturing yield. [DOI: 10.1115/1.2912209]

In the present work, the potential of using foam structures impregnated with phase change materials (PCMs) as heat sinks for cooling of electronic devices has been numerically studied. Different design parameters have been investigated such as foam properties (porosity, pore size, and thermal conductivity), heat sink shape, orientation, and use of internal fins inside the foam-PCM composite. Due to huge difference in thermal properties between the PCM and the solid matrix, two energy equation model has been adopted to solve the energy conservation equations. This model can handle local thermal nonequilibrium condition between the PCM and the solid matrix. The numerical model is based on volume averaging technique, and the finite volume method is used to discretize the heat diffusion equation. The findings show that, for steady heat generation, the shape and orientation of the composite heat sink have significant impact on the system performance. Conversely, in the case of power spike input, use of a PCM with low melting point and high latent heat is more efficient. [DOI: 10.1115/1.2912185] Keywords: heat sinks, PCM, foams, electronic devices

Light emitting diodes (LEDs) historically have been used for indicators and produced low amounts of heat. The introduction of high brightness LEDs with white light and monochromatic colors has allowed them to penetrate specialty and general illumination applications. The increased electrical currents used to drive the LEDs have resulted in higher heat fluxes than those for average silicon integrated circuits (i.e., ICs). This has created a need to focus more attention on the thermal management engineering of LED power packages. The output of a typical commercial high brightness, 1 m[m.sup.2], LED has exceeded 100 lm at drive levels approaching 3 W. This corresponds to a heat flux of up to 300 W/c[m.sup.2]. Novel thermal solutions need to address system architectures, packaging, phosphors for light color conversion, and encapsulants and fillers for optical extraction. In this paper, the effect of thermal management on packaging architectures, phosphors, encapsulants, and system design are discussed. Additionally, discussions of microscopic defects due to packaging problems as well as chip active layer defects are presented through experimental and computational findings. [DOI: 10.1115/1.2753958]

The disturbed state concept (DSC) with the hierarchical single surface (HISS) plasticity model have been proposed and validated previously for a wide range of problems in electronic packaging. In this paper, detailed analyses are performed with the DSC/HISS model to study the effect of various factors, such as computational and geometrical aspects and material parameters, on the failure life of chip substrate systems. The results and the methodology can be used for parametric analyses and optimal design of problems in electronic packaging. [DOI: 10.1115/1.2753981]

New packaging materials make it possible to produce flexible system in package (SIP) and system on package (SOP) modules. However, in these the integrated circuits are exposed to increased mechanical stresses. The stresses may become even more severe when thinned chips are used. The effect of mechanical stress on the characteristics of on-wafer capacitors was studied. The mechanical stress increased clearly the resonance frequency of poly-insulator-poly capacitors, but caused only minor impedance changes for metal-insulator-metal capacitors. No fatal stress-induced phenomenon was found and the on-wafer capacitors should also operate correctly in SIP and SOP modules. The test chips were processed with two different complementary metal oxide semiconductor processes and the tested on-wafer capacitors had values of 4.8-47 pF. [DOI: 10.1115/1.2753918] Keywords: CMOS, capacitor, stress

This study aims to enhance the flow rate and reduce the filling time in flip-chip underfill packaging by combining capillary force, pressure difference, and inertia effects. In the designed underfill apparatus, the capillary force effect is developed by surface tension, the pressure difference between the inlet and the outlet is established using a pump or a vacuum, and the inertia force is achieved via circular rotation. The governing equations containing the three analyzed effects are derived and solved using a dimensionless technique. The analytical results indicate that for the general gap height of approximately 10-1000 [micro]m, the pressure difference and inertia effects dominate the driving force and provide a significant reduction in the filling time. However, for a gap height of less than 1 [micro]m, the driving force is dominated by the capillary effect. The present results confirm that the productivity of the flip-chip underfill packaging process can be enhanced through the appropriate control of the capillary force, pressure difference, and inertia effects. [DOI: 10.1115/1.2429709] Keywords: flip-chip packaging, underfill, capillary force, pressure difference, rotation

The ball impact test is developed as a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. Following classical structural dynamics principles, the ball impact test process is analyzed to provide insights into transient characteristics of this particular test methodology. A design guideline for the ball impact test apparatus based on characteristics of the measured impact force profile is proposed. [DOI: 10.1115/1.2429716] Keywords: ball impact test (BIT), solder joint, structural dynamics, transient structural responses, design guideline

Interfacial failure under thermal cycling conditions is one of the main concerns in package design, To minimize such failure in multi-layered electronic assemblies and packages, it is important to develop a better understanding of the reliability at a molecular level. In this paper, molecular dynamics (MD) simulations were conducted to investigate the interfacial energy of the epoxy molding compound (EMC) cuprous oxide system during the thermal cycling test. In order to investigate the effect of the cuprous oxide content in the copper substrate on the interfacial adhesion, two kinds of MD models were examined in this study. The results revealed that the cuprous oxide content in the copper substrate had a large effect on the interfacial adhesion between the EMC and copper, which is consistent with the experimental observation. [DOI: 10.1115/1.2429707] Keywords: delamination, thermal cycling, molecular dynamics, cuprous oxide content, interfacial adhesion

The importance of power cycling as a mean of reliability assessment was revisited for flip chip plastic ball grid array (FC-PBGA) packages. Conventionally, reliability was addressed empirically through accelerated thermal cycling (ATC) because of its simplicity and conservative nature of life prediction. It was well accepted and served its role effectively for ceramic packages. In reality, an assembly is subjected to a power cycling, i.e., nonuniform temperature distribution with a chip as the only heat source and other components as heat dissipaters. This non-uniform temperature distribution and different coefficient of thermal expansion (CTE) of each component make the package deform differently than the case of uniform temperature in ATC. Higher substrate CTE in a plastic package generates double curvature in the package deformation and transfers higher stresses to the solder interconnects at the end of die. This mechanism makes the solder interconnects near the end of die edge fail earlier than those of the highest distance to neutral point. This phenomenon makes the interconnect fail earlier in power cycling than ATC. Apparently, we do not see this effect (the die shadow effect) in ceramic packages. In this work, a proper power cycling analysis procedure was proposed and conducted to predict solder fatigue life. An effort was made for FC-PBGA to show the possibility of shorter fatigue life in power cycling than the one of ATC. The procedure involves computational fluid dynamics (CFD) and finite element analyses (FEA). CFD analysis was used to extract transient heat transfer coefficients while subsequent FEA-thermal and FEA-structural analyses were used to calculate temperature distribution and strain energy density, respectively. [DOI: 10.11151/1.2429706] Keywords: power cycling, FEA, CFD, flip chip PBGA, ATC, ANSYS, ICEPAK

As the electronic packaging industry develops technologies for fabrication of smaller, faster, economical and reliable products, thermal management and design play an important role. Temperature fluctuations caused by either power consumption or environmental changes, along with the resulting thermal expansion mismatch between the various packages materials result in deformation stresses in packages/assemblies especially in solder interconnects. Increased power dissipation and density in modern electronics system requires efficient and intelligent design and thermal management strategies to ensure the reliability of electronic products. In the past reliability issues related to optimization of electronic packages were dealt with by coupling analysis tools with optimization solvers. In this paper, ANSYS APDL code is used with a built-in optimization tool for optimization of electronic packages, and for improving the solder joint life and arriving at optimal design. It has been shown that, design optimization would enormously decrease the lead time. The finite element tool ANSYS is used to estimate the cycles to fatigue failure of solder joint of the package coupled with optimization module present in the solver for providing the details on determining optimal design parameters that affect the product reliability. Four model characteristics: printed wiring board (PWB) core in-plane Young's modulus, PWB core in-plane coefficient of thermal expansion, PWB core thickness, and the standoff solder joint height are chosen as the optimization inputs (design variables) that ensure higher reliability and improved performance of the assembled product. The objective junction of the paper is to minimize average plastic work to improve the fatigue life of solder joints of the package. Subapproximation, design of experiment and central composite design based response surface modeling methodologies are used to study the effects of each design variables on the fatigue life. [DOI: 10.1115/1.2429704]

Heat transfer in turbomachinery has been well established due to the long history of research in the field. A vast amount of research has been devoted to obtain flow fields and regimes, heat transfer modes, surface effects, and heat transfer enhancement techniques. Since most of the flows are in the turbulent regime of air cooling, various heat transfer enhancements such as turbulators, pin fins, concavities, and lattice cooling have been investigated. The electronics industry has shown a rapid increase in the functionality, speed, and the density of transistors, leading to a large increase in the required heat transfer. Most of the flows are in the transitional regime. Heat sinks are the primary choice for thermal management in electronics systems. Enhancements in heat sinks have been limited to taller and tighter fin spacing, while decreasing the weight and the cost. Current state-of-the-art for heat sinks in electronics components is lacking in heat transfer enhancement technologies, which is common in turbine heat transfer practice. Therefore, the primary goal of this paper is to examine the turbomachinery cooling technologies and to inform the packaging engineers about the thermal technologies on the other side of the thermal world. [DOI: 10.1115/1.2229219]

This investigation addresses the thermogeometric performance of a two-square cavity system contrasted against a two-isosceles triangular cavity system, with an exactly equal heating segment and comparable cooling segment. When one square cavity is cut diagonally in hall it results in a pair of isosceles triangular cavities. The isosceles triangular cavity on the left is heated from the left vertical wall, the top wall is insulated, and the inclined wall is cold; the so-called HIC triangular cavity. The isosceles triangular cavity on the right is heated from the right vertical wall, the bottom wall is insulated, and the inclined wall is cold; the so-called HCI triangular cavity. It may be speculated that the two-isosceles triangular cavity system may find application in the miniaturization of electronic packaging severely constrained by space and/or weight. The finite volume method, accounting for temperature-dependent thermophysical properties of air, is employed to perform the computational analysis. Representative height-based Rayleigh numbers assume values up to [10.sup.6] to avoid oscillations that occur at a Rayleigh number between [Ra.sub.H]=2 X [10.sup.6] and 2.2 X [10.sup.6]. Numerical results are reported for the velocity field, the temperature field, and the local and the mean convective coefficient along the heated vertical wall. Under a dominant conduction condition for [Ra.sub.H]= [10.sup.3], the heat flux across the derived two-isosceles triangular system is 334% higher than its counterpart across the original two-square system. In contrast, for a dominant convection condition for [Ra.sub.H]= [10.sup.6], this margin diminishes to 20%, but still constitutes a significant improvement. For the design of two-triangular cavity systems, a [Nu.sub.H] correlation equation has been constructed yielding a maximum error of 2% at [Ra.sub.H]= [10.sup.4]. [DOI: 10.1115/1.2229224]

Our goals in this paper are to develop and demonstrate a computationally efficient methodology for assessing the effect of circuit board warpage, component warpage, and solder volume variation on the shape of the solder joints in area array packages. The effect of warpage is analyzed using a two-step procedure in the present paper. In the first step, the restoring forces and moments (in the molten state of solder droplet) that result from a given solder joint height, solder material volume, pad diameter, and pad inclination are predicted using the surface tension theory. In the second step of the analysis, the forces and moments at individual solder joints caused by varying solder heights and pad tilts are combined to predict the equilibrium configuration of the package. A program written in the MATHEMATICA[R] environment was developed to implement the above-described methodology. The developed procedure was validated on an experimental test vehicle with nine solder joints. The heights of solder joints computed by the program matched the experimentally measured heights to within [+ or -]5% error. Further, the general capabilities of the modeling procedure are demonstrated by assuming complex combinations of package and PCB warpage. [DOI: 10.1115/1.2227058]

A fundamental understanding of the dynamics of the PCB assembly when subjected to a half-sine acceleration has also been obtained through analyzing the PCB as a spring mass system, a beam, and a plate, respectively. The magnitude of stresses in the solder interconnection due to flexing of the PCB is two orders higher than the magnitude of the stresses induced by acceleration and inertia loading the IC package. By ignoring the inertia loading, computational effort to evaluate the interconnection stresses due to PCB flexing can be reduced significantly via a two-step dynamic-static analysis. The dynamic analysis is first performed to evaluate the PCB bending moment adjacent the package, and is followed by a static analysis where the PCB bending moment is applied around the package. Parametric studies performed suggest a fundamental difference in designing for drop impact and designing for temperature cycling. The well-known design rules for temperature cycling--minimizing package length and maximizing interconnection standoff--does not work for drop impact. Instead, drop impact reliability can be enhanced by increasing the interconnection diameter, reducing the modulus of the interconnection materials, reducing the span of the PCB, or using either a very thin or a very thick PCB. [DOI: 10.111511.2065747] Keywords: electronic packaging, drop impact, finite element, parametric studies

In electronics packaging, one of the key processes is dispensing fluid materials, such as adhesive, epoxy, encapsulant, onto substrates or printed circuit boards for the purpose of surface mounting or encapsulation. In order to precisely control the dispensing process, the understanding and characterization of the flow behavior of the fluid being dispensed is very important, as the behavior can have a significant influence on the dispensing process. However, this task has proven to be very challenging due to the fact that the fluids for electronics packaging usually exhibit the time-dependent rheological behavior, which has not been well defined in literature. In the paper a study on the characterization of the time-dependent rheological behavior of the fluids for electronics packaging is presented. In particular, a model is developed based on structural theory and then applied to the characterization of the decay and recovery of fluid behavior, which happen in the dispensing process due to the interruption of process. Experiments are carried out to verify the effectiveness of the model developed. [DOI: 10.1115/1.2056568]

More wires in a package and smaller wire gaps are the trend in the integrated circuit (IC) packaging industry. The effect of wire density is becoming increasingly apparent, especially on the flow pattern of the epoxy molding compound during the molding process and, hence, on the amount of wire sweep. In most mold flow simulations, the wire density effect is ignored. In order to consider the wire density effect on the predicted amount of wire sweep in the analysis, several indirect approaches were used by researchers before. But those approaches were not general enough to be applied to all cases. This paper presents a more direct and convenient approach to consider wire density effect by including wires in the mesh model for three-dimensional (3D) mold-filling analysis. A thin small outline package (TSOP) with 53 wires is used as the demonstration example, and all the wires are modeled in the 3D mesh. By comparison with experimental results, it is shown that this approach can accurately describe the wire density effect. When the wires are included in the mesh model, the predicted wire sweep results are better than those without considering the wire density effect. [DOI: 10.1115/1.1939028] Keywords: Wire Density Effect, Wire Sweep, Mold-Filling Analysis, Transfer Molding, Plastic Packaging of ICs, Plastic Encapsulation

Laser hammering (LH) is a process used in the manufacturing of butterfly optoelectronic packages to correct laser-to-fiber misalignment that occurs when the semiconductor lasers are welded in place. High-power, precisely positioned pulsed lasers are used in LH to induce deformation of the fiber support housing to, in turn, induce realignment. A thermomechanical modeling study of LH is reported in this paper, which focuses on the degree to which a steady-state model can predict the asymptotic state of a transient response subjected to a periodic laser excitation. A baseline, two-dimensional fiber mounting/ferrule geometry is employed in a finite element analysis simulation case study. Various laser wave forms are applied to focus spot location sizes of 50 and 200 [micro]m over a range of applied heat fluxes (10-1000 W/[mm.sup.2]). Effects of laser energy deposition location, as well as the use of multiple lasers, are also studied. The results show that the steady-state solution is in good agreement with the asymptotic transient response for horizontal fiber displacement and fiber temperature. The laser focus spot surface temperature predictions are also found to be in reasonable agreement. However, the vertical fiber displacement tends to be overpredicted by the steady-state solution, sometimes by as much as an order of magnitude. The causes, both physical and computational, of this disagreement are discussed. [DOI: 10.1115/1.1938206]

Ball grid array solder joint reliability is known to be dependent on the shape of solder joints after reflow. To ensure good solder joint formation and prevent solder bridging, it is critical to understand the amount of paste volume needed during assembly and reflow. The final shape of the solder joint is a function of surface tension, wetting area, gravin, and applied forces. In this paper, a new methodology to simulate solder joint shape is presented. Large deformation viscoplastic finite element analysis is used to simulate incompressible fluid flow. A numerical model for surface tension is outlined and validated with closed-form solutions. The results of the numerical model are compared to other known solder joint shape prediction methods. The effects of package weight, coplanarity, warpage, paste volume, pad misregistration, and joint construction on solder joint shape are then analyzed. Recommendations are provided on ways to maximize standoff height and avoid bridging. Finally, the formation of leadless solder joints is studied and compared to experimental data. [DOI: 10.1115/1.1938985] Keywords: Ball Grid Array, Coplanarity, Eutectic Solder, Finite Element Analysis, High Lead Solder, Hydrostatic Pressure, Leadless, Microelectronics, Micro Lead Frame, Packaging, Perzyna, Rigid Plastic, Solder Joints, Shape, Standoff Height, Surface Evolver, Viscoplastic, Von Mises, Warpage

To give a proper and accurate estimation of the fatigue life of ball grid array (BGA) solder joints, a mechanical fatigue test method under mixed-mode loading is proposed. Experiments were conducted with 63Sn/37Pb and Sn/3.5Ag/0.75Cu solder joints in room temperature. The mechanical low cycle fatigue tests were performed under several loading angles. The loading angle is controlled by several grips which have specific surface angle to the loading direction. Constant displacement controlled tests are performed using a micro-mechanical test apparatus. It was found that the normal deformation significantly affects the fatigue life of the solder joint. Throughout the whole test conditions at room temperature, Sn/3.5Ag/0.75Cu solder alloy had longer fatigue life than 63Sn/37Pb alloy. Failure patterns of the fatigue tests were observed and discussed. A morrow energy model was examined and found to be a proper low cycle fatigue model for solder joints under mixed mode loading condition. [DOI: 10.1115/1.1871192] Keywords: Electronic Packaging, Ball Grid Array (BGA), Solder Joints, Low Cycle Fatigue, Mixed-Mode Loading

The data retention degradation of a 256-Mbit DRAM during the packaging process is investigated. The retention time of the degraded chip is strongly dependent on the negative wordline voltage and operation temperature but less sensitive to the substrate bias.

Various methodologies of wire sweep analysis have been introduced to get better prediction and matching the experimental measurements by many researchers. As more and more high pin-count packages (such as BGA, QFP) are used today, efficiency has become an important requirement besides accuracy for software used to predict wire sweep in IC packaging. This study introduces a newly developed wire sweep analysis solution (In-Pack), not only to meet the need of accuracy, but also enhance the efficiency for actual applications. It combines global flow analysis (C-MOLD) and structure analysis (ANSYS) to become a solution for general wire sweep analysis. [DOI: 10.1115/1.1535447]

A study was conducted on a new plastic air cavity encapsulation process for packaging a multi-gigabit limiting amplifier integrated circuit that was implemented with AlGaAs/GaAs heterojunction bipolar transistors. The packaging process involves the use of an alpha-staged thermally setting epoxy which is in the form of an uncured gel. Its overall yield was over 99% when subjected to the industry standard condition 'c' gross leak test.

In this paper, we first present a mathematical method that can be used to predict the eutectic solder fillet shape for ceramic ball grid array joints. An underlying assumption is that the solder fillets on both the module and the card sides can be represented as arcs. The fillets' profiles are then calculated for the factors affecting the shape including solder volume, pad size, solder ball size, the wetting angle between eutectic solder and solder ball, and the gap between solder ball and pad. The second part of the paper focuses on design for reliability and investigates the effect of the interactions between the card-side and the module-side solder fillets on CBGA solder joint reliability. To this end, a central composite design of experiment is set up to systematically vary the pad size and the eutectic solder volume on both the module and the card sides. For each of the design settings, the proposed mathematical method is used to calculate the solder fillet shape. Using ABAQUS and the modified Coffin-Manson relationship, the mean fatigue life is predicted. The implications of the simulations are discussed. In addition, a response surface model is presented to find the optimum settings for maximum reliability. Finally, a comparison is made for the fatigue life predictions obtained using the proposed mathematical method and the linear solder fillet assumption.

The tape automated bonding using anisotropic conductive adhesive is commonly used for packaging large liquid crystal displays. However, there is a trend towards the use of chip-on-glass technology to increase the packaging density and reduce the material requirement. The technology basically involves flip-chip techniques using different adhesives. Techniques using non conductive, anisotropic and isotropic conductive adhesives are described.

In this paper the impact of the state of barrel-laminate adhesion on the PTH and via stresses is investigated. A representative PTH and a representative blind via in a printed wiring board are used as demonstration vehicles. Transient heat conduction and nonlinear elastic-plastic-contact finite element analyses are carried out on PTHs and vias under the extreme conditions of perfect and zero barrel-laminate adhesion. In general, the maximum equivalent plastic strains in PTHs and vias with strong barrel-laminate adhesion are not large enough to fracture the plating. Fracture is possible at or near the innerplane junction when barrel-laminate adhesion is lost. The possibility of plating fracture in a blind via is strongly dependent on the tolerances in manufacturing process parameters such as drill depth and laminate thickness.

In this study, the wire-sweep problem has been studied by performing experiments using a commercial-grade epoxy molding compound, a real chip assembly, and an industrial encapsulation process. After encapsulating the chip, the deformed wire shape inside the plastic package has been determined by X-ray scanning. A procedure for the wire-sweep calculation during encapsulation process has been developed. The wire sweep values have been calculated using this procedure with material properties measured from experiments. The calculated wire-sweep values are compared with experimental values measured at different mold temperatures, fill times, and cavities. In most cases, the calculated values are in good agreement with the experimental values.

The automated search techniques from the field of numerical optimization provide tools that enable optimal design of electronic packages in general, and solder joints in particular. However, there is considerable difficulty in using these procedures for solder joints since the estimation of fatigue life is computationally very expensive. In this paper, global approximation schemes based on designed experiments, linear regression models, and artificial neural network models are developed to approximate the fatigue life as a function of solder joint design parameters. Since these approximate surfaces are inexpensive to evaluate, their use with the numerical optimization techniques leads to a computationally efficient method for optimizing electronic packages. The developed techniques are demonstrated using the 225 I/0 Plastic Ball Grid Array (PBGA) package, manufactured by Motorola, Inc. An exact optimization of the solder joints (without approximations) is also carried out and used as a basis for comparing the accuracy and efficiency of the developed methods.

A method wherein the microlens is directly attached to the laser for an almost self-aligned and self-supported packaging is proposed. The configuration and the high index of the lens make the packaging scheme highly resistant to fabrication and alignment errors and extremely compact. An almost diffraction-limited collimated beam with 0.7 degree divergence and low sidelobe intensities has been observed for mass-transported GaP spherical microlenses packaged to InGaAs-AlGaAs ridge-waveguide lasers.

A packaging technique utilizes silica based planar lightwave circuit to design and fabricate an optical 90 degree-hybrid balanced receiver for a homodyne detection system. The fabricated receiver exhibits a broadband frequency response 14-GHz for a 10-Gb/s homodyne detection. Moreover, the receiver employs microsolder bumps for photoreceiver fabrication and an impedance matched film carrier technique for electrical interconnections. The structural features, design, fabrication, and assembly of the receiver are detailed.

A new technology, active packaging (AP), helps implement ultra-fast InP heterojunction bipolar transistors (HBTs) on a thin silicon chip. The AP technology enables the integration of III-V device structures with the silicon integrated semiconductor circuitry on a single substrate. AP technology also helps implement submillimeter and millimeter phase antenna arrays for beam steering.