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FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively. [ABSTRACT FROM AUTHOR]

This paper aims to outline the effectiveness of modern universal gate quantum computers when utilizing different configurations to solve the B-SAT (Boolean satisfiability) problem. The quantum computing experiments were performed using Grover's search algorithm to find a valid solution. The experiments were performed under different variations to demonstrate their effects on the results. Changing the number of shots, qubit mapping, and using a different quantum processor were all among the experimental variables. The study also branched into a dedicated experiment highlighting a peculiar behavior that IBM quantum processors exhibit when running circuits with a certain number of shots. [ABSTRACT FROM AUTHOR]

Designing distributed filter circuits (DFCs) is complex and time-consuming, involving setting and optimizing multiple hyperparameters. Traditional optimization methods, such as using the commercial finite element solver High-Frequency Structure Simulator to enumerate all parameter combinations with fixed steps and then simulate each combination, are not only time-consuming and labor-intensive but also rely heavily on the expertise and experience of electronics engineers, making it difficult to adapt to rapidly changing design requirements. Additionally, these commercial tools struggle with precise adjustments when parameters are sensitive to numerical changes, resulting in limited optimization effectiveness. This study proposes a novel end-to-end automated method for DFC design. The proposed method harnesses reinforcement learning (RL) algorithms, eliminating the dependence on the design experience of engineers. Thus, it significantly reduces the subjectivity and constraints associated with circuit design. The experimental findings demonstrate clear improvements in design efficiency and quality when comparing the proposed method with traditional engineer-driven methods. Furthermore, the proposed method achieves superior performance when designing complex or rapidly evolving DFCs, highlighting the substantial potential of RL in circuit design automation. In particular, compared with the existing DFC automation design method CircuitGNN, our method achieves an average performance improvement of 8.72%. Additionally, the execution efficiency of our method is 2000 times higher than CircuitGNN on the CPU and 241 times higher on the GPU. [ABSTRACT FROM AUTHOR]

The slowdown of Moore's Law necessitates an exploration of novel computing methodologies, new materials, and advantages in chip design. Thus, carbon-based materials have promise for more energy-efficient computing systems in the future. Moreover, sustainability emerges as a new concern for the semiconductor industry. The production and recycling processes associated with current chips present huge environmental challenges. Electronic waste is a major problem, and sustainable solutions in computing must be found. In this review, we examine an alternative chip design based on nanocellulose, which also features semiconductor properties and transistors. Our review highlights that nanocellulose (NC) is a versatile material and a high-potential composite, as it can be fabricated to gain suitable electronic and semiconducting properties. NC provides ideal support for ink-printed transistors and electronics, including green paper electronics. Here, we summarise various processing procedures for nanocellulose and describe the structure of exclusively nanocellulose-based transistors. Furthermore, we survey the recent scientific efforts in organic chip design and show how fully automated production of such a full NC chip could be achieved, including a Process Design Kit (PDK), expected variation models, and a standard cell library at the logic-gate level, where multiple transistors are connected to perform basic logic operations—for instance, the NOT-AND (NAND) gate. Taking all these attractive nanocellulose features into account, we envision how chips based on nanocellulose can be fabricated using Electronic Design Automation (EDA) tool chains. [ABSTRACT FROM AUTHOR]

Technology mapping is an essential process in the Electronic Design Automation (EDA) flow which aims to find an optimal implementation of a logic network from a technology library. In application-specific integrated circuit (ASIC) designs, the non-linear delay behaviors of cells in the library essentially guide the search direction of technology mappers. Existing methods for cell delay estimation, however, rely on approximate simplifications that significantly compromise accuracy, thereby limiting the achievement of better Quality-of-Result (QoR). To address this challenge, we propose formulating cell delay estimation as a regression learning task by incorporating multiple perspective features, such as the structure of logic networks and non-linear cell delays, to guide the mapper search. We design a learning model that incorporates a customized attention mechanism to be aware of the pin delay and jointly learns the hierarchy between the logic network and library through a Neural Tensor Network, with the help of proposed parameterizable strategies to generate learning labels. Experimental results show that (i) our proposed method noticeably improves area by 9.3% and delay by 1.5%, and (ii) improves area by 12.0% for delay-oriented mapping, compared with the well-known mapper. [ABSTRACT FROM AUTHOR]

Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called "glitches". Electronic Design Automation (EDA) software considers inertial gate delays and represses a glitch in the cell's output if its width is below a threshold. Selecting threshold values for the inertial glitch classification and filtering is crucial for precise power estimations. In this direction, we explore the effectiveness of automatically adjusting such thresholds on a cell-specific basis according to the local cell's information. We used a commercial industry-standard gate-level power estimation tool and a 32 nm CMOS standard cell library. Via power measurements in circuit simulations, we created customized lookup tables for each library cell employed in the benchmark circuits. We compared the proposed approach's performance with other methods for glitch threshold definition. Our method demonstrated good power estimation accuracy while presenting the lowest mean absolute error among all the cells of the circuits under test and the smallest standard deviation. The latter suggests that the proposed method achieves better cell-specific accuracy, which is expected to allow for more precise circuit-level power estimations in complex circuits with a large number of combinational cells. [ABSTRACT FROM AUTHOR]

This research paper demonstrates behavior of memristor emulator circuit at various input frequencies. It is a critical circuit having a vast potential for constructing digital and analog circuits, FM-to-AM converters, filters, cellular neural networks, sensors, analog circuits, and chaotic oscillators are all designed with memristor circuits. It has some unique properties such as nonlinear behaviour, analog signal processing, adaptive and reconfigurable system, memory and state retention and also high density and low power consumption. These properties build the communication system more reliable secure and more efficient. To enhance the design of the memristor model, implementation doing using analog multiplier and operational transconductance amplifier with a constant transcoductance gain is employed. In addition to the input supply voltage frequency (f) and amplitude (Vm), the operational transconductance amplifier provides a control parameter known as the transconductance (gm). Modifications in amplitude have an impact on memory resistance, and variations in biassing voltage influence transconductance (gm) of OTA. The research shows memristor-based chaotic circuit use for secure transmission system. The operational frequency that exhibits the maximum value is 10 kilohertz, accompanied by a power dissipation of 24.1 microwatts with noise 51.9 nV / Hz 1 / 2 at room temperature. This study employs a circuit electronic design automation (EDA) tool to demonstrate the behavior of a memristor circuit under varying input conditions. [ABSTRACT FROM AUTHOR]

This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design for the decryption of the AES depends on the synthesizable hardware description language (HDL) code development for all 10 rounds of processes with the key expansion algorithm. The lookup tables (LUTs) are used for the inverse S-box in the HDL code. The proposed SOC is designed using the Cadence electronic design automation (EDA) tools by making use of the synthesized HDL code for the proposed methods and analyzed for the very large-scale integration (VLSI) parameters. [ABSTRACT FROM AUTHOR]

With the increasing complexity of integrated circuit design, the threat of a hardware Trojan (HT) is becoming more and more prominent. At present, the research mainly focuses on the detection of HTs, but the amount of research on the diagnosis of HTs is very small. The number of existing HT diagnosis methods is generally completed by detecting the HT nodes in the netlist. The main reason is the lack of consideration of the integrity of HTs, so the diagnosis accuracy is low. Based on the above reason, this paper proposes two implanted node search algorithms named layer-by-layer difference search (LDS) and layer-by-layer grouping difference search (LGDS). The LDS algorithm can greatly reduce the search time, and the LGDS algorithm can solve the problem of input node disorder. The two methods greatly reduce the number of nodes sorting and comparing, and therefore the time complexity is lower. Moreover, the relevance between implanted nodes is taken into account to improve the diagnosis rate. We completed experiments on an HT diagnosis; the HT implantation example is from Trust-Hub. The experimental results are shown as follows: (1) The average true positive rate (TPR) of the diagnosis using KNN, RF, or SVM with the LDS or LGDS algorithm is more than 93%, and the average true negative rate (TNR) is 100%. (2) The average proportion of implanted nodes obtained by the LDS or LGDS algorithm is more than 97%. The proposed method has a lower time complexity compared with other existing diagnosis methods, and the diagnosis time is shortened by nearly 75%. [ABSTRACT FROM AUTHOR]

The expeditious development of the technologies result in immeasurable growth in Integrated Circuit chips. The on-chip communication description plays a major role in connection and management of the functional blocks of the system on chip. The Advanced eXtensible Interface (AXI) and AXI Coherence Extension are the two protocols introduced in the later version of AMBA. AXI4 is the high speed bus which has five channels for write and read operation with handshaking mechanism for control transmission. ACE have three channels in addition to the existing channels in AXI4 for cache coherence. This work focuses on the design and analysis of AXI4 and ACE protocols using Verilog language and test bench environment with help of the system Verilog environment. The functional verification of AXI and ACE interconnects, simulation waveforms developed using Cadence Xcelium EDA (Electronic Design Automation) tool and explored as per expectation without any change in the features of DUT (Design Under Test).The design is verified for both 16 bytes and 256 bytes per transfer providing 4 transfers and 4 bytes per transfer for transferring 16 bytes in a single transaction and providing 16 transfers and 16 bytes per transfer for transferring 256 bytes in a single transaction. Thus, the work shows that ACE protocol supports the snooping concept additionally to overcome cache coherence problem along with the features of AXI protocol. The environment completely encloses the DUT while monitoring those protocol's performance. The key benefit of creating a system Verilog testbench is that verification engineers will spend less time in verifying the design since the testbench is reusable. The features of this protocol help in improving the bandwidth and latency of data transfers and transactions during the communications between the peripherals. [ABSTRACT FROM AUTHOR]

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the I – V characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes. [ABSTRACT FROM AUTHOR]

Printed Circuit Board overheating is a problem that can be present in the power supply section of electronic equipment. Due to the negative impact this problem can have on the performance and reliability of the device, it must receive dedicated attention from the early stages of system design. Using Electronic Computer-Aided Design tools, ECAD, to simulate the PCB facilitates the inclusion of thermal requirements during the design process. This work presents the analysis of PCB design alternatives for a power supply to manage the temperatures dissipated in the circuit, to reduce self-heating and the size of the PCB. Results indicate that with the proposed analysis it is possible to obtain a greater performance and reliability design. [ABSTRACT FROM AUTHOR]

Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs. [ABSTRACT FROM AUTHOR]

The typical Integrated Circuit (IC) development process commences with formulating specifications in natural language and subsequently proceeds to Register Transfer Level (RTL) implementation. RTL code is traditionally generated through manual efforts, using Hardware Description Languages (HDL) such as VHDL or Verilog. High-Level Synthesis (HLS), on the other hand, converts programming languages to HDL; these methods aim to streamline the engineering process, minimizing human effort and errors. Currently, Electronic Design Automation (EDA) algorithms have been improved with the use of AI, with new advancements in commercial (such as ChatGPT, Bard, among others) Large Language Models (LLM) and open-source tools presenting an opportunity to automate the chip design process. This paper centers on the creation of AI by AI, a Convolutional Neural Network (CNN) IC entirely developed by an LLM (ChatGPT-4), and its manufacturing with the first fabricable open-source Process Design Kit (PDK), SKY130A. The challenges, opportunities, advantages, disadvantages, conversation flow, and workflow involved in CNN IC development are presented in this work, culminating in the manufacturing process of AI by AI using a 130 nm technology, marking a groundbreaking achievement as possibly the world's first CNN entirely written by AI for its IC manufacturing with a free PDK, being a benchmark for systems that can be generated today with LLMs. [ABSTRACT FROM AUTHOR]

This article explores the evolution of integrated circuits (I C s) , highlighting the fundamental role of open source Electronic Design Automation (EDA) tools in their development. It describes the IC's design flow, differentiating between Front-end and Back-end design stages, and details the process of implementing the digital stage in offset quadrature phase-shift keying (OQPSK) modulation in an IC, including its hardware description language (HDL), the implementation test in the field-programmable gate array (FPGA), and the physical layout using the first manufactured open source process design kits (PDKs) in Global Foundries' 180 nm, as well as the use of OpenLane and Caravel. To conclude, the results of the physical tests obtained from the digital modulation are presented, as well as the performance of the raised cosine shaping filter. [ABSTRACT FROM AUTHOR]

Since the AI 'architectural explosion' of 2022, and as things have become clearer but have not yet settled down, a whole raft of possibilities for creativity and commercial exploration are emerging. Architectural and urban designer Wanyu He explains some of these opportunities, and also reminds us of the ethical and societal concerns about this technology – its biases and blindnesses – which must be addressed before these new approaches can be applied equitably. [ABSTRACT FROM AUTHOR]

A faulty Through Silicon Via (TSV) could spoil a 3D IC and cause hefty loss as the potentially expensive known-good-dies bonded together must be discarded. This work presents a Fault-tolerant TSV scheme to avoid such a disastrous situation. Our method uses two differential TSVs for each binary signal to be transmitted. Compared to the previous Fault-tolerant TSV schemes, our test and repair scheme is not only instant and much more simplified, requiring no global test result analysis and complex reconfiguration process, thereby making it especially suitable for some situations when the more involved TSV test and repair schemes cannot be easily supported by some die providers in multi-vendor 3D-IC design environment. [ABSTRACT FROM AUTHOR]

The challenges of conventional semiconducting electronics, such as dark silicon, memory wall, and stagnant clock frequency motivate the search for alternative computing technologies. Superconductive electronics (SCE) represents one of the most advanced beyond-CMOS technologies, with the potential of revolutionizing high-performance computing. In this review, the advancements of SCE over the past 25 years are presented. Novel logic families, circuit design techniques, and electronic design automation tools for SCE circuits are described. Eventually, future advancements in SCE are discussed from circuit and system design perspective. [ABSTRACT FROM AUTHOR]

This article presents a genetic algorithm‐based technique for microwave integrated distributed amplifier synthesis. To speed‐up synthesis, only linear characteristics are used in the goal function. The technique uses MMIC foundry process design kit models providing manufacturing‐ready schematics to be found. The models from the process design kit are presented as S‐parameters again to enhance algorithm performance. The technique allows searching among most of the existing schematics of the microwave distributed amplifier but is not limited to typical topologies. The section number is theoretically unlimited and makes it possible to find principally new circuit topology. The synthesis shortens and simplifies the distributed amplifier design time. Experimental validation of the technique is carried out by synthesizing the broadband driver stage for the 20–30 GHz buffer amplifier. The technique produces several amplifier topologies meeting the requirements. The most appropriate circuit was manufactured using a commercial 0.25 μm GaAs pHEMT process. The manufactured buffer amplifier demonstrates a gain of 10 dB and 20 dBm output power at a 1 dB compression point. [ABSTRACT FROM AUTHOR]

At nanometer technology nodes, the efficient signal integrity and performance assessment of vast on-chip interconnects are crucial and challenging. For a long time, copper (Cu) has been used as an interconnect material in integrated circuits (ICs). However, as heading towards lower technology nodes, Cu is becoming inadequate to satisfy the requirements for high-speed applications due to its physical limitations. To mitigate this issue, a multiwall carbon nanotube bundle (MWCNTB) is proven to be a better replacement for Cu. Hence, the current work innovatively focuses on modeling, analysis, and performance evaluation of MWCNTB interconnects at 32 nm technology nodes using various machine learning (ML) and neural network (NN) based techniques for signal integrity assessment and fast computation of on-chip interconnect design. Based on the results obtained by comparing the different performance parameters, it is envisaged that NN-based ADAM technique leads to the best-suited model. The developed model is fruitful in evaluating the output performance of the system, such as power-delay-product (PDP), performing parametric analysis, and predicting optimum input design parameters of the driver-interconnect-load (DIL) system. This work utilizes HSPICE and Python electronic design automation tools for its implementation. [ABSTRACT FROM AUTHOR]

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The object of research is the process that forms strategies and methods for effective commercialization of intellectual products at industrial enterprises. The problems of introducing intellectual property objects into the economic circulation in the field of industrial production have been analyzed. The most important of them are economic and managerial problems, which consist in the lack of necessary funding and are determined by the difficulty of assessing the market competitiveness of an intellectual product. Special attention was paid to market, technical-technological, and legal problems, the presence of which inhibits the development of the technological market and significantly affects the efficiency of intellectual and innovative activities. The presence of these problems predetermined the main goal of the study – to devise methods and strategies for the commercialization of intellectual property objects. Three basic strategies for the commercialization of intellectual products have been studied: the strategy of promoting an intellectual product, the strategy of diffusion of innovations, and the strategy of accumulating maximum income. Based on them, an integrated strategy for the commercialization of intelligent products for enterprises of the machine-building industry, which is oriented towards achieving the goals of maximizing the economic and social effect of the production of an intelligent product, was formed and substantiated. The main component of an integrated strategy is an organizational mechanism that provides investment support for innovative activities and scientific and consulting support for an intellectual product. The research results could be used to form programs of intellectual and innovative activity of industrial enterprises and would serve as a basis for further scientific research on these issues. [ABSTRACT FROM AUTHOR]

This paper proposes new techniques for automatic simulation-based analog circuit synthesis using genetic algorithms. This is intended to contribute to the set of electronic design automation tools that use genetic algorithms in circuit synthesis, especially those that use the simulator-in-the-loop paradigm. In this study, a genetic algorithm was employed as the generation engine for analog circuits, and variable-length chromosomes were used to describe circuit topology. The entire process is carried out on a flat level (device level), i.e. using the transistor and other elementary devices (e.g. resistors) as the basic elementary blocks. Circuit synthesis is accomplished without any knowledge of previously defined topologies (or analog block cells). Three techniques are presented for analog circuit synthesis that are incorporated in the genetic algorithm, which contribute to its robustness, leading to better and faster results. These techniques can be summarized as follows: 1) adaptive probability of chromosome acceptance, 2) removal of redundant or useless components, and 3) segmented evolution. The automatic process starts with the circuit input and output specifications and proceeds with the evolution of both circuit topology and component sizing. The results shown in this paper include a 40 dB DC gain amplifier, which, when evaluated with SPECTRE/CADENCE 6.0, using a standard 130 nm technology, with a load capacitor of 10 pF, has a gain of 102 V/V, a GBW product of 70 MHz, and a figure of merit of 1436 MHz.pF/mW.

Millimeter-wave and Terahertz communications consist of complex analog and mixed-signal transceivers where overall system performance is often limited by the weakest performing subsystem. While analog and mixed-signal integrated circuits have significantly advanced, the future of 5G and 6G transceiver design could be accelerated by including artificial intelligence. In this combination, analog integrated circuit design and operation would harness machine learning to identify, characterize, and act upon variations and anomalies in system performance. Focusing on 5G and 6G, this paper investigates solutions for a unified intelligent integrated transceiver: a conceptual combination of a traditional analog subsystem, a supporting digital subsystem that enables artificial intelligence, and dedicated feedback circuitry or sensors that monitor performance, efficiency, or reliability. Active and passive components and propagation channels are reviewed based on their merits of introducing intelligence. Holistically and for broader applicability, the paper conceptualizes and coins the notion of an “intelligent integrated system (IIS)”, which brings forward a novel unified vision and approach toward context-aware subsystems that dynamically interact with ambient and varying operating conditions. To demonstrate viability, the paper concatenates a select set of measurement results.

Bus and register management is one of the crucial aspects of application-specific integrated circuit-, system-on-chip-, or field-programmable gate array-based designs. The problems related to it are well known, and multiple tools or approaches are already trying to solve or mitigate them. However, all available solutions share the same register-centric paradigm. A user defines registers and then manually lays out the data into the registers. Such an approach has its limitations. A description does not contain information on data spanning multiple registers or data forming a broader context, for example, procedure arguments. It also does not contain information on the purpose of the data. As a result, the generated access code is low-level and usually needs an extra wrapper, which leaves room for potential human mistakes. For instance, it is the user's responsibility to guarantee proper access order to registers or to provide an atomic change of data wider than a single register width. This article proposes a new approach, the functionality-centric approach. In the functionality-centric approach, the user defines the data with the type of their functionality. The registers and bus hierarchy are later implicitly inferred. By defining the functionality of the data placed in the registers, it is possible to generate more access code, increase code robustness, improve system design readability, and shorten the implementation process. [ABSTRACT FROM AUTHOR]

Today, the main concern of digital circuit designers is reducing the power of portable equipment due to the limitation of charging their batteries. One of the ways to reduce power consumption is to use approximate units in systems that have the ability to tolerate faults. Another solution to consider is designing circuits with Multi-Valued Logic (MVL), which can also reduce power consumption. The use of CNTFET transistors in MVL circuit designs can lead to higher efficiency in integrated circuits, particularly in terms of power, speed and area. Full adders are essential arithmetic modules in processors and serve as the cornerstone of digital systems. In this research study, we aimed to design an Approximate Ternary Full Adder (ATFA) with the minimum number of transistors and power consumption. Based on simulations conducted using Synopsys HSPICE in Stanford's 32 nm CNTFET technology, the proposed ATFA design demonstrated superior performance compared to previous similar designs, particularly in terms of average power consumption, delay, and energy consumption. In addition, according to the examination of noise immunity curves, the proposed circuit has higher pulse noise amplitude in all pulse widths than other circuits. Meanwhile, at the program level, image composition has been considered to study accuracy criteria such as peak Signal-to-Noise Ratio (PSNR), Structural Similarity (SSIM), and Figures Of Merit (FOM) in image synthesis, supported the superior performance of our proposed circuit compared to other similar circuits. [ABSTRACT FROM AUTHOR]

In this paper, two improved ultra-wideband (UWB) balanced power amplifiers based on the flip-chip system-in-package technique and electronic design automation (EDA) are proposed. The conventional approach to system-on-chip (SoC) involves integrating all sub-circuit designs into a single manufacturing process. However, in radio frequency circuits, adopting the SoC approach necessitates intricate matching designs, leading to an increase in development costs. In this study, two types of SiGe unit power amplifiers attempted to achieve a flat S21 response using simpler matching for input/output. The cascode architecture was adopted as the main structure for the first type of unit power amplifier (type I). Subsequently, the design of the second type unit power amplifier was built upon the foundation of the first type, with the only difference being the implementation of two parallel cascode structures (type II), and the primary goal is to enhance both gain and output power compared to the first type. In addition, for this second type unit power amplifier, in conjunction with a quadrature hybrid coupler, the optimal impedance matching value was selected to maintain the flatness of gain across the entire UWB range. Furthermore, the poor performance of S11,22 of these two types of unit power amplifiers was improved by using quadrature hybrid couplers using the WIPD process combined with EDA simulation. Therefore, using flip-chip packaging technology can effectively reduce the increased wafer fabrication costs caused by complex matching designs in active circuits. This improved system has the potential to offer a new practical application for UWB power amplifier design. [ABSTRACT FROM AUTHOR]

In this paper, a new design of a current mode instrumentation amplifier (CMIA) is presented using a single differential voltage extra-X current controlled current conveyor (DV-EXCCCII) and a grounded resistor. Therefore, this circuit design is very simple and suitable for IC integration. The proposed circuit of instrumentation amplifier has high output impedance so it is easily cascadable with other current mode circuits without buffer requirement. Furthermore, the proposed circuit is electronically tunable with the bias current of the active element used. This circuit offers good frequency performance with wide differential gain and CMRR bandwidth. The non-idealities and parasitic effects of the proposed circuit are also investigated. To validate the proposed instrumentation amplifier, various simulations are performed using the CADENCE VIRTUOSO SPECTRE simulator using 0.18 µm CMOS technology parameters. [ABSTRACT FROM AUTHOR]

As ICs scale up, a problem that arises at the lower levels of the plating system is that the resistance of the copper traces increases rapidly as the size decreases. This is due to the increase in the contribution of electron scattering on the surface and at grain boundaries. In addition, copper lines require fixed-thickness barrier layers to prevent copper from diffusing into the low-k dielectric. When the cross section of the tracks is reduced, the contribution of the barrier layers to the track resistance is excxii essively high. In addition, when the track width is less than 10 nm, the resistance of copper to electromigration is insufficient. Therefore, it is necessary to look for alternative materials to replace copper, which will provide strong resistance to electromigration and low track resistance. The most promising candidates are Ru, Mo, Rh, and Ir. The advantages and disadvantages of these materials are discussed in this study. [ABSTRACT FROM AUTHOR]

The growth of digital communications has driven the development of numerous cryptographic methods for secure data transfer and storage. The SHA-256 algorithm is a cryptographic hash function widely used for validating data authenticity, identity, and integrity. The inherent SHA-256 computational overhead has motivated the search for more efficient hardware solutions, such as application-specific integrated circuits (ASICs). This work presents a custom ASIC hardware accelerator for the SHA-256 algorithm entirely created using open-source electronic design automation tools. The integrated circuit was synthesized using SkyWater SKY130 130 nm process technology through the OpenLANE automated workflow. The proposed final design is compatible with 32-bit microcontrollers, has a total area of 104,585 µm2, and operates at a maximum clock frequency of 97.9 MHz. Several optimization configurations were tested and analyzed during the synthesis phase to enhance the performance of the final design. [ABSTRACT FROM AUTHOR]

Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds' Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of high-performance N-bit digital comparators for use in modern digital systems. Digital comparators are fundamental building blocks in many electronic systems, performing the critical task of comparing two digital values and generating an output indicating their relative magnitudes. For implementing N-bit digital comparator a new design for an 8T EX-OR-NOR cell with full rail-to-rail output swing has been proposed. The proposed EX-OR-NOR cell is based on the hybrid circuit utilizing CMOS inverter and transmission gate logics, which thereby uses less power and minimizes propagation delay. Thus, a high-speed N-bit digital comparator design is accomplished using the proposed 8T EX-OR-NOR cell. In the present work 4-bit to 32-bit digital comparators are designed and implemented using the proposed circuitry. All the circuits are designed using Cadence electronic design automation (EDA) Virtuoso Design Environment for 180nm CMOS technology node. The outcomes are evaluated and verified with the comparator designs reported in the literature. The proposed modified N-bit digital comparators provide an excellent combination of speed, power consumption, and accuracy, making them a promising solution for modern digital electronics systems. [ABSTRACT FROM AUTHOR]

Two‐dimensional material‐based field‐effect transistors (2DM‐FETs) are playing a revolutionary role in electronic devices. However, before electronic design automation (EDA) for 2DM‐FETs can be achieved, it remains necessary to determine how to incorporate contact transports into model. Reported methods compromise between physical intelligibility and model compactness due to the heterojunction nature. To address this, quasi‐Fermi‐level phase space theory (QFLPS) is generalized to incorporate contact transports using the Landauer formula. It turns out that the Landauer‐QFLPS model effectively overcomes the issue of concern. The proposed new formula can describe 2DM‐FETs with Schottky or Ohmic contacts with superior accuracy and efficiency over previous methods, especially when describing non‐monotonic drain conductance characteristics. A three‐bit threshold inverter quantizer (TIQ) circuit is fabricated using ambipolar black phosphorus and it is demonstrated that the model accurately predicts circuit performance. The model could be very effective and valuable in the development of 2DM‐FET‐based integrated circuits. [ABSTRACT FROM AUTHOR]

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing. [ABSTRACT FROM AUTHOR]

Droplet generation is a fundamental component of droplet microfluidics, compartmentalizing biological or chemical systems within a water-in-oil emulsion. As adoption of droplet microfluidics expands beyond expert labs or integrated devices, quality metrics are needed to contextualize the performance capabilities, improving the reproducibility and efficiency of operation. Here, we present two quality metrics for droplet generation: performance versatility, the operating range of a single device, and stability, the distance of a single operating point from a regime change. Both metrics were characterized in silico and validated experimentally using machine learning and rapid prototyping. These metrics were integrated into a design automation workflow, DAFD 2.0, which provides users with droplet generators of a desired performance that are versatile or flow stable. Versatile droplet generators with stable operating points accelerate the development of sophisticated devices by facilitating integration of other microfluidic components and improving the accuracy of design automation tools. [ABSTRACT FROM AUTHOR]

Reverse engineering (RE) in Integrated Circuits (IC) is a process in which one will attempt to extract the internals of an IC, extract the circuit structure, and determine the gate-level information of an IC. In general, the RE process can be done for validation as well as Intellectual Property (IP) stealing intentions. In addition, RE also facilitates different illicit activities such as the insertion of hardware Trojan, pirating, or counterfeiting a design, or developing an attack. In this work, we propose an approach to introduce cognitive perturbations, with the aid of adversarial machine learning, to the IC layout that could prevent the RE process from succeeding. We first construct a layer-by-layer image dataset of 45 nm predictive technology. With this dataset, we propose a conventional neural network model called RecoG-Net to recognize the logic gates, which is the first step in RE. RecoG-Net is successful in recognizing the gates with more than 99.7% accuracy. Our thwarting approach utilizes the concept of adversarial attack generation algorithms to generate perturbation. Unlike traditional adversarial attacks in machine learning, the perturbation generation needs to be highly constrained to meet the fab rules such as Design Rule Checking (DRC) Layout vs. Schematic (LVS) checks. Hence, we propose CAPTIVE as a constrained perturbation generation satisfying the DRC. The experiments show that the accuracy of reverse engineering using machine learning techniques can decrease from 100% to approximately 30% based on the adversary generator. [ABSTRACT FROM AUTHOR]

This paper aims to develop a novel hierarchical recursive nonsingular terminal sliding mode controller (HRNTSMC), which is designed to stabilize the inverted pendulum (IP). In contrast to existing hierarchical sliding mode controllers (HSMC), the HRNTSMC significantly reduces the chattering problem in control input and improves the convergence speed of errors. In the HRNTSMC design, the IP system is first decoupled into pendulum and cart subsystems. Subsequently, a recursive nonsingular terminal sliding mode controller (RNTSMC) surface is devised for each subsystem to enhance the error convergence rate and attenuate chattering effects. Following this design, the HRNTSMC surface is constructed by the linear combination of the RNTSMC surfaces. Ultimately, the control law of the HRNTSMC is synthesized using the Lyapunov theorem to ensure that the system states converge to zero within a finite time. By invoking disturbances estimation, a linear extended state observer (LESO) is developed for the IP system. To validate the effectiveness, simulation results, including comparison with a conventional hierarchical sliding mode control (CHSMC) and a hierarchical nonsingular terminal sliding mode control (HNTSMC) are presented. These results clearly showcase the excellent performance of this approach, which is characterized by its strong robustness, fast convergence, high tracking accuracy, and reduced chattering in control input. [ABSTRACT FROM AUTHOR]